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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-44f9696be17si5910631cf.12.2024.07.18.06.34.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jul 2024 06:34:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PaPA1wkT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sURG9-000362-UB; Thu, 18 Jul 2024 09:33:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sURG7-0002yO-RE for qemu-devel@nongnu.org; Thu, 18 Jul 2024 09:33:23 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sURG6-0008QT-9q for qemu-devel@nongnu.org; Thu, 18 Jul 2024 09:33:23 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4279c10a40eso2683525e9.3 for ; Thu, 18 Jul 2024 06:33:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721309601; x=1721914401; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2mso2QJcRmduCVnkl/10ds9MgeFytW7Y36v0Ku50nZ0=; b=PaPA1wkTj0d5sDOJdfOnFgctZJ+Tb4hhxsioSSaYCXX5zsTnH/9CNk8JbRzBw8WFMy N98rQjCg+an5rKAvyNb10jQuViZkpQJ9tTMyluKsxd4b3MQoWmEa+6X/NUDOtAu59tPg dvqwMwUl1PbZ6y52BDB6b6E7rfkKoDejyvfnPawltuKQ82CyXEcFYrPwXhQtkzb1wvZh 8o5l8vyGxxmWRAYDVwUYKbF/opQV8PtQHjQONhV5uCRS9jKmabeaS3fkW5P217uorvN1 hjoyz7IMKstV4sCqnC1K4mfOpQbhZVpe7y08DVzEF3RwiyyNsCpsYX3Cw8EU/JqSEdy8 Y6OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721309601; x=1721914401; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2mso2QJcRmduCVnkl/10ds9MgeFytW7Y36v0Ku50nZ0=; b=rgneGXkQditl5sfBHiSA5U37ShHkkv3SldazjN8QkeS+X0mAN//o48fM4NfqcN2nyo MA4Bct+3b5vvgEavacxZLCpmwqyFWC79aB6CmjUac9CkxXrVktQvroj1uZhHHNsaOkJA 60YUHsr/d532JdrFpo5GCtQ1b9YwmB+fKuMnmYEzMfFyt9lhsGo1pUtC9VfIHZNk6hvb ybwQD55qOkxBd343VxkuAHtr/m7L/RrLAxjUmSH3oeHbw4kPWsUrwSxLUW/+DO4+t9O6 Lu4pUOPExtkM8qSaR3Bg5OpOh1Y783NAe1fgtZmDfip33eHyE1hYgc4RmkKS/M2UiGDR FC5Q== X-Forwarded-Encrypted: i=1; AJvYcCWG1v2BpOncexuC/0JK3pOkc99xZABVo15fQ5nhWBX0pAaPq2S0c34m1nCTNaCXU26GcbeD6DBu8nDDENq94MKah4havGY= X-Gm-Message-State: AOJu0Yyg7ikIMAGb9DaHtb6pJwQAl77Wr/kttJnMAHc4eVkO5nVtWVUi AwT4XTu27k0CR67QGvr8f0z78ShZ6JSppkKe5WBHjEnL71+tM/WMy09JqQgy6m8= X-Received: by 2002:a05:600c:314d:b0:426:616e:db8d with SMTP id 5b1f17b1804b1-427c2ca9b13mr31097455e9.15.1721309600733; Thu, 18 Jul 2024 06:33:20 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2b1815esm13685285e9.13.2024.07.18.06.33.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:33:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 01/19] hw/intc/loongson_ipi: Declare QOM types using DEFINE_TYPES() macro Date: Thu, 18 Jul 2024 15:32:53 +0200 Message-ID: <20240718133312.10324-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. Replace the type_init() / type_register_static() combination. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Song Gao --- hw/intc/loongson_ipi.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index e6a7142480..dc82caea0d 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -363,17 +363,14 @@ static void loongson_ipi_finalize(Object *obj) g_free(s->cpu); } -static const TypeInfo loongson_ipi_info = { - .name = TYPE_LOONGSON_IPI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPI), - .class_init = loongson_ipi_class_init, - .instance_finalize = loongson_ipi_finalize, +static const TypeInfo loongson_ipi_types[] = { + { + .name = TYPE_LOONGSON_IPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(LoongsonIPI), + .class_init = loongson_ipi_class_init, + .instance_finalize = loongson_ipi_finalize, + } }; -static void loongson_ipi_register_types(void) -{ - type_register_static(&loongson_ipi_info); -} - -type_init(loongson_ipi_register_types) +DEFINE_TYPES(loongson_ipi_types) From patchwork Thu Jul 18 13:32:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813213 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp297389wro; Thu, 18 Jul 2024 06:36:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWrEvC/Hw4AhrVURGOQ8nSfaWMqHtiTwvainRgQg8bLUATiuEecBM9IXrqP7xqtcLODWM6mnH42/d0j+Yrgg7fn X-Google-Smtp-Source: AGHT+IFN9XBgFACsR5Xz6G02lnV+BtbPujGwoq8aCMwfPUHNT7nZNnclmj2hDYOE0bpVJBk+AxTE X-Received: by 2002:a05:690c:460d:b0:65f:e113:bb7e with SMTP id 00721157ae682-6660229a195mr31974007b3.25.1721309790450; Thu, 18 Jul 2024 06:36:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309790; cv=none; d=google.com; s=arc-20160816; b=FRYKl3Dvwr2IVfaMKhze3iHit4unGQMfzjkTwpCIuz27liHMtWg3c/MT6uW5xtl8jw jCBft2Be3XXvOr4740UX2ik5YDApI4+bO7cAtAcyBtihMhuCq3lW6exsBBtWTypfYjw2 jnOcqRU+0xJhI//Vz46emqxboNcsAH7YWLI1+O3rRAZaNVLRKNYrOfJTT+IIGL0STLDW RjlToIserZho/tgbdeKw7IvnUv1ZX4bHKWtFF1ynHFUMIxbwrS6sKzhRnm22PqNLDRje ZHdZHmX30zYJg6JNWqKw/gM/GDrZyem1eygOCzHOvuAd+E1M5CmCySbuILjSkP4R5OBP 9JHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ms4f5OfzFZYNwxaY7U7GVqyRgrfCUCWkkMxGuFg0vIE=; fh=iuHf7rvDXJbzLPuk/W6rlRFjI1pAjhek+aCHF14vtLQ=; b=es55o9nOIT/kziXrt79cuHhJaFG1i/raoeeUJ2B9HRCM8nW6xdyi1FhNgBSHV2pfOX KlSBNHnIkEU+qVF/tV2cQJSHq7c8o5/SqLRXP7QguPSbmW2TiJiUBPllpvcMCMuV2SDk GXned/vq+8l+zn83RhOp3oa+9Nng4LHJgS36N4DzrY38EihEBAqA49g5wr8FKW4q+9iJ WucqlUOht6tGxpQ5jtMIBcpdJddQ1f+ebaq+A9feNf3NQ0zq+9edPQ/DZ4/iSeRj1fGN 4nJMUHBX4GvRlRbKUceDYFJ7IANuGBWgdcJyx02FsHnAgRKdgiMf1V6MCk+FUszx2Q5+ eF5g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L4spQmzb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support") [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- hw/intc/loongson_ipi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index dc82caea0d..d315f6f303 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "exec/address-spaces.h" +#include "exec/memory.h" #include "migration/vmstate.h" #ifdef TARGET_LOONGARCH64 #include "target/loongarch/cpu.h" @@ -102,7 +103,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, * if the mask is 0, we need not to do anything. */ if ((val >> 27) & 0xf) { - data = address_space_ldl(iocsr_as, addr, attrs, NULL); + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); for (i = 0; i < 4; i++) { /* get mask for byte writing */ if (val & (0x1 << (27 + i))) { @@ -113,7 +114,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, data &= mask; data |= (val >> 32) & ~mask; - address_space_stl(iocsr_as, addr, data, attrs, NULL); + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); return MEMTX_OK; } From patchwork Thu Jul 18 13:32:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813195 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296178wro; Thu, 18 Jul 2024 06:34:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXcQjbL9fi5OiizWNkYXqDbHtDJqIcRuYcqlZiyXzZ0eMlz0SbCopoxomDCCWsRZItxq5mHkEDlC25UmMrJ7HIx X-Google-Smtp-Source: AGHT+IHchBQzt+h7Ti1YRXl6fmbrTKHBsGc9LaU8vXV54/LwecmpaVIBj1uznyU0jPWLa2Eaf6iQ X-Received: by 2002:a05:620a:2484:b0:79f:436:7e3a with SMTP id af79cd13be357-7a1874fe0a5mr538056085a.48.1721309643838; Thu, 18 Jul 2024 06:34:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309643; cv=none; d=google.com; s=arc-20160816; b=tDVa+0RtHJkWlolxpbc9m8NQKZ7CH4DOQdc4UOuWXeTtUHS7rMZRUHAXnP1WR97NP2 PzZz/X81P5aK93Oo9tbGfZ4dePWohxHg9lSLiFo78ulxKPFpGdckLsB1LSt6Sp2pd9am JwDUFYUhx7ooKzq+9tk/CvMb1r4e+zwA/ALNj4pmnWbPOm4euCyMb4wIZtT1LkN/Dj09 qGc3CA0cxP4fNGbr8W2cH+AH29yGJNMc0zVoeJiN/UGjJDq9XUVv/7Y/g1Q8U7nfUm++ oGQvpGXdblZKT32w0LYWxeT7k2g5gvW4OQ5i83EUU7AjWuPJT+qcW1PNJYXxVg0CeZ+b 2vxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1X1N1UHwRToEvVtdtgPiuXjRXuRHL3MityADuWCMGFA=; fh=mbud3nYnGXuGYoBAA4PA3rW8FDQ+J8eilHIrZEKOPoE=; b=TNgTglXrgjkvKzoQDnG3hm0QoVrhyKsSTm6OPwrShpPLScDYZFKXD+17rfwotEgsOI N2QPAcYvouOQ4GreTTnkwdmG2ZFIqRiAf/xe+8fr/SC3D8PqODhGhvNa8nUbvSO3sfQc Gy05v4bzrxOQhAaEZ0tl7Ohjuws3SssIsRBwtJ76sGmgeIFiE5xODlkpn0lDb7rx7D9l BqkjXH8dTSAVCkEOj8mwg4VTX5LvGMQvdpuust4T4va7CLDvkVxK7mzqxJX3aKcoY86H lsYTRtRI/lc+ejzyrFVZYLI8/biLxbTt2uzpMZ1Frj85bniEICfc8DE8zf4l0PyMaHFz 9d4A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qCfKJTkF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/intc/loongson_ipi.h | 6 +++--- hw/intc/loongson_ipi.c | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 3f795edbf3..efb772f384 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -31,10 +31,10 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI) +OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) typedef struct IPICore { - LoongsonIPI *ipi; + LoongsonIPIState *ipi; MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; @@ -45,7 +45,7 @@ typedef struct IPICore { qemu_irq irq; } IPICore; -struct LoongsonIPI { +struct LoongsonIPIState { SysBusDevice parent_obj; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index d315f6f303..d870af39c1 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPI *ipi = s->ipi; + LoongsonIPIState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_realize(DeviceState *dev, Error **errp) { - LoongsonIPI *s = LOONGSON_IPI(dev); + LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -337,14 +337,14 @@ static const VMStateDescription vmstate_loongson_ipi = { .version_id = 2, .minimum_version_id = 2, .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu, + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, vmstate_ipi_core, IPICore), VMSTATE_END_OF_LIST() } }; static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1), + DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -359,7 +359,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) static void loongson_ipi_finalize(Object *obj) { - LoongsonIPI *s = LOONGSON_IPI(obj); + LoongsonIPIState *s = LOONGSON_IPI(obj); g_free(s->cpu); } @@ -368,7 +368,7 @@ static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPI), + .instance_size = sizeof(LoongsonIPIState), .class_init = loongson_ipi_class_init, .instance_finalize = loongson_ipi_finalize, } From patchwork Thu Jul 18 13:32:56 2024 Content-Type: text/plain; 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- hw/intc/loongson_ipi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index d870af39c1..960d1e604f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -357,13 +357,18 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_loongson_ipi; } -static void loongson_ipi_finalize(Object *obj) +static void loongson_ipi_common_finalize(Object *obj) { LoongsonIPIState *s = LOONGSON_IPI(obj); g_free(s->cpu); } +static void loongson_ipi_finalize(Object *obj) +{ + loongson_ipi_common_finalize(obj); +} + static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, From patchwork Thu Jul 18 13:32:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813198 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296345wro; Thu, 18 Jul 2024 06:34:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXdjSLr7pVU3fFOFbcVHPrjaKMKi8Gd3+w74I7ZGJON22kxwynpx9kjoAYlbNGHlYB7kNHfOfs3hJ2Ks7VibZZO X-Google-Smtp-Source: AGHT+IEibew8sVzjm1+a1RRIjWmAWOJcu+iin9v/DkfLxShP3NfGYLE8Ugp3/RKrFvYy1YvKo1mv X-Received: by 2002:a05:6122:3d10:b0:4ef:5a4c:ab5e with SMTP id 71dfb90a1353d-4f4df688316mr6450953e0c.5.1721309659384; Thu, 18 Jul 2024 06:34:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309659; cv=none; d=google.com; s=arc-20160816; b=Lu8vS8ChtrjukaFStdOXSJUg4s38xCSbRoFjM/vaDbMN8ZLiMdmCyFRhkKvLUu+SXm lBJASoMgwNA3dbqKxGggiKuslFV8vSbrUOz/JDV42fsvkWGyJlsFRfqIHIyuuUX4sS2n tFwgIhg0cTSY+UFWFZIwodvMJKdhq9dAczRPWRhD0LlLkaxYLqRP7uCs+8HKd6kbnQpm jTl7Or3QssOIvvKXkV5r4YIf04eVIiHDB6DzuSG/yzaHVtGMBJ9Exx926HS0d2R1VwbS oahQwNiVImOzLGVu/0OTAtN7pbT0dr3BcOxBbJvcfxc9zYx8zfOzxrSlIYSeErHw53Am 595w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dJ1Jzmp+9J5R2QdMsXruspBz2Qg6XytMsq9xTnRszl0=; fh=Ma3NITrTLTG+PofQVfaX8SyzK2cu8WMhBV0JvV/fBpU=; b=aW/siqvXweHwYG4w9GSZyDlhwdRGkSsj1pIqKnJnrU+PYI+zTFTMGHtIPNes6ROvNA Z/wnnMvV9xIMWj31xE/q4ryKCb6h0zNHC7Uolq4ixxa1/jNLlRRX0lAzlJXCoBZuAGo/ oItCxoHhA0dh+Lwoe/ralK57vGwS2OraEFy2DTqsKEQivKzt4+n1DJImndTII+V6zNZL YQ6wu9prAgZomgdqpL7uS4xVbu5Kit8/VJqzOZBPfCM8UHJ4i9qZ66EnsvHXkpv1HB7b huKHGv/+EWvHZoanUN0eeUFzB8ZviG9HesAcU2oRAUgceJ5EKBkMu2JqvOvSROOpXQbh vnWw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ieHRK1T5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- hw/intc/loongson_ipi.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 960d1e604f..bab4d8816b 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void loongson_ipi_realize(DeviceState *dev, Error **errp) +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -301,20 +301,31 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); s->cpu = g_new0(IPICore, s->num_cpu); - if (s->cpu == NULL) { - error_setg(errp, "Memory allocation for IPICore faile"); + for (i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi = s; + + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} + +static void loongson_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPIState *s = LOONGSON_IPI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + Error *local_err = NULL; + + loongson_ipi_common_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); return; } - for (i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi = s; + for (unsigned i = 0; i < s->num_cpu; i++) { s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); } } From patchwork Thu Jul 18 13:32:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813197 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296310wro; Thu, 18 Jul 2024 06:34:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCViKGVIV0eGO4Pq/pOUvV0A7SgFtYIkvuQqwAT9u0owzpeFqwLntX1R4EUIcIMR/yrIWcXRpC/qGMipPk0UQR4j X-Google-Smtp-Source: AGHT+IGf6o5Q0yX1uhnes4VJLgf4f3feRKdG1ZYVckgeE8i/WW3lwzgPXp0gImlo1f4kuCzGtpWF X-Received: by 2002:a05:6808:1441:b0:3d9:29c1:be41 with SMTP id 5614622812f47-3dad1f3f4e6mr6395671b6e.10.1721309657651; Thu, 18 Jul 2024 06:34:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309657; cv=none; d=google.com; s=arc-20160816; b=t23z8O/KKo8VsQWbIqR7sVT6+DavXN10tAkvI1X7KeI+M7odw5rX3dAwFKrXZRfDHa xgsf7loZ052IxPgMVW3Gv+cFsTv0sSGub32VMXAXR/pMbZcv64LXPIDiUFT85aMj6kvF zzVHSI9U+O0wIr8jnJMx6jfmyfmzC3OhCg8++wdvFTnwTPF/yYm0a2U3Rwo9uhWv0TcM jlsNGWIrXN954zcAKEHzZXg4Sy5/hMSFsS5fozakECw5lxxQ8cGzudQ1MYkfjnjIxELB LSYuEJbwuEOvLOv9kaNwJjx8XiU0/a5cBK2OPRu4V3Wl5J4VvlYJECh8NH6z7dqna9Ya RQyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oPF3lpjwa8azmyfI5pemrpn1QlX/iiaQsFcCFwFBaHY=; fh=Ap/CuDuL+6s5hXHC1a4E2B9t0UbV8ioY5BZc/p/T0Ao=; b=rtseTS1YDMXjvFp2jvmys9y3tgR2rlqQXV0VhmgWDLWwFSpyiLppTt1QX7eCoGUYtD 2Ba538rEyRAbL7LiXt6S5mAsMwcXCW12k/ZxKszRgMeFFxUPGyIrRbtoGPuu0ynQbyEn KSDB9bZqZPbqh0Uno/uFE0sBWUQfIgt0TVYBZ/vKGBKO11gHW2UVt1/JVG4XJF/r+GGD fkw7lJkj5slnJ+HBJO34nzXuiGr2u4uoWdaq5I/c/wSv/8KP/8QN+lXS63111mJpKeD4 Ar3gF8wT5b2a2/haG4TZoJE1X+g7PdXP9f01LRNOy9+t+jlVGBrTYLXmL19+Lqbxu3vI kzug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e8TBg+MV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- MAINTAINERS | 4 ++++ include/hw/intc/loongson_ipi.h | 13 +++++++++++-- include/hw/intc/loongson_ipi_common.h | 26 ++++++++++++++++++++++++++ hw/intc/loongson_ipi.c | 7 ++++--- hw/intc/loongson_ipi_common.c | 22 ++++++++++++++++++++++ hw/intc/Kconfig | 4 ++++ hw/intc/meson.build | 1 + 7 files changed, 72 insertions(+), 5 deletions(-) create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongson_ipi_common.c diff --git a/MAINTAINERS b/MAINTAINERS index 7d9811458c..a670c8ee67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1249,8 +1249,10 @@ F: configs/devices/loongarch64-softmmu/default.mak F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c @@ -1385,11 +1387,13 @@ Loongson-3 virtual platforms M: Huacai Chen R: Jiaxun Yang S: Maintained +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: hw/intc/loongson_liointc.c F: hw/mips/loongson3_bootp.c F: hw/mips/loongson3_bootp.h F: hw/mips/loongson3_virt.c +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: include/hw/intc/loongson_liointc.h F: tests/avocado/machine_mips_loongson3v.py diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index efb772f384..82cb64ca40 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -8,6 +8,8 @@ #ifndef HW_LOONGSON_IPI_H #define HW_LOONGSON_IPI_H +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" /* Mainy used by iocsr read and write */ @@ -31,7 +33,7 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) +OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; @@ -45,8 +47,15 @@ typedef struct IPICore { qemu_irq irq; } IPICore; +struct LoongsonIPIClass { + LoongsonIPICommonClass parent_class; + + DeviceRealize parent_realize; +}; + struct LoongsonIPIState { - SysBusDevice parent_obj; + LoongsonIPICommonState parent_obj; + MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h new file mode 100644 index 0000000000..70ac69d0ba --- /dev/null +++ b/include/hw/intc/loongson_ipi_common.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson ipi interrupt header files + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGSON_IPI_COMMON_H +#define HW_LOONGSON_IPI_COMMON_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" +OBJECT_DECLARE_TYPE(LoongsonIPICommonState, + LoongsonIPICommonClass, LOONGSON_IPI_COMMON) + +struct LoongsonIPICommonState { + SysBusDevice parent_obj; +}; + +struct LoongsonIPICommonClass { + SysBusDeviceClass parent_class; +}; + +#endif diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index bab4d8816b..20f3f6bd3f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -362,8 +362,10 @@ static Property ipi_properties[] = { static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); - dc->realize = loongson_ipi_realize; + device_class_set_parent_realize(dc, loongson_ipi_realize, + &lic->parent_realize); device_class_set_props(dc, ipi_properties); dc->vmsd = &vmstate_loongson_ipi; } @@ -383,8 +385,7 @@ static void loongson_ipi_finalize(Object *obj) static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPIState), + .parent = TYPE_LOONGSON_IPI_COMMON, .class_init = loongson_ipi_class_init, .instance_finalize = loongson_ipi_finalize, } diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c new file mode 100644 index 0000000000..970525c242 --- /dev/null +++ b/hw/intc/loongson_ipi_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson IPI interrupt common support + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/intc/loongson_ipi_common.h" + +static const TypeInfo loongarch_ipi_types[] = { + { + .name = TYPE_LOONGSON_IPI_COMMON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(LoongsonIPICommonState), + .class_size = sizeof(LoongsonIPICommonClass), + .abstract = true, + } +}; + +DEFINE_TYPES(loongarch_ipi_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 58b6d3a710..a2a0fdca85 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -87,8 +87,12 @@ config GOLDFISH_PIC config M68K_IRQC bool +config LOONGSON_IPI_COMMON + bool + config LOONGSON_IPI bool + select LOONGSON_IPI_COMMON config LOONGARCH_PCH_PIC bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index afd1aa51ee..a09a527207 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -69,6 +69,7 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) From patchwork Thu Jul 18 13:32:59 2024 Content-Type: text/plain; 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Thu, 18 Jul 2024 06:33:55 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3680daccacdsm14337586f8f.62.2024.07.18.06.33.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:33:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 07/19] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h Date: Thu, 18 Jul 2024 15:32:59 +0200 Message-ID: <20240718133312.10324-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/intc/loongson_ipi.h | 18 ------------------ include/hw/intc/loongson_ipi_common.h | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 82cb64ca40..d53bd5dcfe 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,24 +12,6 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -/* Mainy used by iocsr read and write */ -#define SMP_IPI_MAILBOX 0x1000ULL -#define CORE_STATUS_OFF 0x0 -#define CORE_EN_OFF 0x4 -#define CORE_SET_OFF 0x8 -#define CORE_CLEAR_OFF 0xc -#define CORE_BUF_20 0x20 -#define CORE_BUF_28 0x28 -#define CORE_BUF_30 0x30 -#define CORE_BUF_38 0x38 -#define IOCSR_IPI_SEND 0x40 -#define IOCSR_MAIL_SEND 0x48 -#define IOCSR_ANY_SEND 0x158 - -#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) -#define MAIL_SEND_OFFSET 0 -#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) - #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 70ac69d0ba..b43b77bda6 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -23,4 +23,23 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; }; +/* Mainy used by iocsr read and write */ +#define SMP_IPI_MAILBOX 0x1000ULL + +#define CORE_STATUS_OFF 0x0 +#define CORE_EN_OFF 0x4 +#define CORE_SET_OFF 0x8 +#define CORE_CLEAR_OFF 0xc +#define CORE_BUF_20 0x20 +#define CORE_BUF_28 0x28 +#define CORE_BUF_30 0x30 +#define CORE_BUF_38 0x38 +#define IOCSR_IPI_SEND 0x40 +#define IOCSR_MAIL_SEND 0x48 +#define IOCSR_ANY_SEND 0x158 + +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) + #endif From patchwork Thu Jul 18 13:33:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813205 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296730wro; Thu, 18 Jul 2024 06:35:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU5wHy5udrGkPn37OK211U+4FR0UysW4QzuAcpTAmE9y//XIt38MtjyA9in1zRd86IUerhZikpGMg++SV9AF6I8 X-Google-Smtp-Source: AGHT+IGL4tUuNosCN4TS5vvT6sy/wz++QMwoU81p6Gm/LUFRzRJmwtOqNqH84ajyMHb0LYCKnRfj X-Received: by 2002:a05:690c:6608:b0:65f:80ed:683e with SMTP id 00721157ae682-6660360d337mr41998227b3.2.1721309702115; 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/intc/loongson_ipi.h | 2 +- hw/intc/loongson_ipi.c | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index d53bd5dcfe..00a65a82fb 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; - MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; uint32_t set; @@ -38,6 +37,7 @@ struct LoongsonIPIClass { struct LoongsonIPIState { LoongsonIPICommonState parent_obj; + MemoryRegion *ipi_mmio_mem; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 20f3f6bd3f..2319aea18f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } + s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); for (unsigned i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } @@ -379,6 +379,9 @@ static void loongson_ipi_common_finalize(Object *obj) static void loongson_ipi_finalize(Object *obj) { + LoongsonIPIState *s = LOONGSON_IPI(obj); + + g_free(s->ipi_mmio_mem); loongson_ipi_common_finalize(obj); } From patchwork Thu Jul 18 13:33:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813202 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296662wro; Thu, 18 Jul 2024 06:34:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUhnDajJKXG7L648DhZj7fEtSbIF/1YMWbz1dS98oG4C4TeFImkwcN2dIGcOOaGdExmMzc+Uu2twPB6NKvLKnDf X-Google-Smtp-Source: AGHT+IFqy4A/Y5zP+mXGdFMOheXfZxxHGgjlRpSVgKGdMV5o/WHz8b7HPIUSfOLe8y+aKZ4FF3ZM X-Received: by 2002:a05:620a:4095:b0:79e:fcb5:55e2 with SMTP id af79cd13be357-7a187441635mr586896685a.5.1721309694197; Thu, 18 Jul 2024 06:34:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309694; cv=none; d=google.com; s=arc-20160816; b=qLPcvi6eWrFfb08FoEKU6VCklbaTHh91/p4i+BoQGekgkKTBC10xzfX2UOH+RZnvgY XCGM5Nnp+Bh7eY7srwUl1mIB/AE0xO0HkU+ALEdk9FVD5bwCtLyzfNtMDO20qz+4Jfqj uzCqblGEFRCdxyoVTM4MlK5BSMALLhHRAdlfAKPMLlb6svPd/jaseNyqSD0tt6Ils61y hTNz5aUOMxy/hXEAM8Dq8VfbMLW2G6sE60YKSnD0CoJ8PX+LgP1sy93FZqXG5HHK/qSL Yp1ELJ1Ooj/tVQ4d3zQl+5izOQxAPB1Bdlu+5kAxcFUY7waboWgrfbxv6hi6XkfFWGSn LvMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=N5/k8L384L3wuw6eUDlmJEyK1Cofx+7INGx2FWPkB4s=; fh=4QNqASrmkA9zTjQxyx+rn6Xu7HPzqgN8XHg+AfOVGYg=; b=IzE74+wAgq4s7e1T9PHjcLrzVG/2v97bV3ZwstLq9DYaW6jxWJ23bPFvyBHzB6QRwp 3KjtQxybe3iB0Va8z6n5jpZEZCANMi21XlcjrgHN2i/jYOn2nr7WLPa/WDPz+39IlBkj QIh2ZQ66FmZUDoMbFnZrwmum93lmrcRIudLDCFwVSOr9fNaDryef49BEV5b+m5+sgH/r o6sJG+LoQDCSj7VYlf4cInTokziHeRF1nq9pR8tekonc89AbkA9bKseBcHQWitpPVKkk TnUL5RZupFe/5QYl2iYKvHAWH1fjrN3CZu5CrycDv7hAggkyDpz8IM6QAkdmCkowpG0C 17Sw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J54g9hVI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/intc/loongson_ipi.h | 17 -------- include/hw/intc/loongson_ipi_common.h | 18 +++++++++ hw/intc/loongson_ipi.c | 56 +++++---------------------- hw/intc/loongson_ipi_common.c | 50 ++++++++++++++++++++++++ 4 files changed, 77 insertions(+), 64 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 00a65a82fb..bb55899991 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,22 +12,9 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -#define IPI_MBX_NUM 4 - #define TYPE_LOONGSON_IPI "loongson_ipi" OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) -typedef struct IPICore { - LoongsonIPIState *ipi; - uint32_t status; - uint32_t en; - uint32_t set; - uint32_t clear; - /* 64bit buf divide into 2 32bit buf */ - uint32_t buf[IPI_MBX_NUM * 2]; - qemu_irq irq; -} IPICore; - struct LoongsonIPIClass { LoongsonIPICommonClass parent_class; @@ -38,10 +25,6 @@ struct LoongsonIPIState { LoongsonIPICommonState parent_obj; MemoryRegion *ipi_mmio_mem; - MemoryRegion ipi_iocsr_mem; - MemoryRegion ipi64_iocsr_mem; - uint32_t num_cpu; - IPICore *cpu; }; #endif diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index b43b77bda6..891b43644d 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -11,12 +11,30 @@ #include "qom/object.h" #include "hw/sysbus.h" +#define IPI_MBX_NUM 4 + #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" OBJECT_DECLARE_TYPE(LoongsonIPICommonState, LoongsonIPICommonClass, LOONGSON_IPI_COMMON) +typedef struct IPICore { + LoongsonIPICommonState *ipi; + uint32_t status; + uint32_t en; + uint32_t set; + uint32_t clear; + /* 64bit buf divide into 2 32bit buf */ + uint32_t buf[IPI_MBX_NUM * 2]; + qemu_irq irq; +} IPICore; + struct LoongsonIPICommonState { SysBusDevice parent_obj; + + MemoryRegion ipi_iocsr_mem; + MemoryRegion ipi64_iocsr_mem; + uint32_t num_cpu; + IPICore *cpu; }; struct LoongsonIPICommonClass { diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 2319aea18f..f3d1f031bc 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPIState *ipi = s->ipi; + LoongsonIPICommonState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { - LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) static void loongson_ipi_realize(DeviceState *dev, Error **errp) { + LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; @@ -320,45 +321,16 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } - s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); - for (unsigned i = 0; i < s->num_cpu; i++) { + s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu); + for (unsigned i = 0; i < sc->num_cpu; i++) { g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); + &loongson_ipi_core_ops, &sc->cpu[i], name, 0x48); sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } -static const VMStateDescription vmstate_ipi_core = { - .name = "ipi-single", - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_UINT32(status, IPICore), - VMSTATE_UINT32(en, IPICore), - VMSTATE_UINT32(set, IPICore), - VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_loongson_ipi = { - .name = TYPE_LOONGSON_IPI, - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, - vmstate_ipi_core, IPICore), - VMSTATE_END_OF_LIST() - } -}; - -static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -366,15 +338,6 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) device_class_set_parent_realize(dc, loongson_ipi_realize, &lic->parent_realize); - device_class_set_props(dc, ipi_properties); - dc->vmsd = &vmstate_loongson_ipi; -} - -static void loongson_ipi_common_finalize(Object *obj) -{ - LoongsonIPIState *s = LOONGSON_IPI(obj); - - g_free(s->cpu); } static void loongson_ipi_finalize(Object *obj) @@ -382,7 +345,6 @@ static void loongson_ipi_finalize(Object *obj) LoongsonIPIState *s = LOONGSON_IPI(obj); g_free(s->ipi_mmio_mem); - loongson_ipi_common_finalize(obj); } static const TypeInfo loongson_ipi_types[] = { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 970525c242..cc49896b2d 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,6 +8,54 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +static void loongson_ipi_common_finalize(Object *obj) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(obj); + + g_free(s->cpu); +} + +static const VMStateDescription vmstate_ipi_core = { + .name = "ipi-single", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_UINT32(status, IPICore), + VMSTATE_UINT32(en, IPICore), + VMSTATE_UINT32(set, IPICore), + VMSTATE_UINT32(clear, IPICore), + VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_loongson_ipi = { + .name = "loongson_ipi", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState, + num_cpu, vmstate_ipi_core, + IPICore), + VMSTATE_END_OF_LIST() + } +}; + +static Property ipi_properties[] = { + DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_props(dc, ipi_properties); + dc->vmsd = &vmstate_loongson_ipi; +} static const TypeInfo loongarch_ipi_types[] = { { @@ -15,6 +63,8 @@ static const TypeInfo loongarch_ipi_types[] = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(LoongsonIPICommonState), .class_size = sizeof(LoongsonIPICommonClass), + .class_init = loongson_ipi_common_class_init, + .instance_finalize = loongson_ipi_common_finalize, .abstract = true, } }; From patchwork Thu Jul 18 13:33:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813200 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296418wro; Thu, 18 Jul 2024 06:34:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUdxpAf6VJMy4vLZC53mo8LcpCinSY0aeLffxOqNl57reUxT+ZfNmyNkMESyW41FankdWNBIGHJgAKZSRL5Yhae X-Google-Smtp-Source: AGHT+IH2j1XHKRSWCakKQ/CzxcJeLyj3wY2t8uALQYCPWefDO+aGgFKrf9UsUxe+Vo7YXOIVSmUv X-Received: by 2002:a05:620a:4012:b0:79f:e9a:5ae5 with SMTP id af79cd13be357-7a19398e46bmr100229485a.60.1721309665190; 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- hw/intc/loongson_ipi.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index f3d1f031bc..a54db87638 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) return NULL; } -static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, - MemTxAttrs attrs) +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) { int i, mask = 0, data = 0; AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); @@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, return MEMTX_OK; } -static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = val & 0xffff; attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, @@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = { static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { + LoongsonIPICommonState *ipi = opaque; MemTxResult ret = MEMTX_OK; addr &= 0xfff; switch (addr) { case MAIL_SEND_OFFSET: - ret = mail_send(val, attrs); + ret = mail_send(ipi, val, attrs); break; case ANY_SEND_OFFSET: - ret = any_send(val, attrs); + ret = any_send(ipi, val, attrs); break; default: break; From patchwork Thu Jul 18 13:33:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813207 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296954wro; Thu, 18 Jul 2024 06:35:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVs2WgbarlOg8aFyCs2usyhY3BRQ6PHHL9TPw0XjxzQp2AhsF5f/t4uSJwm9sabrniXNOwHbTvDdlZn/Lu1nWmf X-Google-Smtp-Source: AGHT+IH3/v1rCR4HeNrfcpjc4bmXXUCpllpgTRfLCO1X3wGoY060cGPHuqk5wd/oEqFFSEk+Ym9+ X-Received: by 2002:a05:690c:60c5:b0:64b:4f90:ced1 with SMTP id 00721157ae682-66601ccc044mr38343267b3.12.1721309731365; Thu, 18 Jul 2024 06:35:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309731; cv=none; d=google.com; s=arc-20160816; b=aXvT3er5OWHBTLsErsMwtXwo5yJ4P0AzdS8D3gKPVctRgJUWfWsFi8vlR/9vZSxuTn wfsFwxZ0mkAXAVIHNuUfzo3B159jD/0ZC4w8sTXuWYzMmE86xOXSkIx5dR9Ks1neg+Wa o37d8X63ZvS9tIwQjEbQZ35zQla+9HI0NaF/Qd/Sm6JVBIgp5l7E9M2chy6Mx/F5IX+I +WMMKns4csYQXIGpaY+DDJxalf+CqjqPInQn67yIMq6Ofgsqn2STNr7TqbxyDQRGGQMF lsf3zFONEjKddTJWdUUFgFbAcvEWd25yuxOh3UzoXPPM8c0p8r0dXI84GP0ce3B9vJH4 vQQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=k6Hx2eTtFNzw/hpMI15i/HZcqpokYYD9kQA6KJM/AwE=; fh=ZlZBqXKkNKem03kc4jDAJ7ucYhwGchF2HlwWQ2aIe48=; b=LG6vPyO+XoPOKE0T40MsdTMaBMeraRUYvxapFSOabWJH/UusmiRTIdNVUgoYDTvrhF 6Y/sihBvz5wexr7Pz619hC58baROHn4o2PTxuaV8BCvAd+rHqptYhbLnU2D5GnFj4CK+ s0PGjkA0hJJ3zSR0Zfiivl+wkmuWCBxlGzf73E1097EgzmyMykNo53MTjtQl/5wW+haE r5yNOZr18LHmHkuxvbHPanrsAGe/8B6d0MGqe1RlcEiR27hN9zLFdHn8H2aHvLPWSeru Q8W5t0dyTRpFlmP1evRoab9vAH6wShot1WRu/jZ3C69YpLTMiQxP9r1Vub4MBUT82ZYi TK7Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uwy4A7TL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-44f9696ba90si5778701cf.87.2024.07.18.06.35.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jul 2024 06:35:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uwy4A7TL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sURH6-00005X-BF; Thu, 18 Jul 2024 09:34:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sURH4-0008D4-Nr for qemu-devel@nongnu.org; Thu, 18 Jul 2024 09:34:22 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sURH2-00004w-Qe for qemu-devel@nongnu.org; Thu, 18 Jul 2024 09:34:22 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-368557c9e93so348393f8f.2 for ; Thu, 18 Jul 2024 06:34:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721309659; x=1721914459; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k6Hx2eTtFNzw/hpMI15i/HZcqpokYYD9kQA6KJM/AwE=; b=Uwy4A7TLEgUxfYBnvnqCZOzCxHam+ZJN+9BEKEi8ssFto/ogq5FMcSoXReQhxfz00E TE7CpjlPqN2M9RZrw/cv66Hv+9o19zWEYn9mIE3Hs16SDxoXQK/G5dIB4VMld96hLZvn llDIsEQeunESA4KZ5siYhsu6qm4yLrZT3XZmwr3J2tEkSTrNwZu4eYWaF+GK/7ibvg9+ c43o/9JOqWHWFllAxCykf12G/tRaL3J0tXJIo1f3H40w4aXREAyCCwV7gTox5Xlv1QJX YWLCK5fm2QRIFq9cRf15HPbXfcG38CaQWzTkGwqxtyhRVdpKDgwx3jPVJM1PgWNIsez7 weIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721309659; x=1721914459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k6Hx2eTtFNzw/hpMI15i/HZcqpokYYD9kQA6KJM/AwE=; b=KzhI3PHTPe65AiclWnc5pFMxOlVzRuoGs8dGqcR9jEZ81S8tvqSjEjiWVdAkxZCsi5 yY55F+Fa/Q8A5ZIwhX5hgkbaxtbRipkuJlzGcvm2rH44BOj8R9Ucoys99GBLKTwMzrwV S7YR7jiGmuTDM22+5GdiWLtnNO4oYIoCbq4tUHYRfH+oZm3JQtd12iFAo+Ln4afqXXpQ XiEOuUBOltOOny2EQySDHfrJGZA1beU/xhI8RQ1lMnh1Q9mVeHy/eweo5s0BQsEF2Zei DeBQZlijvSbsW02QeUK7k80NBzhLl8PxmWtmzMWoP+UnKdMweXlbdMYZuRgR5vqotwau rM1A== X-Forwarded-Encrypted: i=1; AJvYcCVG8oVct2qXJgv1cl74xg2uPuLp178UZhLjxbB1oflSsEq5BR1OnsS/4WYk9pzUbxspmq4kfAAQ/HJLdiCgVYmpX0Vsp+A= X-Gm-Message-State: AOJu0YzSBLZI5XDgCCI/LWa+IBI9vt63FZXFJ92+Ywb4xT/8WkqXviK0 GCxHz/HHBiH7KE9ryvOkfsMy/L4AShD+viwSlcw8ofHsXg9uKvUKFfY11r6L/sbqnUcaSlETPzz 8 X-Received: by 2002:a5d:5547:0:b0:362:3cb8:cba with SMTP id ffacd0b85a97d-368317c88a8mr2893373f8f.67.1721309659003; Thu, 18 Jul 2024 06:34:19 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3680dabefa6sm14298504f8f.44.2024.07.18.06.34.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:34:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 11/19] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler Date: Thu, 18 Jul 2024 15:33:03 +0200 Message-ID: <20240718133312.10324-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Allow Loongson IPI implementations to have their own get_iocsr_as() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/intc/loongson_ipi_common.h | 2 ++ hw/intc/loongson_ipi.c | 16 ++++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 891b43644d..e49c156db3 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -39,6 +39,8 @@ struct LoongsonIPICommonState { struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; + + AddressSpace *(*get_iocsr_as)(CPUState *cpu); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index a54db87638..2c8829c3cc 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, return loongson_ipi_core_readl(s, addr, data, size, attrs); } -static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) -{ #ifdef TARGET_LOONGARCH64 +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} #endif + #ifdef TARGET_MIPS +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { return &MIPS_CPU(cpu)->env.iocsr.as; } -#endif + return NULL; } +#endif static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, uint64_t val, hwaddr addr, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int i, mask = 0, data = 0; - AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); if (!iocsr_as) { return MEMTX_DECODE_ERROR; @@ -338,9 +344,11 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); device_class_set_parent_realize(dc, loongson_ipi_realize, &lic->parent_realize); + licc->get_iocsr_as = get_iocsr_as; } static void loongson_ipi_finalize(Object *obj) From patchwork Thu Jul 18 13:33:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813201 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296575wro; Thu, 18 Jul 2024 06:34:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVRmBi2WRRkA4AJSfyp8Wvnea4XtXuvsphWQt9Kjat6dBZ22rTPKX8OVyDljC4Mi1M4Dh17WuKtQX5cnIku92l2 X-Google-Smtp-Source: AGHT+IF+TJBCQB3FPuMoOL9v1UA7hWpJ61TjH4e7VnxsIutX+RS4sAO23b7IXRayJSwaGJXTNFxM X-Received: by 2002:a05:620a:370f:b0:79f:1731:ae24 with SMTP id af79cd13be357-7a19390b964mr103630185a.32.1721309685601; Thu, 18 Jul 2024 06:34:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309685; cv=none; d=google.com; s=arc-20160816; b=q93oo7feDGrx+k0KTeo2I2x9Fs8gvSY1G3SWINiy3bRmYo2bYLJHaC0EZmNLA5DuDc KfX4wtJBoENAf4ITxrjK1Uk3MeqWy7h9euhA7pD3qi55Ds6UON0mlmW0Qq+kcH/8nOvd MwnJRUdV6csQzl2fNZLhSZW38xRNoW2M6Uege8yE8TKKlwO/5zPAzy30uxgg33fNnVJn ZSkzS3Jq0gwMJ5jz8jXuPWxkrKuXdWVmlg89YlCBuNubUAJKrcWiOXYQQk7xjpI7opn7 Xbj8oLsQH9jTwfIs99X38/NHbcdqh57DaCbNYoIlx7p/uTfMYIcBhT4B+54WYoHS4iDe /tqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0+OxJiG+z3ssF/3QJZPn0rn/Ivu5hISnKA+KGQ086vg=; fh=UvpztvDzfIrJXBGeMpateaxtmz8AES1IeU4CVSQy5xk=; b=0zN/6LT8ZaiYO6GSmhWJi79VikQtnoeNNofb/YEqFwL7bqi+o8dspYTinOev1RFZ1w FXNK0dq9KLeGZlcsY+8oQ5OQfdumVXRQmmiXbHRnKc3SK5whS2/9GhK2qmD2VQH+1aow +mOktju5grY7aZhz6ByDAIPomLXvdSrIV/zgsmJLYL/W79rL8kVmiRezsSnuNlLZkisi XhE9c8YRj3zuw3v4NquTTS9oWEVyPKAhr97XBdj4eDj2AyKZZmPPPSKwkXLoqgNuvUKK ajl7fwZXivunYQeEKyUzAxSx5bZPoREamfegNbS9DAMZb+/QIZXTX1P5Xa27gsfpmeN0 BSLg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hwDyVAfT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/intc/loongson_ipi_common.h | 1 + hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index e49c156db3..5447e9f650 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -41,6 +41,7 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; AddressSpace *(*get_iocsr_as)(CPUState *cpu); + CPUState *(*cpu_by_arch_id)(int64_t id); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 2c8829c3cc..39bcf0031d 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi, static MemTxResult any_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int index = 0; uint32_t cpuid; uint8_t vector; @@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, cpuid = extract32(val, 16, 10); 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/intc/loongson_ipi_common.h | 6 ++++++ hw/intc/loongson_ipi.c | 10 ++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 5447e9f650..a75882f775 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -10,6 +10,7 @@ #include "qom/object.h" #include "hw/sysbus.h" +#include "exec/memattrs.h" #define IPI_MBX_NUM 4 @@ -44,6 +45,11 @@ struct LoongsonIPICommonClass { CPUState *(*cpu_by_arch_id)(int64_t id); }; +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs); +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs); + /* Mainy used by iocsr read and write */ #define SMP_IPI_MAILBOX 0x1000ULL diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 39bcf0031d..a2db8bb2e2 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,9 +24,8 @@ #endif #include "trace.h" -static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; uint64_t ret = 0; @@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi, return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; From patchwork Thu Jul 18 13:33:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813204 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp296720wro; Thu, 18 Jul 2024 06:35:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXKE8HVQKADmNaCDOVru2TOQbtZDkGvR0wnCFprq4s5kNAAbBEyVgVagz26pZvuO0Cfw5+gc+MDMrSyo3YLZv0u X-Google-Smtp-Source: AGHT+IFVOyBo7k1uD3y2w0YnfAeMR1uETHHT8ht6lHgE63bJS4GaNPfxPIqOLFMONV2RqiwMyf7X X-Received: by 2002:a05:6902:2747:b0:e03:512e:c435 with SMTP id 3f1490d57ef6-e05fec0b7ccmr3159598276.52.1721309701102; Thu, 18 Jul 2024 06:35:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309701; cv=none; d=google.com; s=arc-20160816; b=cU22i0dk+WezHKU4DZQ4KkgJU+rvRl3HhnaO9woq0+IlmBoZZpcgIZ4ZejtuKlc/Vd B618RfMHjhyo3HNoJZRQQqa5RBl3KGFn53zH6n0BT05ptnaTHphfD8KyDzZQy87nGuPi RR6Ozt0b+Hp4Gi/Ne+OzMT69lgAitpUMAgUBVzqnz0vf0t2Puq74IhAhHKUnsvyhFyuE 8V51zg2zEatL/kJPRTtlYltwMJPZHSEK0PPYNp75pXM/ggCrcPQoMmkEBTaCAoW4+f8W OFCQ0Sdb/iLTaePk/oswe3hYLYDbFscagxCpqO3jhgpDaE7RZv4LvmtSp2O1joyvjyWj Jujg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hkEk/NJ7l23oCST4OhgnNgMF481p6nwLpHkqastMauo=; fh=D4IRlIqiDBDne+2eIj/U1Ng3F7UhBwC9GVSM52EdeNs=; b=e69+atAY1E/spBsZuE/xC9mMj9BVsGSSPzakqbOrkG/sh/8s2xiCko0TPr4Vo7++cC JLbqx5om3+bVXOFyB7Fc1n4nSooTexvITYeIv65IHec2rG5oIwHG0kyeNa/HVEfDDuaw oEZdYiCkDU+cRpL+NmazR4o0UCcSjV8KZ4I6wysAIb1pDceAQ/mYQl/ey9D9Z1Csrokl /xC/s5US5niZ+LZEo8eOYoli9AJ7WzYjJIMMDeOoPRoFSa8HaKAhGqBjDydIuTf/N+/z 9aJ1Jxg1bt9WgTgXXjmboaWUIl2Z2mY4tp2RXWfCzILVHZBPA74y8h9RIGYOiDOvAxb5 SqoQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pb1OimMS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 18 Jul 2024 06:34:36 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2b18420sm13657555e9.19.2024.07.18.06.34.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:34:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 14/19] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c Date: Thu, 18 Jul 2024 15:33:06 +0200 Message-ID: <20240718133312.10324-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Move the common code from loongson_ipi.c to loongson_ipi_common.c, call parent_realize() instead of loongson_ipi_common_realize() in loongson_ipi_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- hw/intc/loongson_ipi.c | 269 +-------------------------------- hw/intc/loongson_ipi_common.c | 272 ++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 267 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index a2db8bb2e2..86badb2972 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,56 +24,6 @@ #endif #include "trace.h" -MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - uint64_t ret = 0; - int index = 0; - - addr &= 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret = s->status; - break; - case CORE_EN_OFF: - ret = s->en; - break; - case CORE_SET_OFF: - ret = 0; - break; - case CORE_CLEAR_OFF: - ret = 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - ret = s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongson_ipi_read(size, (uint64_t)addr, ret); - *data = ret; - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_readl(s, addr, data, size, attrs); -} - #ifdef TARGET_LOONGARCH64 static AddressSpace *get_iocsr_as(CPUState *cpu) { @@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) } #endif -static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, - uint64_t val, hwaddr addr, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int i, mask = 0, data = 0; - AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); - - if (!iocsr_as) { - return MEMTX_DECODE_ERROR; - } - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); - for (i = 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |= 0xff << (i * 8); - } - } - } - - data &= mask; - data |= (val >> 32) & ~mask; - address_space_stl_le(iocsr_as, addr, data, attrs, NULL); - - return MEMTX_OK; -} - -static MemTxResult mail_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -static MemTxResult any_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = val & 0xffff; - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - LoongsonIPICommonState *ipi = s->ipi; - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int index = 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - addr &= 0xff; - trace_loongson_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en = val; - break; - case CORE_SET_OFF: - s->status |= val; - if (s->status != 0 && (s->status & s->en) != 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &= ~val; - if (s->status == 0 && s->en != 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - s->buf[index] = val; - break; - case IOCSR_IPI_SEND: - cpuid = extract32(val, 16, 10); - /* IPI status vector */ - vector = extract8(val, 0, 5); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, - BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } - - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_writel(s, addr, val, size, attrs); -} - static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, .write_with_attrs = loongson_ipi_core_writel, @@ -244,88 +52,15 @@ static const MemoryRegionOps loongson_ipi_core_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static const MemoryRegionOps loongson_ipi_iocsr_ops = { - .read_with_attrs = loongson_ipi_iocsr_readl, - .write_with_attrs = loongson_ipi_iocsr_writel, - .impl.min_access_size = 4, - .impl.max_access_size = 4, - .valid.min_access_size = 4, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - MemTxResult ret = MEMTX_OK; - - addr &= 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret = mail_send(ipi, val, attrs); - break; - case ANY_SEND_OFFSET: - ret = any_send(ipi, val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongson_ipi64_ops = { - .write_with_attrs = loongson_ipi_writeq, - .impl.min_access_size = 8, - .impl.max_access_size = 8, - .valid.min_access_size = 8, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) -{ - LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu == 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), - &loongson_ipi_iocsr_ops, - s, "loongson_ipi_iocsr", 0x48); - - /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard = true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongson_ipi64_ops, - s, "loongson_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu = g_new0(IPICore, s->num_cpu); - for (i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi = s; - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } -} - static void loongson_ipi_realize(DeviceState *dev, Error **errp) { LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; - loongson_ipi_common_realize(dev, &local_err); + lic->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); return; diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index cc49896b2d..8be7649295 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,8 +8,279 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" #include "migration/vmstate.h" +#include "trace.h" + +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + uint64_t ret = 0; + int index = 0; + + addr &= 0xff; + switch (addr) { + case CORE_STATUS_OFF: + ret = s->status; + break; + case CORE_EN_OFF: + ret = s->en; + break; + case CORE_SET_OFF: + ret = 0; + break; + case CORE_CLEAR_OFF: + ret = 0; + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + ret = s->buf[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); + break; + } + + trace_loongson_ipi_read(size, (uint64_t)addr, ret); + *data = ret; + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int i, mask = 0, data = 0; + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); + + if (!iocsr_as) { + return MEMTX_DECODE_ERROR; + } + + /* + * bit 27-30 is mask for byte writing, + * if the mask is 0, we need not to do anything. + */ + if ((val >> 27) & 0xf) { + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); + for (i = 0; i < 4; i++) { + /* get mask for byte writing */ + if (val & (0x1 << (27 + i))) { + mask |= 0xff << (i * 8); + } + } + } + + data &= mask; + data |= (val >> 32) & ~mask; + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); + + return MEMTX_OK; +} + +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = val & 0xffff; + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int index = 0; + uint32_t cpuid; + uint8_t vector; + CPUState *cs; + + addr &= 0xff; + trace_loongson_ipi_write(size, (uint64_t)addr, val); + switch (addr) { + case CORE_STATUS_OFF: + qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); + break; + case CORE_EN_OFF: + s->en = val; + break; + case CORE_SET_OFF: + s->status |= val; + if (s->status != 0 && (s->status & s->en) != 0) { + qemu_irq_raise(s->irq); + } + break; + case CORE_CLEAR_OFF: + s->status &= ~val; + if (s->status == 0 && s->en != 0) { + qemu_irq_lower(s->irq); + } + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + s->buf[index] = val; + break; + case IOCSR_IPI_SEND: + cpuid = extract32(val, 16, 10); + /* IPI status vector */ + vector = extract8(val, 0, 5); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); + break; + } + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_iocsr_ops = { + .read_with_attrs = loongson_ipi_iocsr_readl, + .write_with_attrs = loongson_ipi_iocsr_writel, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .valid.min_access_size = 4, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +/* mail send and any send only support writeq */ +static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + MemTxResult ret = MEMTX_OK; + + addr &= 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + ret = mail_send(ipi, val, attrs); + break; + case ANY_SEND_OFFSET: + ret = any_send(ipi, val, attrs); + break; + default: + break; + } + + return ret; +} + +static const MemoryRegionOps loongson_ipi64_ops = { + .write_with_attrs = loongson_ipi_writeq, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpu == 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), + &loongson_ipi_iocsr_ops, + s, "loongson_ipi_iocsr", 0x48); + + /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ + s->ipi_iocsr_mem.disable_reentrancy_guard = true; + + sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); + + memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), + &loongson_ipi64_ops, + s, "loongson_ipi64_iocsr", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); + + s->cpu = g_new0(IPICore, s->num_cpu); + for (i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi = s; + + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} static void loongson_ipi_common_finalize(Object *obj) { @@ -53,6 +324,7 @@ static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = loongson_ipi_common_realize; device_class_set_props(dc, ipi_properties); dc->vmsd = &vmstate_loongson_ipi; } From patchwork Thu Jul 18 13:33:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813214 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp297396wro; 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Thu, 18 Jul 2024 06:34:42 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2b29342sm13216315e9.31.2024.07.18.06.34.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:34:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 15/19] hw/intc/loongarch_ipi: Add loongarch IPI support Date: Thu, 18 Jul 2024 15:33:07 +0200 Message-ID: <20240718133312.10324-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Loongarch IPI is added here, it inherits from class TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can be used when ipi is emulated in userspace with KVM mode. Signed-off-by: Bibo Mao [PMD: Rebased and simplified] Co-Developed-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Signed-off-by: Philippe Mathieu-Daudé Acked-by: Song Gao --- include/hw/intc/loongarch_ipi.h | 25 ++++++++++++ hw/intc/loongarch_ipi.c | 68 +++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 4 ++ hw/intc/meson.build | 1 + 4 files changed, 98 insertions(+) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 hw/intc/loongarch_ipi.c diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h new file mode 100644 index 0000000000..276b3040a3 --- /dev/null +++ b/include/hw/intc/loongarch_ipi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch IPI interrupt header files + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_IPI_H +#define HW_LOONGARCH_IPI_H + +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" + +#define TYPE_LOONGARCH_IPI "loongarch_ipi" +OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI) + +struct LoongarchIPIState { + LoongsonIPICommonState parent_obj; +}; + +struct LoongarchIPIClass { + LoongsonIPICommonClass parent_class; +}; + +#endif diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c new file mode 100644 index 0000000000..2ae1a42c46 --- /dev/null +++ b/hw/intc/loongarch_ipi.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch IPI interrupt support + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/intc/loongarch_ipi.h" +#include "target/loongarch/cpu.h" + +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ + return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} + +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a = (CPUArchId *)a; + CPUArchId *archid_b = (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id = id; + found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, + sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +{ + MachineState *machine = MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid = find_cpu_by_archid(machine, arch_id); + if (archid) { + return CPU(archid->cpu); + } + + return NULL; +} + +static void loongarch_ipi_class_init(ObjectClass *klass, void *data) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + + licc->get_iocsr_as = get_iocsr_as; + licc->cpu_by_arch_id = loongarch_cpu_by_arch_id; +} + +static const TypeInfo loongarch_ipi_types[] = { + { + .name = TYPE_LOONGARCH_IPI, + .parent = TYPE_LOONGSON_IPI_COMMON, + .class_init = loongarch_ipi_class_init, + } +}; + +DEFINE_TYPES(loongarch_ipi_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index a2a0fdca85..dd405bdb5d 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -94,6 +94,10 @@ config LOONGSON_IPI bool select LOONGSON_IPI_COMMON +config LOONGARCH_IPI + bool + select LOONGSON_IPI_COMMON + config LOONGARCH_PCH_PIC bool select UNIMP diff --git a/hw/intc/meson.build b/hw/intc/meson.build index a09a527207..f4d81eb8e4 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c')) From patchwork Thu Jul 18 13:33:08 2024 Content-Type: text/plain; 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Thu, 18 Jul 2024 06:34:47 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2b1dfd8sm13891305e9.22.2024.07.18.06.34.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:34:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 16/19] hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI Date: Thu, 18 Jul 2024 15:33:08 +0200 Message-ID: <20240718133312.10324-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- include/hw/loongarch/virt.h | 1 - hw/loongarch/virt.c | 4 ++-- hw/loongarch/Kconfig | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..91216418c8 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e592b1b6b7..29040422aa 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) */ /* Create IPI device */ - ipi = qdev_new(TYPE_LOONGSON_IPI); + ipi = qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 89be737726..0de713a439 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -12,7 +12,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS - select LOONGSON_IPI + select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI From patchwork Thu Jul 18 13:33:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813212 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp297388wro; Thu, 18 Jul 2024 06:36:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUjROE9SebQzySPnwKERJgYOR6+UzAVo2L0Kzj4meRP75WIK2xNxucR8dyBlg3tFqfm44L2LEpaTXzVeJxwWuLP X-Google-Smtp-Source: AGHT+IG9ZUKs9eNGVF8NGjYjl4SzFWeT7kxMoJM+I/gckPHGuWFbEK/sooaPWIDqZa/2uBr/2/9N X-Received: by 2002:a05:6214:d0d:b0:6b5:7fae:53db with SMTP id 6a1803df08f44-6b79c67cf87mr32817326d6.30.1721309790160; Thu, 18 Jul 2024 06:36:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309790; cv=none; d=google.com; s=arc-20160816; b=KXTpQhrt84mgt7NuvEWlNmZiuH7YVie1x5rqb9+w4IFWTgDLwyMv32gBhSfBeJM/Mo pU3hCf8DPCJBSD8/Wuckvf1Js4Ik8ZAleLh/ag2bfYDdvUjWpE2J4050N0seyVzAj3Zt /9+aNDRg5uprsx+7sgipNgdCUkQPNcLRIP7hmBkSMJL9BuY7Y7hbvFILrVq6oNCsFdIh g6x3whhoMJvhdNlPUSmTFeJ6t7Gl8jDTzi9uHuH8gT1iNdIGBD/LakiYsARlCySs+6tu YLGkF/RVjogfc+NeA5TSA7S2xqdzSCU2rqP6fVNb26fheHU4WRN3Gh3DaYfmjW02gPkm 3wZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zsKSM3KuaB4chvTu0dhkMoqoWuPlYClNtw5MCTNrLns=; fh=o+e88Sv1vuG/DCNNuzlRGTSMKhb3bEkldzPznsH1Fl8=; b=nMj3x/YFFtiqgzYjG9SeKOSHlDVL8Eoe57UdXhnqsWlTPGMYnTXeDioDpy4yo8q3td izAIsX67nErRMNFl0TFfDLPrGFpODelL4nc1ITC9Xwraqt6YW9dQM5wQcgmwBIvB0rRX ttrhJuvPyFHMC7WVtCOPBS0rI6j2nG1S8c+M8vRjQ4AW5FdftooEDb58GhdkoyeCSErV JJ/gmEy+cTGtUTr4WrtyRcbYKZf9RhEhsA/KZYXYF2PGjJyftu6prKcjy0FeP/7nZXdh I7x7UCLNwEpiFwHQ4/JhTTpWnRrp/+IsYQyQbjhraiQ6l7lZ56i8XYbU9RpGt5SNLHWy OlZg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="IT22f//m"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- MAINTAINERS | 2 -- hw/intc/loongson_ipi.c | 14 -------------- 2 files changed, 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a670c8ee67..c2d51b0158 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1250,10 +1250,8 @@ F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h F: include/hw/intc/loongson_ipi_common.h -F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c F: hw/intc/loongson_ipi_common.c -F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c F: gdb-xml/loongarch*.xml diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 86badb2972..051e910586 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -16,22 +16,9 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "migration/vmstate.h" -#ifdef TARGET_LOONGARCH64 -#include "target/loongarch/cpu.h" -#endif -#ifdef TARGET_MIPS #include "target/mips/cpu.h" -#endif #include "trace.h" -#ifdef TARGET_LOONGARCH64 -static AddressSpace *get_iocsr_as(CPUState *cpu) -{ - return LOONGARCH_CPU(cpu)->env.address_space_iocsr; -} -#endif - -#ifdef TARGET_MIPS static AddressSpace *get_iocsr_as(CPUState *cpu) { if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { @@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } -#endif static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, From patchwork Thu Jul 18 13:33:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813210 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp297095wro; Thu, 18 Jul 2024 06:35:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUNYzhYX2y8/7K++6NeSUY48adTy9Ebnzk0Bd2oig4XZuP5U7JFOkdNmuBZbfjAoI6Krlh3+NU8/QKWXmSzYKoI X-Google-Smtp-Source: AGHT+IGWtwXhasiiSbotqRkoTwZ7EcJqXaQhysUdBMfZj50nHkZQyyTh6VMr2pWefIhQRuWC9EZl X-Received: by 2002:a05:620a:29ca:b0:79e:ff0a:87a0 with SMTP id af79cd13be357-7a193b0dc97mr129385885a.11.1721309749359; Thu, 18 Jul 2024 06:35:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721309749; cv=none; d=google.com; s=arc-20160816; b=D8iH9/3oakXLBRjP2/Ryb0J8ZiIKGAbv5QRj6f9y81zJQmnilBDqXIlprauT3bGf8g 6hcqJrD7giBranE04BDJS7SMGIZrwHdB/XdRDlQwuSxpfdITTzNJeq5r6rkwgk30yhDv xlRJbqOTsNODi7U2rJGhw1N1RI3HzubzU8MWyNwJBD3oc7KYs5nPnBoRdUC+zZSVKleO Fe5ik52ROc3jC8ax3NQnIZcg+8k6KW8weKqmUUkvU86yyDR7HIqjK7wxE1lt6/Tq/947 plE6PFrby8KkSFeOKGtWPUtRNwD1Wzhb/D/tya7wZ+uHhvi+CpBEc6N8IheEXiwqeuCo tLBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HR1xIddw3GQAkekNAdVkZHeDlA8TRFDNATHX/fKoI7M=; fh=oe7O75uzUo1qhceGXZL1fFYZv0N8Y+Ck6o4kN+zajqE=; b=X2qUMkUPOiFQOfMzeDZ/RXzHYZX5YeWYy5oqwyBxe964JdGz3ZU1CJZM6L1nAsslhv rsctlRIepnntkfOa4uO7c2O5xL9kiapc3ZoYDC6XQg5EbhUk3IocHZ5YakJF06cmUOcO udSVAoOcXrQcv082bJc8x5Ur42DxAgzD9H+8G7BOaV4d/piGpuUz4E1R9sCTKGvkQvNJ /F8zprrajX66FxNog11KPHLeC7LuyFj7B70ly8lAjdBj1JLNd9olgq47PCFC7ia/Itkp 0bddnnBTlWZlQmbqhfL50kvFw9ryOz0JqOTJH3wOgObXeWkH1FOTND/Cz+N4Vi0B/CZX BRGg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vMKLqrX7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 18 Jul 2024 06:34:59 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a94f50sm14311575e9.44.2024.07.18.06.34.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:34:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 18/19] hw/intc/loongson_ipi: Remove unused headers Date: Thu, 18 Jul 2024 15:33:10 +0200 Message-ID: <20240718133312.10324-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao --- hw/intc/loongson_ipi.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 051e910586..aa1b0a474c 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -6,18 +6,9 @@ */ #include "qemu/osdep.h" -#include "hw/boards.h" -#include "hw/sysbus.h" #include "hw/intc/loongson_ipi.h" -#include "hw/irq.h" -#include "hw/qdev-properties.h" #include "qapi/error.h" -#include "qemu/log.h" -#include "exec/address-spaces.h" -#include "exec/memory.h" -#include "migration/vmstate.h" #include "target/mips/cpu.h" -#include "trace.h" static AddressSpace *get_iocsr_as(CPUState *cpu) { From patchwork Thu Jul 18 13:33:11 2024 Content-Type: text/plain; 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Thu, 18 Jul 2024 06:35:04 -0700 (PDT) Received: from localhost.localdomain ([176.176.173.113]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2b2a11asm14390595e9.40.2024.07.18.06.35.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 06:35:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Bibo Mao , qemu-devel@nongnu.org, Jiaxun Yang Cc: Song Gao , Paolo Bonzini , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Xianglai Li Subject: [PATCH v5 19/19] docs: Correct Loongarch -> LoongArch Date: Thu, 18 Jul 2024 15:33:11 +0200 Message-ID: <20240718133312.10324-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718133312.10324-1-philmd@linaro.org> References: <20240718133312.10324-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- docs/about/emulation.rst | 2 +- hw/rtc/ls7a_rtc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index b5ff9c5f69..3bfe8cc14a 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -42,7 +42,7 @@ depending on the guest architecture. - :ref:`Yes` - Yes - The ubiquitous desktop PC CPU architecture, 32 and 64 bit. - * - Loongarch + * - LoongArch - Yes - Yes - A MIPS-like 64bit RISC architecture developed in China diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c index 052201c2cd..3226b6105e 100644 --- a/hw/rtc/ls7a_rtc.c +++ b/hw/rtc/ls7a_rtc.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Loongarch LS7A Real Time Clock emulation + * LoongArch LS7A Real Time Clock emulation * * Copyright (C) 2021 Loongson Technology Corporation Limited */