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[83.30.44.214]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fc226cdccsm91552e87.164.2024.07.22.02.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 02:52:15 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Srinivas Kandagatla , Banajit Goswami , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladimir Lypak Subject: [PATCH 1/4] ASoC: qcom: apq8016_sbc.c: Add Quinary support Date: Mon, 22 Jul 2024 11:51:05 +0200 Message-ID: <20240722095147.3372-2-a39.skl@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722095147.3372-1-a39.skl@gmail.com> References: <20240722095147.3372-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Vladimir Lypak Add support for configuring Quinary Mi2S interface it will be used on MSM8953 and MSM8976 platform. Signed-off-by: Vladimir Lypak [Adam: Split from MSM8953 support patch,add msg] Signed-off-by: Adam Skladowski --- sound/soc/qcom/apq8016_sbc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/sound/soc/qcom/apq8016_sbc.c b/sound/soc/qcom/apq8016_sbc.c index 3023cf180a75..8971f4f5d339 100644 --- a/sound/soc/qcom/apq8016_sbc.c +++ b/sound/soc/qcom/apq8016_sbc.c @@ -20,12 +20,13 @@ #include "common.h" #include "qdsp6/q6afe.h" -#define MI2S_COUNT (MI2S_QUATERNARY + 1) +#define MI2S_COUNT (MI2S_QUINARY + 1) struct apq8016_sbc_data { struct snd_soc_card card; void __iomem *mic_iomux; void __iomem *spkr_iomux; + void __iomem *quin_iomux; struct snd_soc_jack jack; bool jack_setup; int mi2s_clk_count[MI2S_COUNT]; @@ -86,6 +87,12 @@ static int apq8016_dai_init(struct snd_soc_pcm_runtime *rtd, int mi2s) SPKR_CTL_TLMM_DATA1_EN | SPKR_CTL_TLMM_WS_OUT_SEL_SEC | SPKR_CTL_TLMM_WS_EN_SEL_SEC, pdata->spkr_iomux); break; + case MI2S_QUINARY: + /* Configure Quinary MI2S */ + if (!pdata->quin_iomux) + return -ENOENT; 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[83.30.44.214]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fc226cdccsm91552e87.164.2024.07.22.02.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 02:52:17 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Srinivas Kandagatla , Banajit Goswami , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladimir Lypak Subject: [PATCH 2/4] ASoC: msm8916-wcd-analog: add cajon and cajon v2 support Date: Mon, 22 Jul 2024 11:51:06 +0200 Message-ID: <20240722095147.3372-3-a39.skl@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722095147.3372-1-a39.skl@gmail.com> References: <20240722095147.3372-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Vladimir Lypak Add regs overrides for Cajon(PM8952) and Cajon v2(PM8953) codecs. Signed-off-by: Vladimir Lypak [Adam: Add Cajon support,add msg] Co-developed-by: Adam Skladowski Signed-off-by: Adam Skladowski --- sound/soc/codecs/msm8916-wcd-analog.c | 63 +++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/msm8916-wcd-analog.c b/sound/soc/codecs/msm8916-wcd-analog.c index 9ca381812975..daf65f5d4e99 100644 --- a/sound/soc/codecs/msm8916-wcd-analog.c +++ b/sound/soc/codecs/msm8916-wcd-analog.c @@ -250,6 +250,7 @@ SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \ SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \ SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) +#define CDC_A_SPKR_ANA_BIAS_SET (0xf1B3) #define CDC_A_SPKR_OCP_CTL (0xf1B4) #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) @@ -264,12 +265,15 @@ #define CDC_A_SPKR_DRV_DBG (0xf1B7) #define CDC_A_CURRENT_LIMIT (0xf1C0) +#define CDC_A_BYPASS_MODE (0xf1C2) #define CDC_A_BOOST_EN_CTL (0xf1C3) #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) #define CDC_A_SEC_ACCESS (0xf1D0) #define CDC_A_PERPH_RESET_CTL3 (0xf1DA) #define CDC_A_PERPH_RESET_CTL4 (0xf1DB) +#define CDC_A_RX_EAR_STATUS (0xf1A1) + #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ @@ -715,6 +719,50 @@ static const struct reg_default wcd_reg_defaults_2_0[] = { {CDC_A_MASTER_BIAS_CTL, 0x30}, }; +static const struct reg_default wcd_reg_defaults_cajon[] = { + {CDC_A_RX_COM_OCP_CTL, 0xD1}, + {CDC_A_RX_COM_OCP_COUNT, 0xFF}, + {CDC_D_SEC_ACCESS, 0xA5}, + {CDC_D_PERPH_RESET_CTL3, 0x0F}, + {CDC_A_TX_1_2_OPAMP_BIAS, 0x4C}, + {CDC_A_NCP_FBCTRL, 0xA8}, + {CDC_A_NCP_VCTRL, 0xA4}, + {CDC_A_SPKR_DRV_CTL, 0x69}, + {CDC_A_SPKR_DRV_DBG, 0x01}, + {CDC_A_SEC_ACCESS, 0xA5}, + {CDC_A_PERPH_RESET_CTL3, 0x0F}, + {CDC_A_CURRENT_LIMIT, 0x82}, + {CDC_A_SPKR_ANA_BIAS_SET, 0x41}, + {CDC_A_SPKR_DAC_CTL, 0x03}, + {CDC_A_SPKR_OCP_CTL, 0xE1}, + {CDC_A_RX_HPH_BIAS_PA, 0xFA}, + {CDC_A_MASTER_BIAS_CTL, 0x30}, + {CDC_A_MICB_1_INT_RBIAS, 0x00}, +}; + +static const struct reg_default wcd_reg_defaults_cajon_2_0[] = { + {CDC_A_RX_COM_OCP_CTL, 0xD1}, + {CDC_A_RX_COM_OCP_COUNT, 0xFF}, + {CDC_D_SEC_ACCESS, 0xA5}, + {CDC_D_PERPH_RESET_CTL3, 0x0F}, + {CDC_A_TX_1_2_OPAMP_BIAS, 0x4C}, + {CDC_A_NCP_FBCTRL, 0xA8}, + {CDC_A_NCP_VCTRL, 0xA4}, + {CDC_A_SPKR_DRV_CTL, 0x69}, + {CDC_A_SPKR_DRV_DBG, 0x01}, + {CDC_A_SEC_ACCESS, 0xA5}, + {CDC_A_PERPH_RESET_CTL3, 0x0F}, + {CDC_A_CURRENT_LIMIT, 0xA2}, + {CDC_A_BYPASS_MODE, 0x18}, + {CDC_A_SPKR_ANA_BIAS_SET, 0x41}, + {CDC_A_SPKR_DAC_CTL, 0x03}, + {CDC_A_SPKR_OCP_CTL, 0xE1}, + {CDC_A_RX_HPH_BIAS_PA, 0xFA}, + {CDC_A_RX_EAR_STATUS, 0x10}, + {CDC_A_MASTER_BIAS_CTL, 0x30}, + {CDC_A_MICB_1_INT_RBIAS, 0x00}, +}; + static int pm8916_wcd_analog_probe(struct snd_soc_component *component) { struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); @@ -738,9 +786,18 @@ static int pm8916_wcd_analog_probe(struct snd_soc_component *component) snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); - for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) - snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg, - wcd_reg_defaults_2_0[reg].def); + if (priv->codec_version == 4) + for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_cajon_2_0); reg++) + snd_soc_component_write(component, wcd_reg_defaults_cajon_2_0[reg].reg, + wcd_reg_defaults_cajon_2_0[reg].def); + else if (priv->codec_version == 3) + for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_cajon); reg++) + snd_soc_component_write(component, wcd_reg_defaults_cajon[reg].reg, + wcd_reg_defaults_cajon[reg].def); + else + for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) + snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg, + wcd_reg_defaults_2_0[reg].def); priv->component = component; From patchwork Mon Jul 22 09:51:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 813814 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D542F16DEB9; Mon, 22 Jul 2024 09:52:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721641945; cv=none; b=AH4bjIyXShH4BZsH7HdKe5AX/r2WtFMlrDv907dv2fwTAn5DO3jV3wu7XngtGuVpkF6Nc/ZJl0xvn1KJ49vLj2AI62YfrytbjES1oXjDjj27xh2OJSqjUZHior7ijDvfN2lo6L4ZWMqxkHSXVxLzwZydQvqWcczPq2KShajXKzo= ARC-Message-Signature: i=1; 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[83.30.44.214]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fc226cdccsm91552e87.164.2024.07.22.02.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 02:52:21 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Srinivas Kandagatla , Banajit Goswami , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] ASoC: dt-bindings: qcom,sm8250: Add msm8953/msm8976-qdsp6-sndcard Date: Mon, 22 Jul 2024 11:51:07 +0200 Message-ID: <20240722095147.3372-4-a39.skl@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722095147.3372-1-a39.skl@gmail.com> References: <20240722095147.3372-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document MSM8953/MSM8976 QDSP6 cards. Signed-off-by: Adam Skladowski --- .../bindings/sound/qcom,sm8250.yaml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index b2e15ebbd1bc..3b5f8adba725 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -29,6 +29,8 @@ properties: - enum: - qcom,apq8016-sbc-sndcard - qcom,msm8916-qdsp6-sndcard + - qcom,msm8953-qdsp6-sndcard + - qcom,msm8976-qdsp6-sndcard - qcom,qcm6490-idp-sndcard - qcom,qcs6490-rb3gen2-sndcard - qcom,qrb5165-rb5-sndcard @@ -144,10 +146,30 @@ allOf: - model - reg - reg-names - else: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8953-qdsp6-sndcard + - qcom,msm8976-qdsp6-sndcard + then: properties: - reg: false - reg-names: false + reg: + items: + - description: Microphone I/O mux register address + - description: Speaker I/O mux register address + - description: Quinary Mi2S I/O mux register address + reg-names: + items: + - const: mic-iomux + - const: spkr-iomux + - const: quin-iomux + required: + - compatible + - model + - reg + - reg-names additionalProperties: false From patchwork Mon Jul 22 09:51:08 2024 Content-Type: text/plain; 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[83.30.44.214]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52fc226cdccsm91552e87.164.2024.07.22.02.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 02:52:24 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Srinivas Kandagatla , Banajit Goswami , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladimir Lypak Subject: [PATCH 4/4] ASoC: qcom: apq8016_sbc: Add support for msm8953/msm8976 SoC Date: Mon, 22 Jul 2024 11:51:08 +0200 Message-ID: <20240722095147.3372-5-a39.skl@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722095147.3372-1-a39.skl@gmail.com> References: <20240722095147.3372-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Vladimir Lypak Introduce support for audio card on MSM8953/MSM8976 platform. Main difference between those two is Q6AFE CLK API supported by firmware which influence way we enable digital codec clock. Either inside machine driver or outside via q6afe-clocks driver. Signed-off-by: Vladimir Lypak [Adam: Add MSM8976, rename functions, add mclk setting,add msg] Co-developed-by: Adam Skladowski Signed-off-by: Adam Skladowski --- sound/soc/qcom/apq8016_sbc.c | 66 ++++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 2 deletions(-) diff --git a/sound/soc/qcom/apq8016_sbc.c b/sound/soc/qcom/apq8016_sbc.c index 8971f4f5d339..51efefefe0a1 100644 --- a/sound/soc/qcom/apq8016_sbc.c +++ b/sound/soc/qcom/apq8016_sbc.c @@ -22,6 +22,11 @@ #define MI2S_COUNT (MI2S_QUINARY + 1) +enum afe_clk_api { + Q6AFE_CLK_V1, + Q6AFE_CLK_V2 +}; + struct apq8016_sbc_data { struct snd_soc_card card; void __iomem *mic_iomux; @@ -29,6 +34,8 @@ struct apq8016_sbc_data { void __iomem *quin_iomux; struct snd_soc_jack jack; bool jack_setup; + enum afe_clk_api q6afe_clk_ver; + bool dig_cdc_mclk_en; int mi2s_clk_count[MI2S_COUNT]; }; @@ -192,6 +199,28 @@ static int qdsp6_dai_get_lpass_id(struct snd_soc_dai *cpu_dai) } } +static int qdsp6_get_clk_id(struct apq8016_sbc_data *data, int mi2s_id) +{ + if (data->q6afe_clk_ver == Q6AFE_CLK_V2) { + switch (mi2s_id) { + case MI2S_PRIMARY: + return Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT; + case MI2S_SECONDARY: + return Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT; + case MI2S_TERTIARY: + return Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT; + case MI2S_QUATERNARY: + return Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + case MI2S_QUINARY: + return Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + default: + break; + } + } + /* If AFE CLK isn't V2 return V1 */ + return LPAIF_BIT_CLK; +} + static int msm8916_qdsp6_dai_init(struct snd_soc_pcm_runtime *rtd) { struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); @@ -214,8 +243,16 @@ static int msm8916_qdsp6_startup(struct snd_pcm_substream *substream) if (++data->mi2s_clk_count[mi2s] > 1) return 0; + /* + * On newer legacy SoC (MSM8976) lpass codec clocks are not available in gcc region + * so we have to request clock from machine driver using V1 API) + */ + if (data->q6afe_clk_ver == Q6AFE_CLK_V1 && data->dig_cdc_mclk_en == true) + ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_DIG_CLK, DEFAULT_MCLK_RATE, 0); + if (ret) + dev_err(card->dev, "Failed to enable LPAIF dig clk: %d\n", ret); - ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_BIT_CLK, MI2S_BCLK_RATE, 0); + ret = snd_soc_dai_set_sysclk(cpu_dai, qdsp6_get_clk_id(data, mi2s), MI2S_BCLK_RATE, 0); if (ret) dev_err(card->dev, "Failed to enable LPAIF bit clk: %d\n", ret); return ret; @@ -236,9 +273,15 @@ static void msm8916_qdsp6_shutdown(struct snd_pcm_substream *substream) if (--data->mi2s_clk_count[mi2s] > 0) return; - ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_BIT_CLK, 0, 0); + ret = snd_soc_dai_set_sysclk(cpu_dai, qdsp6_get_clk_id(data, mi2s), 0, 0); if (ret) dev_err(card->dev, "Failed to disable LPAIF bit clk: %d\n", ret); + + if (data->q6afe_clk_ver == Q6AFE_CLK_V1 && data->dig_cdc_mclk_en == true) + ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_DIG_CLK, 0, 0); + if (ret) + dev_err(card->dev, "Failed to disable LPAIF dig clk: %d\n", ret); + } static const struct snd_soc_ops msm8916_qdsp6_be_ops = { @@ -279,6 +322,23 @@ static void msm8916_qdsp6_add_ops(struct snd_soc_card *card) } } +static void msm8953_qdsp6_add_ops(struct snd_soc_card *card) +{ + struct apq8016_sbc_data *pdata = snd_soc_card_get_drvdata(card); + + pdata->q6afe_clk_ver = Q6AFE_CLK_V2; + msm8916_qdsp6_add_ops(card); +} + +static void msm8976_qdsp6_add_ops(struct snd_soc_card *card) +{ + struct apq8016_sbc_data *pdata = snd_soc_card_get_drvdata(card); + + pdata->q6afe_clk_ver = Q6AFE_CLK_V1; + pdata->dig_cdc_mclk_en = true; + msm8916_qdsp6_add_ops(card); +} + static const struct snd_kcontrol_new apq8016_sbc_snd_controls[] = { SOC_DAPM_PIN_SWITCH("Headphone Jack"), SOC_DAPM_PIN_SWITCH("Mic Jack"), @@ -343,6 +403,8 @@ static int apq8016_sbc_platform_probe(struct platform_device *pdev) static const struct of_device_id apq8016_sbc_device_id[] __maybe_unused = { { .compatible = "qcom,apq8016-sbc-sndcard", .data = apq8016_sbc_add_ops }, { .compatible = "qcom,msm8916-qdsp6-sndcard", .data = msm8916_qdsp6_add_ops }, + { .compatible = "qcom,msm8953-qdsp6-sndcard", .data = msm8953_qdsp6_add_ops }, + { .compatible = "qcom,msm8976-qdsp6-sndcard", .data = msm8976_qdsp6_add_ops }, {}, }; MODULE_DEVICE_TABLE(of, apq8016_sbc_device_id);