From patchwork Fri Aug 2 05:55:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 816361 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D620335C0; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722578119; cv=none; b=I7IMlAPxH/KAtpaqhD2rrdHwxfOxrc8qTRqLtJ+Xvn7RsWhU/p8mQWioXBnzF0tdHSi8HEFW20X7TmWUf0WIrictcO9gA4brIufw1CE0DiryAtX3ZtCAWK19E1s3UICt72TC2PbkJ/mvmjezvzpRsRbyNm7MbJnuNhYjNJjqrG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722578119; c=relaxed/simple; bh=z+/bbibB7haQjY5NkNZVL8klnDC2hXm8Zfuofz+R8Ck=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WT7naYxei9YWWqC4vB6l/IKUW1yXF2P9FaVXix7XQ33yG94/4k+Xyj4xd+8Bf170ghA43q5zlk/oMFUybJv2k47d+CqZ74CmXshZlENcEftxR2tDClQwIIxEgG0hdJozNPt6jEncxzndDZ3mum/53JPESpeEJ30OLT7L6gUx28c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hCw4Hw5j; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hCw4Hw5j" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3770BC4AF09; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722578119; bh=z+/bbibB7haQjY5NkNZVL8klnDC2hXm8Zfuofz+R8Ck=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hCw4Hw5jNu6juv04ldDJZhw/ATOY4zG3uUbhheVWMf3X8fm5Q6U23ITrT538xVIDR VDcyySVuZc0PRHDlB9gRY4QayXqJO+cSF8h5QnSVmk21jXFXNWbC2ZSm6kFf5RfUgg LO8GBHw05lCa904ZaZfq2651Ra7Pp5vebqF5+dB7xhUPVed+01zNvqtYHPg2ykGa53 rGPZ3VucFk7btTBjc51chIqVLCAObkIK+Ckte6IwftgV9kSiyHJelp0r7pYgwuDsB1 8Ki0zNkcRZUGTkRpKKhtA99Gfc4SKLjUdXqJPCXYyyoDqxr+kiwE/bURKuDPtFBDD5 VEFCfPnkWsdLA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23401C52D72; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Fri, 02 Aug 2024 11:25:00 +0530 Subject: [PATCH v5 1/4] PCI/portdrv: Make use of pci_dev::bridge_d3 for checking the D3 possibility Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240802-pci-bridge-d3-v5-1-2426dd9e8e27@linaro.org> References: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> In-Reply-To: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> To: Bjorn Helgaas , "Rafael J. Wysocki" , Len Brown Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, lukas@wunner.de, mika.westerberg@linux.intel.com, Manivannan Sadhasivam , Hsin-Yi Wang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1613; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=yht1diuW60Yop5/MJv61ZmShJUebX/GlA7kDcmFMjJk=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmrHTC/WwYy2qeJjZ533ltqs4myHg2ephLfnjaa 88YaDf3/OaJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqx0wgAKCRBVnxHm/pHO 9ajrCACDX9M1OQiUvAHCdt5y/BA9vHawznd1tH4hTb3nJK8n/6kNEfLMDhmwA8MSkNfE1c9v9lj ECeeyKSLzwztu4Fi1/mgf2sK1UZwHrhTz3aozN4Ll7G13WXkMBYTtKHniV+vZXpVX/BV25rZR8y saJbDjOS+H6g8iiydB32M1mvUN/bZLE48kWjT+FPw5sHKsOCVIAlY4WzcXNeUnuO6k6i0K4XaZx KiNj7YAr0GUinezr9e1e9zeJgzPry+a6FWPaZ6hY8vgOThxKPOvQRtt2U/MV0O/ibEVHYnEjG52 jfv65jm1/C5VMXdRKjTSndaSQKRVp8UIcpA69FZiEA0bMaR1 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam PCI core is already caching the value of pci_bridge_d3_possible() in pci_dev::bridge_d3 during pci_pm_init(). Since the value is not going to change, let's make use of the cached value. Tested-by: Hsin-Yi Wang Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pcie/portdrv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 14a4b89a3b83..1f02e5d7b2e9 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -702,7 +702,7 @@ static int pcie_portdrv_probe(struct pci_dev *dev, dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE | DPM_FLAG_SMART_SUSPEND); - if (pci_bridge_d3_possible(dev)) { + if (dev->bridge_d3) { /* * Keep the port resumed 100ms to make sure things like * config space accesses from userspace (lspci) will not @@ -720,7 +720,7 @@ static int pcie_portdrv_probe(struct pci_dev *dev, static void pcie_portdrv_remove(struct pci_dev *dev) { - if (pci_bridge_d3_possible(dev)) { + if (dev->bridge_d3) { pm_runtime_forbid(&dev->dev); pm_runtime_get_noresume(&dev->dev); pm_runtime_dont_use_autosuspend(&dev->dev); @@ -733,7 +733,7 @@ static void pcie_portdrv_remove(struct pci_dev *dev) static void pcie_portdrv_shutdown(struct pci_dev *dev) { - if (pci_bridge_d3_possible(dev)) { + if (dev->bridge_d3) { pm_runtime_forbid(&dev->dev); pm_runtime_get_noresume(&dev->dev); pm_runtime_dont_use_autosuspend(&dev->dev); From patchwork Fri Aug 2 05:55:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 816360 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD0CC3D982; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722578119; cv=none; b=qZUsygraCn7QhIxC2VgqdTB16lwbSXmMs4xp/LDXDf1vx/MfPt53Ml65JZ38lcWk8c9XFt7+f1b19bK7nfbFvMqjwEkIduNsyoviRbf/ZyiM1DRZjxxlReS4RvOxlzhlcjPOXV3/TaltLoK+jU7BcnKqjr64H+oMX+xYXXw/1UU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722578119; c=relaxed/simple; bh=2oOLSwZBpER+fZyeqXw9zPR5Y8Qfiqz8767N5YxtuLU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z221ZST/InS/r/UZdqqVy+jp7+c7Hn+tmKVahvin/TBvyUiwtQA0GimGs3a7GsCd7bVGRKNLig6B6xsjbTs8plSzWnJknpRc8WuQXSVnj5NITlJ7ggD5Cw+6t1wfGTbP7MkVzNxjG1AVOl4i3A+mF+7Wxu92WminU9l+lGk+aCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cTHKtKH0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cTHKtKH0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 43E3DC4AF0A; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722578119; bh=2oOLSwZBpER+fZyeqXw9zPR5Y8Qfiqz8767N5YxtuLU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cTHKtKH0x0K4jUorzs3sSp+LiQefTiaCIlsbNQ1YoCsiutkgsPCCFt4AQzabQsgYs o1ctamuIEayaMJ7UnvtrlBvFhegMglkP0c8YOI2bh/lU79YVjOcvVlaX7O46PrRAap HdxHdDxwrfi7CnjcQjzxxibANBL2tVa35upRZcJFf0N/POrXNPsc7S9WIB5fvyx8ym TKmMyVVT/5ZN7H8H3cip8llCY2c5E1+nre0zWRbpi00fiDElECw2xQjFQDB/b/OMcn gelIPSQJs+dOPsyvRsPhw2xVI02fIjKXm2PoQbymReg+hA7gzNvx6u8an4epXuww8M Mtr8ZJkUBHWAw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32A36C52D70; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Fri, 02 Aug 2024 11:25:01 +0530 Subject: [PATCH v5 2/4] PCI: Rename pci_bridge_d3_possible() to pci_bridge_d3_allowed() Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240802-pci-bridge-d3-v5-2-2426dd9e8e27@linaro.org> References: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> In-Reply-To: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> To: Bjorn Helgaas , "Rafael J. Wysocki" , Len Brown Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, lukas@wunner.de, mika.westerberg@linux.intel.com, Manivannan Sadhasivam , Bjorn Helgaas , Hsin-Yi Wang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=8312; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=GHrE4/WAAdQZRtTkchDWpjeIs/pSQnBrSg7T9J3wJiQ=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmrHTCu6YnayPL+5a/XwseNd/yFsK4K2oSYiSj+ 41/m1Wj7reJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqx0wgAKCRBVnxHm/pHO 9WAOB/9MbWubQKHItHwS3BYSnjjKo27Bx6FMGf11h2VBR9EDdPCyC63ocW4PooEzMIrjj2rVGoN abW5nzspKSZecn1wM3QYiQlmBcPL18dkPi2w1PbYCvt065ox9F9s7u5dSRVaa8P+5H+OGWMdJ3E 6Ta90T2Tf7Tzxw1qCpCmxz3L5btbKLMq1Qh7+C7RM1wWb949E/xHLGdVf98AKd6C9vZNxaz+QaE oKhhF0mvdLRDhAGCcks4VlwDEXITH5lbUKqGCpuTbd2c8H7/W5aILE/dXruq0fN6D5DolAXioKI 4ChVXYQHE/u9vt5pl8K7ULRm+UTfoYDRBD8mwWkVYUG26Q6t X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam As per the 'PCI Bus Power Management Interface Specification' v1.2, all devices should support D3 states (both D3Hot and D3Cold). So the term 'possible' doesn't make sense for the bridge devices, since D3 states should be possible as per the design. But due to various circumstances, D3 states might not be allowed for the bridges. In those cases, the API should be called 'pci_bridge_d3_allowed()' to reflect the actual behavior. So let's rename it. This also warrants renaming the variable 'bridge_d3' in 'struct pci_dev' to 'bridge_d3_allowed' for the reason cited above. No functional change. Reported-by: Bjorn Helgaas Closes: https://lore.kernel.org/linux-pci/20240305175107.GA539676@bhelgaas/ Tested-by: Hsin-Yi Wang Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pci-acpi.c | 8 ++++---- drivers/pci/pci.c | 18 +++++++++--------- drivers/pci/pci.h | 4 ++-- drivers/pci/pcie/portdrv.c | 14 +++++++------- include/linux/pci.h | 2 +- 5 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 004575091596..0f260cdc4592 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1429,12 +1429,12 @@ void pci_acpi_setup(struct device *dev, struct acpi_device *adev) device_set_wakeup_capable(dev, true); /* - * For bridges that can do D3 we enable wake automatically (as - * we do for the power management itself in that case). The + * For bridges that are allowed to do D3, we enable wake automatically + * (as we do for the power management itself in that case). The * reason is that the bridge may have additional methods such as * _DSW that need to be called. */ - if (pci_dev->bridge_d3) + if (pci_dev->bridge_d3_allowed) device_wakeup_enable(dev); acpi_pci_wakeup(pci_dev, false); @@ -1452,7 +1452,7 @@ void pci_acpi_cleanup(struct device *dev, struct acpi_device *adev) pci_acpi_remove_pm_notifier(adev); if (adev->wakeup.flags.valid) { acpi_device_power_remove_dependent(adev, dev); - if (pci_dev->bridge_d3) + if (pci_dev->bridge_d3_allowed) device_wakeup_disable(dev); device_set_wakeup_capable(dev, false); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e5f243dd4288..0edc4e448c2d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2967,13 +2967,13 @@ static const struct dmi_system_id bridge_d3_blacklist[] = { }; /** - * pci_bridge_d3_possible - Is it possible to put the bridge into D3 + * pci_bridge_d3_allowed - Is it allowed to put the bridge into D3 * @bridge: Bridge to check * - * This function checks if it is possible to move the bridge to D3. + * This function checks if the bridge is allowed to move to D3. * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. */ -bool pci_bridge_d3_possible(struct pci_dev *bridge) +bool pci_bridge_d3_allowed(struct pci_dev *bridge) { if (!pci_is_pcie(bridge)) return false; @@ -3060,14 +3060,14 @@ void pci_bridge_d3_update(struct pci_dev *dev) bool d3cold_ok = true; bridge = pci_upstream_bridge(dev); - if (!bridge || !pci_bridge_d3_possible(bridge)) + if (!bridge || !pci_bridge_d3_allowed(bridge)) return; /* * If D3 is currently allowed for the bridge, removing one of its * children won't change that. */ - if (remove && bridge->bridge_d3) + if (remove && bridge->bridge_d3_allowed) return; /* @@ -3087,12 +3087,12 @@ void pci_bridge_d3_update(struct pci_dev *dev) * so we need to go through all children to find out if one of them * continues to block D3. */ - if (d3cold_ok && !bridge->bridge_d3) + if (d3cold_ok && !bridge->bridge_d3_allowed) pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, &d3cold_ok); - if (bridge->bridge_d3 != d3cold_ok) { - bridge->bridge_d3 = d3cold_ok; + if (bridge->bridge_d3_allowed != d3cold_ok) { + bridge->bridge_d3_allowed = d3cold_ok; /* Propagate change to upstream bridges */ pci_bridge_d3_update(bridge); } @@ -3167,7 +3167,7 @@ void pci_pm_init(struct pci_dev *dev) dev->pm_cap = pm; dev->d3hot_delay = PCI_PM_D3HOT_WAIT; dev->d3cold_delay = PCI_PM_D3COLD_WAIT; - dev->bridge_d3 = pci_bridge_d3_possible(dev); + dev->bridge_d3_allowed = pci_bridge_d3_allowed(dev); dev->d3cold_allowed = true; dev->d1_support = false; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 17fed1846847..53ca75639201 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -92,7 +92,7 @@ void pci_pm_init(struct pci_dev *dev); void pci_ea_init(struct pci_dev *dev); void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); -bool pci_bridge_d3_possible(struct pci_dev *dev); +bool pci_bridge_d3_allowed(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); @@ -113,7 +113,7 @@ static inline bool pci_power_manageable(struct pci_dev *pci_dev) * Currently we allow normal PCI devices and PCI bridges transition * into D3 if their bridge_d3 is set. */ - return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; + return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3_allowed; } static inline bool pcie_downstream_port(const struct pci_dev *dev) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 1f02e5d7b2e9..8401a0f7b394 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -632,7 +632,7 @@ __setup("pcie_ports=", pcie_port_setup); #ifdef CONFIG_PM static int pcie_port_runtime_suspend(struct device *dev) { - if (!to_pci_dev(dev)->bridge_d3) + if (!to_pci_dev(dev)->bridge_d3_allowed) return -EBUSY; return pcie_port_device_runtime_suspend(dev); @@ -641,11 +641,11 @@ static int pcie_port_runtime_suspend(struct device *dev) static int pcie_port_runtime_idle(struct device *dev) { /* - * Assume the PCI core has set bridge_d3 whenever it thinks the port - * should be good to go to D3. Everything else, including moving + * Assume the PCI core has set bridge_d3_allowed whenever it thinks the + * port should be good to go to D3. Everything else, including moving * the port to D3, is handled by the PCI core. */ - return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY; + return to_pci_dev(dev)->bridge_d3_allowed ? 0 : -EBUSY; } static const struct dev_pm_ops pcie_portdrv_pm_ops = { @@ -702,7 +702,7 @@ static int pcie_portdrv_probe(struct pci_dev *dev, dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE | DPM_FLAG_SMART_SUSPEND); - if (dev->bridge_d3) { + if (dev->bridge_d3_allowed) { /* * Keep the port resumed 100ms to make sure things like * config space accesses from userspace (lspci) will not @@ -720,7 +720,7 @@ static int pcie_portdrv_probe(struct pci_dev *dev, static void pcie_portdrv_remove(struct pci_dev *dev) { - if (dev->bridge_d3) { + if (dev->bridge_d3_allowed) { pm_runtime_forbid(&dev->dev); pm_runtime_get_noresume(&dev->dev); pm_runtime_dont_use_autosuspend(&dev->dev); @@ -733,7 +733,7 @@ static void pcie_portdrv_remove(struct pci_dev *dev) static void pcie_portdrv_shutdown(struct pci_dev *dev) { - if (dev->bridge_d3) { + if (dev->bridge_d3_allowed) { pm_runtime_forbid(&dev->dev); pm_runtime_get_noresume(&dev->dev); pm_runtime_dont_use_autosuspend(&dev->dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 16493426a04f..2a48c88512e1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -375,7 +375,7 @@ struct pci_dev { unsigned int d2_support:1; /* Low power state D2 is supported */ unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ unsigned int no_d3cold:1; /* D3cold is forbidden */ - unsigned int bridge_d3:1; /* Allow D3 for bridge */ + unsigned int bridge_d3_allowed:1; /* Allow D3 for bridge */ unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ unsigned int mmio_always_on:1; /* Disallow turning off io/mem decoding during BAR sizing */ From patchwork Fri Aug 2 05:55:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 816821 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C41E1757D; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722578119; cv=none; b=P2Zchr7lC185iTsuXUhGYwNGi6oRqjryLkNrhXhZcWUYv5UPoKFy79zvQnUevSRn2Lz+wvqpVP3Gk7DKQJ8sFt8tVaMUunK0zLukqq/+IMiwnOk6e2KevPAPmP2ulxNJF6mqi7miaYvib0PFmlLPFHdY2hD5uYkgJE/gefd1jZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722578119; c=relaxed/simple; bh=AxtWneldSm9lWW9WolDLawhVdargn0y7wRo9Jq5s5bM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ECZHQrrKZn61vb4dQlhiVs2J0QryA2mpbVnTuwp5Ld8mKexVziVdvnPlwblHsPCfrYWLCTAsxqI45jZzzQeu4g6Dx3As2Wlx5tcuyO9TtyaBTAIFTvovVCF9fbuE4JneHJZBMdd9giNX14VvbJnsSg3tOFru1eOBUVPpKsAOIqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uH9yK/A8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uH9yK/A8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 51FB2C4AF10; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722578119; bh=AxtWneldSm9lWW9WolDLawhVdargn0y7wRo9Jq5s5bM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=uH9yK/A8KTiUnCB/wRYsNBm0efNp8duBcSc069zmKigPfqvhXBl7apgtSV9dJ5YUR oLaZCs45pxm0NL/c8sl1UIJ0Xx7dsJVgzCcQf0BIm9WJ4356uVJGHatsm05qwSZA12 uqt9Y5T/cuQmNtQKAoy/Io51mcyAhGJiAOOjCxJ7W0REFi1vT7dQfIbiRW5lyI1mql cAFopYdUFhvF2CsJ0BlvK0gfoGnjT9wFva9s3AtRgnsOMsETluECCuozdKV/Q4//Q6 uXXALrK9NU3S84iyEp55fWkrFyDC4wPf+wmlO0VVMkmeoNiTANq1lfCRK/ZAYTqopH Fyfb8OtOwAnuw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42628C52D74; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Fri, 02 Aug 2024 11:25:02 +0530 Subject: [PATCH v5 3/4] PCI: Decouple D3Hot and D3Cold handling for bridges Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240802-pci-bridge-d3-v5-3-2426dd9e8e27@linaro.org> References: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> In-Reply-To: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> To: Bjorn Helgaas , "Rafael J. Wysocki" , Len Brown Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, lukas@wunner.de, mika.westerberg@linux.intel.com, Manivannan Sadhasivam , Hsin-Yi Wang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=14065; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+UbyNghldovQGDHW5wq3Nj4VVWdDPl/7KL/Kc/Mfuk8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmrHTDcZGAfECZCzal9nJj1EC6T9sSHUpElLz/U tpd6E2wjOCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqx0wwAKCRBVnxHm/pHO 9aHyB/9qqryeGB3K4b7HlcJ8Sy2v9Uj+lqG+0AkeZFRfYHOpSEKyDXCZpfK6MJ8BKg2XWw8U6Eb RvXAjwruIb3iuzZF0xb7PGxhNlWVLHBLTZnTPKROthzT/bSzg43kp3KQfcy+aKt1Fh0JoBbe9RJ QqOsDLa7WyOW2Izr5XE4cj/C+tWEhZtO22zJ30nPKxT5t3wESXtN8BxrbACLOrVjRblMCl68hsv OCzn9idBp4jwjh3hWni+wjZtUfZup6r4NFwnXM4I4BYy+dVmCJrWV4bTvqhgt/HBLe1zNiKTuc/ fohRmJRSJ2DXfmR5t3/bi5HY1NBbAOGEZ/lTt3x95MrqIs1Q X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Currently, there is no proper distinction between D3Hot and D3Cold while handling the power management for PCI bridges. For instance, pci_bridge_d3_allowed() API decides whether it is allowed to put the bridge in D3, but it doesn't explicitly specify whether D3Hot or D3Cold is allowed in a scenario. This often leads to confusion and may be prone to errors. So let's split the D3Hot and D3Cold handling where possible. The current pci_bridge_d3_allowed() API is now split into pci_bridge_d3hot_allowed() and pci_bridge_d3cold_allowed() APIs and used in relevant places. Also, pci_bridge_d3_update() API is now renamed to pci_bridge_d3cold_update() since it was only used to check the possibility of D3Cold. Note that it is assumed that only D3Hot needs to be checked while transitioning the bridge during runtime PM and D3Cold in other places. In the ACPI case, wakeup is now only enabled if both D3Hot and D3Cold are allowed for the bridge. Still, there are places where just 'd3' is used opaquely, but those are hard to distinguish, hence left for future cleanups. Tested-by: Hsin-Yi Wang Signed-off-by: Manivannan Sadhasivam --- drivers/pci/bus.c | 2 +- drivers/pci/pci-acpi.c | 5 +-- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/pci.c | 78 ++++++++++++++++++++++++++++++---------------- drivers/pci/pci.h | 12 ++++--- drivers/pci/pcie/portdrv.c | 16 +++++----- drivers/pci/remove.c | 2 +- include/linux/pci.h | 3 +- 8 files changed, 75 insertions(+), 45 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 826b5016a101..cb1a1aaefa90 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -346,7 +346,7 @@ void pci_bus_add_device(struct pci_dev *dev) of_pci_make_dev_node(dev); pci_create_sysfs_dev_files(dev); pci_proc_attach_device(dev); - pci_bridge_d3_update(dev); + pci_bridge_d3cold_update(dev); dev->match_driver = !dn || of_device_is_available(dn); retval = device_attach(&dev->dev); diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 0f260cdc4592..aaf5a68e7984 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1434,7 +1434,7 @@ void pci_acpi_setup(struct device *dev, struct acpi_device *adev) * reason is that the bridge may have additional methods such as * _DSW that need to be called. */ - if (pci_dev->bridge_d3_allowed) + if (pci_dev->bridge_d3cold_allowed && pci_dev->bridge_d3hot_allowed) device_wakeup_enable(dev); acpi_pci_wakeup(pci_dev, false); @@ -1452,7 +1452,8 @@ void pci_acpi_cleanup(struct device *dev, struct acpi_device *adev) pci_acpi_remove_pm_notifier(adev); if (adev->wakeup.flags.valid) { acpi_device_power_remove_dependent(adev, dev); - if (pci_dev->bridge_d3_allowed) + if (pci_dev->bridge_d3cold_allowed && + pci_dev->bridge_d3hot_allowed) device_wakeup_disable(dev); device_set_wakeup_capable(dev, false); diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 40cfa716392f..45628b0dd116 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -529,7 +529,7 @@ static ssize_t d3cold_allowed_store(struct device *dev, return -EINVAL; pdev->d3cold_allowed = !!val; - pci_bridge_d3_update(pdev); + pci_bridge_d3cold_update(pdev); pm_runtime_resume(dev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 0edc4e448c2d..c7a4f961ec28 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -166,9 +166,9 @@ bool pci_ats_disabled(void) } EXPORT_SYMBOL_GPL(pci_ats_disabled); -/* Disable bridge_d3 for all PCIe ports */ +/* Disable both D3Hot and D3Cold for all PCIe ports */ static bool pci_bridge_d3_disable; -/* Force bridge_d3 for all PCIe ports */ +/* Force both D3Hot and D3Cold for all PCIe ports */ static bool pci_bridge_d3_force; static int __init pcie_port_pm_setup(char *str) @@ -2966,14 +2966,11 @@ static const struct dmi_system_id bridge_d3_blacklist[] = { { } }; -/** - * pci_bridge_d3_allowed - Is it allowed to put the bridge into D3 - * @bridge: Bridge to check - * - * This function checks if the bridge is allowed to move to D3. - * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. +/* + * Helper function to check whether it is allowed to put the bridge into D3 + * states (D3Hot and D3Cold). */ -bool pci_bridge_d3_allowed(struct pci_dev *bridge) +static bool pci_bridge_d3_allowed(struct pci_dev *bridge, pci_power_t state) { if (!pci_is_pcie(bridge)) return false; @@ -3026,6 +3023,32 @@ bool pci_bridge_d3_allowed(struct pci_dev *bridge) return false; } +/** + * pci_bridge_d3cold_allowed - Is it allowed to put the bridge into D3Cold + * @bridge: Bridge to check + * + * This function checks if the bridge is allowed to move to D3Cold. + * Currently we only allow D3Cold for recent enough PCIe ports on ACPI based + * platforms and Thunderbolt. + */ +bool pci_bridge_d3cold_allowed(struct pci_dev *bridge) +{ + return pci_bridge_d3_allowed(bridge, PCI_D3cold); +} + +/** + * pci_bridge_d3hot_allowed - Is it allowed to put the bridge into D3Hot + * @bridge: Bridge to check + * + * This function checks if the bridge is allowed to move to D3Hot. + * Currently we only allow D3Hot for recent enough PCIe ports on ACPI based + * platforms and Thunderbolt. + */ +bool pci_bridge_d3hot_allowed(struct pci_dev *bridge) +{ + return pci_bridge_d3_allowed(bridge, PCI_D3hot); +} + static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) { bool *d3cold_ok = data; @@ -3046,55 +3069,55 @@ static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) } /* - * pci_bridge_d3_update - Update bridge D3 capabilities + * pci_bridge_d3cold_update - Update bridge D3Cold capabilities * @dev: PCI device which is changed * * Update upstream bridge PM capabilities accordingly depending on if the * device PM configuration was changed or the device is being removed. The * change is also propagated upstream. */ -void pci_bridge_d3_update(struct pci_dev *dev) +void pci_bridge_d3cold_update(struct pci_dev *dev) { bool remove = !device_is_registered(&dev->dev); struct pci_dev *bridge; bool d3cold_ok = true; bridge = pci_upstream_bridge(dev); - if (!bridge || !pci_bridge_d3_allowed(bridge)) + if (!bridge || !pci_bridge_d3cold_allowed(bridge)) return; /* - * If D3 is currently allowed for the bridge, removing one of its + * If D3Cold is currently allowed for the bridge, removing one of its * children won't change that. */ - if (remove && bridge->bridge_d3_allowed) + if (remove && bridge->bridge_d3cold_allowed) return; /* - * If D3 is currently allowed for the bridge and a child is added or - * changed, disallowance of D3 can only be caused by that child, so + * If D3Cold is currently allowed for the bridge and a child is added or + * changed, disallowance of D3Cold can only be caused by that child, so * we only need to check that single device, not any of its siblings. * - * If D3 is currently not allowed for the bridge, checking the device - * first may allow us to skip checking its siblings. + * If D3Cold is currently not allowed for the bridge, checking the + * device first may allow us to skip checking its siblings. */ if (!remove) pci_dev_check_d3cold(dev, &d3cold_ok); /* - * If D3 is currently not allowed for the bridge, this may be caused + * If D3Cold is currently not allowed for the bridge, this may be caused * either by the device being changed/removed or any of its siblings, * so we need to go through all children to find out if one of them - * continues to block D3. + * continues to block D3Cold. */ - if (d3cold_ok && !bridge->bridge_d3_allowed) + if (d3cold_ok && !bridge->bridge_d3cold_allowed) pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, &d3cold_ok); - if (bridge->bridge_d3_allowed != d3cold_ok) { - bridge->bridge_d3_allowed = d3cold_ok; + if (bridge->bridge_d3cold_allowed != d3cold_ok) { + bridge->bridge_d3cold_allowed = d3cold_ok; /* Propagate change to upstream bridges */ - pci_bridge_d3_update(bridge); + pci_bridge_d3cold_update(bridge); } } @@ -3110,7 +3133,7 @@ void pci_d3cold_enable(struct pci_dev *dev) { if (dev->no_d3cold) { dev->no_d3cold = false; - pci_bridge_d3_update(dev); + pci_bridge_d3cold_update(dev); } } EXPORT_SYMBOL_GPL(pci_d3cold_enable); @@ -3127,7 +3150,7 @@ void pci_d3cold_disable(struct pci_dev *dev) { if (!dev->no_d3cold) { dev->no_d3cold = true; - pci_bridge_d3_update(dev); + pci_bridge_d3cold_update(dev); } } EXPORT_SYMBOL_GPL(pci_d3cold_disable); @@ -3167,7 +3190,8 @@ void pci_pm_init(struct pci_dev *dev) dev->pm_cap = pm; dev->d3hot_delay = PCI_PM_D3HOT_WAIT; dev->d3cold_delay = PCI_PM_D3COLD_WAIT; - dev->bridge_d3_allowed = pci_bridge_d3_allowed(dev); + dev->bridge_d3cold_allowed = pci_bridge_d3cold_allowed(dev); + dev->bridge_d3hot_allowed = pci_bridge_d3hot_allowed(dev); dev->d3cold_allowed = true; dev->d1_support = false; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 53ca75639201..f819eab793fc 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -92,8 +92,9 @@ void pci_pm_init(struct pci_dev *dev); void pci_ea_init(struct pci_dev *dev); void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); -bool pci_bridge_d3_allowed(struct pci_dev *dev); -void pci_bridge_d3_update(struct pci_dev *dev); +bool pci_bridge_d3cold_allowed(struct pci_dev *dev); +bool pci_bridge_d3hot_allowed(struct pci_dev *dev); +void pci_bridge_d3cold_update(struct pci_dev *dev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); static inline void pci_wakeup_event(struct pci_dev *dev) @@ -111,9 +112,12 @@ static inline bool pci_power_manageable(struct pci_dev *pci_dev) { /* * Currently we allow normal PCI devices and PCI bridges transition - * into D3 if their bridge_d3 is set. + * into D3 states if both bridge_d3cold_allowed and bridge_d3hot_allowed + * are set. */ - return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3_allowed; + return !pci_has_subordinate(pci_dev) || + (pci_dev->bridge_d3cold_allowed && + pci_dev->bridge_d3hot_allowed); } static inline bool pcie_downstream_port(const struct pci_dev *dev) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 8401a0f7b394..655754b9f06a 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -632,7 +632,7 @@ __setup("pcie_ports=", pcie_port_setup); #ifdef CONFIG_PM static int pcie_port_runtime_suspend(struct device *dev) { - if (!to_pci_dev(dev)->bridge_d3_allowed) + if (!to_pci_dev(dev)->bridge_d3hot_allowed) return -EBUSY; return pcie_port_device_runtime_suspend(dev); @@ -641,11 +641,11 @@ static int pcie_port_runtime_suspend(struct device *dev) static int pcie_port_runtime_idle(struct device *dev) { /* - * Assume the PCI core has set bridge_d3_allowed whenever it thinks the - * port should be good to go to D3. Everything else, including moving - * the port to D3, is handled by the PCI core. + * Assume the PCI core has set bridge_d3hot_allowed whenever it thinks + * the port should be good to go to D3Hot. Everything else, including + * moving the port to D3Hot, is handled by the PCI core. */ - return to_pci_dev(dev)->bridge_d3_allowed ? 0 : -EBUSY; + return to_pci_dev(dev)->bridge_d3hot_allowed ? 0 : -EBUSY; } static const struct dev_pm_ops pcie_portdrv_pm_ops = { @@ -702,7 +702,7 @@ static int pcie_portdrv_probe(struct pci_dev *dev, dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE | DPM_FLAG_SMART_SUSPEND); - if (dev->bridge_d3_allowed) { + if (dev->bridge_d3hot_allowed) { /* * Keep the port resumed 100ms to make sure things like * config space accesses from userspace (lspci) will not @@ -720,7 +720,7 @@ static int pcie_portdrv_probe(struct pci_dev *dev, static void pcie_portdrv_remove(struct pci_dev *dev) { - if (dev->bridge_d3_allowed) { + if (dev->bridge_d3hot_allowed) { pm_runtime_forbid(&dev->dev); pm_runtime_get_noresume(&dev->dev); pm_runtime_dont_use_autosuspend(&dev->dev); @@ -733,7 +733,7 @@ static void pcie_portdrv_remove(struct pci_dev *dev) static void pcie_portdrv_shutdown(struct pci_dev *dev) { - if (dev->bridge_d3_allowed) { + if (dev->bridge_d3hot_allowed) { pm_runtime_forbid(&dev->dev); pm_runtime_get_noresume(&dev->dev); pm_runtime_dont_use_autosuspend(&dev->dev); diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index d749ea8250d6..36d8cb50b582 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -41,7 +41,7 @@ static void pci_destroy_dev(struct pci_dev *dev) pci_doe_destroy(dev); pcie_aspm_exit_link_state(dev); - pci_bridge_d3_update(dev); + pci_bridge_d3cold_update(dev); pci_free_resources(dev); put_device(&dev->dev); } diff --git a/include/linux/pci.h b/include/linux/pci.h index 2a48c88512e1..d0947f932b9a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -375,7 +375,8 @@ struct pci_dev { unsigned int d2_support:1; /* Low power state D2 is supported */ unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ unsigned int no_d3cold:1; /* D3cold is forbidden */ - unsigned int bridge_d3_allowed:1; /* Allow D3 for bridge */ + unsigned int bridge_d3cold_allowed:1; /* Allow D3Cold for bridge */ + unsigned int bridge_d3hot_allowed:1; /* Allow D3Hot for bridge */ unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ unsigned int mmio_always_on:1; /* Disallow turning off io/mem decoding during BAR sizing */ From patchwork Fri Aug 2 05:55:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 816819 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABBDB3D97F; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722578119; cv=none; b=f9R4AnNxg/v7SFQ7liAAxTViFzEkKUjfbUx7sTh+yRfqZljgZ8fXVEaJRovfGVVn7EXgksVrnOv12Uh76//ZZUfxe+vQjdX7LW6SCJtMOWhp398Av0u4YVXDnLbrQm2bQ8t+NjmpzYHC+EAtUSLqPozB8u+0zdE6UhrDJi3C6cA= ARC-Message-Signature: i=1; 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b=fknCQwrKbaeH+FLdDZ4sQrJDl+LtRbdRuC8NQss+/xaIMaAyf/+0v0ya3F6fwSeQ1 K3aZGf0RZ4FInf1OCJ9yYED6CmGzVflUgkuDE6K6F7gk7bDkmtfs8kQRT1okAeNabP emQdoF2PwfEGVTkpLCDJUC9CQGt8BUTra1h+0y5R1SVZBfhTgTbJ1z66REsTgBBmfW YM5gh+7gxAjLquTZO73PwqTYBqvq56fPHjwN5AgjBZ27s4/kiWDaR8fQpxHYR3IN6/ H5s2Xo+hTACWMntame/2jhoS99yw64smB6S4oPD42UPPoyLtMiAmwUTChGzqw5Euts cGgnzGFmropbQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 510CCC52D73; Fri, 2 Aug 2024 05:55:19 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Fri, 02 Aug 2024 11:25:03 +0530 Subject: [PATCH v5 4/4] PCI: Allow PCI bridges to go to D3Hot on all Devicetree based platforms Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240802-pci-bridge-d3-v5-4-2426dd9e8e27@linaro.org> References: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> In-Reply-To: <20240802-pci-bridge-d3-v5-0-2426dd9e8e27@linaro.org> To: Bjorn Helgaas , "Rafael J. Wysocki" , Len Brown Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, lukas@wunner.de, mika.westerberg@linux.intel.com, Manivannan Sadhasivam , Hsin-Yi Wang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1909; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=ysTqE45coqPvykQRZRe0VeyavgQ9+sgZKnMnxkXaMrs=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmrHTDk+wYKSA4ReZo++MT1k+y+mL9mpBeuq5iS rN1qLy+ebqJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqx0wwAKCRBVnxHm/pHO 9bj2B/9CHofWJVlPBG6X2dbdioyUIDnUxWxbrl1XR2oQVu+HOTwlWR1Jk7diQuhO3z4OjhGUR0w R9l3pknbtJ982jDRmJDsHMK3y4rQj3hHflT9zMSeF4qnzGmHEk8V06arY61nfyDQYN8scYnz+hx 8Jf1GktYNZKDlyfF5+oRkJcn3YYLd5pawJ/G21JvXgsmyUI01CKXjpXewgKJoRpanKDt8+YkZHv MY41deRlZ1Crer5imiCiS8WGeEA3Hq9mVA9W4VLS1+2qpAPpM4gQ4+PV1TcqeUPQd7PH7OJoqy/ r6+Zldu8WZQpd8iKpFFT/uIcKjLIyuq6EMKvXh0Iw0+ZKF6d X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Unlike ACPI based platforms, there are no known issues with D3Hot for the PCI bridges in the Devicetree based platforms. So let's allow the PCI bridges to go to D3Hot during runtime. It should be noted that the bridges need to be defined in Devicetree for this to work. Currently, D3Cold is not allowed since Vcc supply which is required for transitioning the device to D3Cold is not exposed on all Devicetree based platforms. Tested-by: Hsin-Yi Wang Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pci.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c7a4f961ec28..bc1e1ca673f1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2992,6 +2992,18 @@ static bool pci_bridge_d3_allowed(struct pci_dev *bridge, pci_power_t state) if (pci_bridge_d3_force) return true; + /* + * Allow D3Hot for all Devicetree based platforms having a + * separate node for the bridge. We don't allow D3Cold for now + * since not all platforms are exposing the Vcc supply in + * Devicetree which is required for transitioning the bridge to + * D3Cold. + * + * NOTE: The bridge is expected to be defined in Devicetree. + */ + if (state == PCI_D3hot && dev_of_node(&bridge->dev)) + return true; + /* Even the oldest 2010 Thunderbolt controller supports D3. */ if (bridge->is_thunderbolt) return true; @@ -3042,7 +3054,7 @@ bool pci_bridge_d3cold_allowed(struct pci_dev *bridge) * * This function checks if the bridge is allowed to move to D3Hot. * Currently we only allow D3Hot for recent enough PCIe ports on ACPI based - * platforms and Thunderbolt. + * platforms, Thunderbolt and Devicetree based platforms. */ bool pci_bridge_d3hot_allowed(struct pci_dev *bridge) {