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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ecb129sm544015566b.222.2024.08.06.05.52.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 01/28] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState Date: Tue, 6 Aug 2024 14:51:29 +0200 Message-ID: <20240806125157.91185-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao We'll have to add LoongsonIPIClass in few commits, so rename LoongsonIPI as LoongsonIPIState for clarity. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-2-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 6 +++--- hw/intc/loongson_ipi.c | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 3f795edbf3..efb772f384 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -31,10 +31,10 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI) +OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) typedef struct IPICore { - LoongsonIPI *ipi; + LoongsonIPIState *ipi; MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; @@ -45,7 +45,7 @@ typedef struct IPICore { qemu_irq irq; } IPICore; -struct LoongsonIPI { +struct LoongsonIPIState { SysBusDevice parent_obj; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 682cec96f3..903483ae80 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPI *ipi = s->ipi; + LoongsonIPIState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_realize(DeviceState *dev, Error **errp) { - LoongsonIPI *s = LOONGSON_IPI(dev); + LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -320,7 +320,7 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) static void loongson_ipi_unrealize(DeviceState *dev) { - LoongsonIPI *s = LOONGSON_IPI(dev); + LoongsonIPIState *s = LOONGSON_IPI(dev); g_free(s->cpu); } @@ -344,14 +344,14 @@ static const VMStateDescription vmstate_loongson_ipi = { .version_id = 2, .minimum_version_id = 2, .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu, + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, vmstate_ipi_core, IPICore), VMSTATE_END_OF_LIST() } }; static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1), + DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -369,7 +369,7 @@ static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPI), + .instance_size = sizeof(LoongsonIPIState), .class_init = loongson_ipi_class_init, } }; From patchwork Tue Aug 6 12:51:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817032 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782339wrh; Tue, 6 Aug 2024 05:52:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX1CWvjWET/lPBD6K6Z14z3lrsLQJZqAdpLYBb5b7qVDTppxJNgyPdEe8Nfoq5azXuegZzFw3Q+LCy8GOjVVwNM X-Google-Smtp-Source: AGHT+IE5bkvS4Q5DmGw0xZiT06rGBcdrZiEfIrUAwSvRmvOqC2M0IYPHEQy56qzpafCHISf7+LaI X-Received: by 2002:a05:620a:4050:b0:79f:d80:5930 with SMTP id af79cd13be357-7a34efe3073mr2049513185a.52.1722948752255; Tue, 06 Aug 2024 05:52:32 -0700 (PDT) ARC-Seal: i=1; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bc3cf3sm556585666b.13.2024.08.06.05.52.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 02/28] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() Date: Tue, 6 Aug 2024 14:51:30 +0200 Message-ID: <20240806125157.91185-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao In preparation to extract common IPI code in few commits, extract loongson_ipi_common_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-3-philmd@linaro.org> --- hw/intc/loongson_ipi.c | 40 ++++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 903483ae80..8aab7e48e8 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void loongson_ipi_realize(DeviceState *dev, Error **errp) +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -301,30 +301,46 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); s->cpu = g_new0(IPICore, s->num_cpu); - if (s->cpu == NULL) { - error_setg(errp, "Memory allocation for IPICore faile"); - return; - } - for (i = 0; i < s->num_cpu; i++) { s->cpu[i].ipi = s; - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); - g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); } } -static void loongson_ipi_unrealize(DeviceState *dev) +static void loongson_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPIState *s = LOONGSON_IPI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + Error *local_err = NULL; + + loongson_ipi_common_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + for (unsigned i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); + g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); + sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + } +} + +static void loongson_ipi_common_unrealize(DeviceState *dev) { LoongsonIPIState *s = LOONGSON_IPI(dev); g_free(s->cpu); } +static void loongson_ipi_unrealize(DeviceState *dev) +{ + loongson_ipi_common_unrealize(dev); +} + static const VMStateDescription vmstate_ipi_core = { .name = "ipi-single", .version_id = 2, From patchwork Tue Aug 6 12:51:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817033 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782636wrh; Tue, 6 Aug 2024 05:53:23 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW4SQacME6N2eyIFkvJwA0eJNCfVpxQZ+5tqogmuFnH0urPeEerfgBTiBy3cB1RfLyICXf1+RBfM/u+p606JP94 X-Google-Smtp-Source: AGHT+IF3Q6GbTNNUgsk7uFFjtO4M1L9aYXiysNpIeIef0XlCxq35mHfYvnWoCFmAFzomUhaYylTy X-Received: by 2002:a05:620a:4087:b0:796:de79:f577 with SMTP id af79cd13be357-7a34eeb6b40mr2735685185a.7.1722948803716; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ec7266sm547817866b.196.2024.08.06.05.52.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 03/28] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub Date: Tue, 6 Aug 2024 14:51:31 +0200 Message-ID: <20240806125157.91185-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-4-philmd@linaro.org> --- MAINTAINERS | 4 ++++ include/hw/intc/loongson_ipi.h | 14 ++++++++++++-- include/hw/intc/loongson_ipi_common.h | 26 ++++++++++++++++++++++++++ hw/intc/loongson_ipi.c | 10 +++++++--- hw/intc/loongson_ipi_common.c | 22 ++++++++++++++++++++++ hw/intc/Kconfig | 4 ++++ hw/intc/meson.build | 1 + 7 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongson_ipi_common.c diff --git a/MAINTAINERS b/MAINTAINERS index e34c2bd4cd..5ca701cf0c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1250,8 +1250,10 @@ F: configs/devices/loongarch64-softmmu/default.mak F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c @@ -1386,11 +1388,13 @@ Loongson-3 virtual platforms M: Huacai Chen R: Jiaxun Yang S: Maintained +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: hw/intc/loongson_liointc.c F: hw/mips/loongson3_bootp.c F: hw/mips/loongson3_bootp.h F: hw/mips/loongson3_virt.c +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: include/hw/intc/loongson_liointc.h F: tests/avocado/machine_mips_loongson3v.py diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index efb772f384..9c9030761e 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -8,6 +8,8 @@ #ifndef HW_LOONGSON_IPI_H #define HW_LOONGSON_IPI_H +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" /* Mainy used by iocsr read and write */ @@ -31,7 +33,7 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) +OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; @@ -45,8 +47,16 @@ typedef struct IPICore { qemu_irq irq; } IPICore; +struct LoongsonIPIClass { + LoongsonIPICommonClass parent_class; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; +}; + struct LoongsonIPIState { - SysBusDevice parent_obj; + LoongsonIPICommonState parent_obj; + MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h new file mode 100644 index 0000000000..70ac69d0ba --- /dev/null +++ b/include/hw/intc/loongson_ipi_common.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson ipi interrupt header files + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGSON_IPI_COMMON_H +#define HW_LOONGSON_IPI_COMMON_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" +OBJECT_DECLARE_TYPE(LoongsonIPICommonState, + LoongsonIPICommonClass, LOONGSON_IPI_COMMON) + +struct LoongsonIPICommonState { + SysBusDevice parent_obj; +}; + +struct LoongsonIPICommonClass { + SysBusDeviceClass parent_class; +}; + +#endif diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 8aab7e48e8..7d15c28e94 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -374,9 +374,12 @@ static Property ipi_properties[] = { static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); - dc->realize = loongson_ipi_realize; - dc->unrealize = loongson_ipi_unrealize; + device_class_set_parent_realize(dc, loongson_ipi_realize, + &lic->parent_realize); + device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, + &lic->parent_unrealize); device_class_set_props(dc, ipi_properties); dc->vmsd = &vmstate_loongson_ipi; } @@ -384,8 +387,9 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_LOONGSON_IPI_COMMON, .instance_size = sizeof(LoongsonIPIState), + .class_size = sizeof(LoongsonIPIClass), .class_init = loongson_ipi_class_init, } }; diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c new file mode 100644 index 0000000000..43002fe556 --- /dev/null +++ b/hw/intc/loongson_ipi_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson IPI interrupt common support + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/intc/loongson_ipi_common.h" + +static const TypeInfo loongarch_ipi_common_types[] = { + { + .name = TYPE_LOONGSON_IPI_COMMON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(LoongsonIPICommonState), + .class_size = sizeof(LoongsonIPICommonClass), + .abstract = true, + } +}; + +DEFINE_TYPES(loongarch_ipi_common_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 58b6d3a710..a2a0fdca85 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -87,8 +87,12 @@ config GOLDFISH_PIC config M68K_IRQC bool +config LOONGSON_IPI_COMMON + bool + config LOONGSON_IPI bool + select LOONGSON_IPI_COMMON config LOONGARCH_PCH_PIC bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index afd1aa51ee..a09a527207 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -69,6 +69,7 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) From patchwork Tue Aug 6 12:51:32 2024 Content-Type: text/plain; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e8383dsm551798066b.173.2024.08.06.05.52.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 04/28] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h Date: Tue, 6 Aug 2024 14:51:32 +0200 Message-ID: <20240806125157.91185-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philmd@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-5-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 18 ------------------ include/hw/intc/loongson_ipi_common.h | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 9c9030761e..70e00dc1a7 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,24 +12,6 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -/* Mainy used by iocsr read and write */ -#define SMP_IPI_MAILBOX 0x1000ULL -#define CORE_STATUS_OFF 0x0 -#define CORE_EN_OFF 0x4 -#define CORE_SET_OFF 0x8 -#define CORE_CLEAR_OFF 0xc -#define CORE_BUF_20 0x20 -#define CORE_BUF_28 0x28 -#define CORE_BUF_30 0x30 -#define CORE_BUF_38 0x38 -#define IOCSR_IPI_SEND 0x40 -#define IOCSR_MAIL_SEND 0x48 -#define IOCSR_ANY_SEND 0x158 - -#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) -#define MAIL_SEND_OFFSET 0 -#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) - #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 70ac69d0ba..b43b77bda6 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -23,4 +23,23 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; }; +/* Mainy used by iocsr read and write */ +#define SMP_IPI_MAILBOX 0x1000ULL + +#define CORE_STATUS_OFF 0x0 +#define CORE_EN_OFF 0x4 +#define CORE_SET_OFF 0x8 +#define CORE_CLEAR_OFF 0xc +#define CORE_BUF_20 0x20 +#define CORE_BUF_28 0x28 +#define CORE_BUF_30 0x30 +#define CORE_BUF_38 0x38 +#define IOCSR_IPI_SEND 0x40 +#define IOCSR_MAIL_SEND 0x48 +#define IOCSR_ANY_SEND 0x158 + +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) + #endif From patchwork Tue Aug 6 12:51:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817040 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782748wrh; Tue, 6 Aug 2024 05:53:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXgOMq2oCEsAGdyRu0wJx1tjwEaM0kYqInoEsLv6h2h3huMz5mJV04wMEmmqviXgA/pFmAszV1cZkuYudKxsh4G X-Google-Smtp-Source: AGHT+IFDDd5Ig5cyBbpqTsbj/GAKExPlyHDtracL5Q/3FTiIg7X4H5V4Paw/pvqXMirOae1i9FzO X-Received: by 2002:a05:620a:4495:b0:79f:190a:8ad7 with SMTP id af79cd13be357-7a34ef3c238mr1723388885a.33.1722948823879; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bcb19csm544275866b.42.2024.08.06.05.52.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 05/28] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState Date: Tue, 6 Aug 2024 14:51:33 +0200 Message-ID: <20240806125157.91185-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao It is easier to manage one array of MMIO MR rather than one per vCPU. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-6-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 2 +- hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 70e00dc1a7..5a52dfbf4d 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; - MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; uint32_t set; @@ -39,6 +38,7 @@ struct LoongsonIPIClass { struct LoongsonIPIState { LoongsonIPICommonState parent_obj; + MemoryRegion *ipi_mmio_mem; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 7d15c28e94..03878b896f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } + s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); for (unsigned i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } @@ -338,6 +338,10 @@ static void loongson_ipi_common_unrealize(DeviceState *dev) static void loongson_ipi_unrealize(DeviceState *dev) { + LoongsonIPIState *s = LOONGSON_IPI(dev); + + g_free(s->ipi_mmio_mem); + loongson_ipi_common_unrealize(dev); } From patchwork Tue Aug 6 12:51:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817034 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782684wrh; Tue, 6 Aug 2024 05:53:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUrtdgHScfBQAHjtJGoDKGFFrwS0k/ZRh+98zS/X3t11FxinKDCFdRX+NIRtURkWq9XVH0yziFwr9YSVs2jy0Qc X-Google-Smtp-Source: AGHT+IEl2M0/pXDwP98gkiMERX2fiFGIf1hj1RORVnNDVS7YDvYu5GSsPgGOrGE1726sgrV7B9oZ X-Received: by 2002:ac8:580a:0:b0:447:f89a:4d37 with SMTP id d75a77b69052e-4518929e522mr197775541cf.44.1722948813351; Tue, 06 Aug 2024 05:53:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948813; cv=none; d=google.com; s=arc-20160816; b=mg9GIUaWaYJgrjqtk4f1wHaU4b7Wy9kn122BcaZ4wc17272yxONVNyQnhlhVCOJ4Hf 2+JphyXpIXvLWyYF5m5ZKUotrMYnzjQwq+sgKfafWFv/kyQ3VtTQiellE9RIPCu4v/VO DxUiFm7gOBIvHlOnVkty3s+vvMG3RSPp3JumUTYGKUXA0JpEqIACGPo27XXUwppwsGeJ u9PcHbl0tG5bcB17grWk7/6ohjgJI+HNSu075Xjotz/BZnQwPjUhzyc22TlIHq7rExGV +GlW60+nGKLaY9Cmb3d1fHHhi1wmooL1ycIVmAHq7tvPhEIPFcWK86s/+YeiR1tPrXxU V36A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QwpY/JynEMtTkyIwPRmmw3TCd0WkcVnsonvQjUTWgeg=; fh=rxGWTSOrq9MmYE4+hMcV/u38d68oc92wX5eFok0A+84=; b=rMNITHJ8JGPqCguBuyAtO8qPf3loVs+SSDYRJBrf+4nrG9EVYAU/ZOJVnAEDx6GUiq KOybT44HICuclaqkatqiTJzblyr1l1iw6+aKrO3UuEt4PoPzxzzjf+e7xn5WpvwfHAk1 KxxGNJy66uROOV+LNK7OHoT8iE4D3G/IPqICZ2291qaFQu7aehydnUj1USj80WWFrnlh NPYr3rErbg6h0nkZiC10Uaxv+py9kpLNf9+BICe/lloHd7YkPqq/itBapWsBaaGFkFz5 K0mCUfm+UifBSzLnT77aMGQKdFXhW+vYE71+aot6xHIkSjHVbKmqqfepLHwYCiuKhoHP gDDA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lZ2HOj26; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ecabb2sm541820766b.214.2024.08.06.05.52.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 06/28] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h Date: Tue, 6 Aug 2024 14:51:34 +0200 Message-ID: <20240806125157.91185-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Move the IPICore structure and corresponding common fields of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h". Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-7-philmd@linaro.org> --- include/hw/intc/loongson_ipi.h | 17 --------- include/hw/intc/loongson_ipi_common.h | 18 ++++++++++ hw/intc/loongson_ipi.c | 50 ++++++--------------------- hw/intc/loongson_ipi_common.c | 42 ++++++++++++++++++++++ 4 files changed, 70 insertions(+), 57 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 5a52dfbf4d..4e517cc8dc 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,22 +12,9 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -#define IPI_MBX_NUM 4 - #define TYPE_LOONGSON_IPI "loongson_ipi" OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) -typedef struct IPICore { - LoongsonIPIState *ipi; - uint32_t status; - uint32_t en; - uint32_t set; - uint32_t clear; - /* 64bit buf divide into 2 32bit buf */ - uint32_t buf[IPI_MBX_NUM * 2]; - qemu_irq irq; -} IPICore; - struct LoongsonIPIClass { LoongsonIPICommonClass parent_class; @@ -39,10 +26,6 @@ struct LoongsonIPIState { LoongsonIPICommonState parent_obj; MemoryRegion *ipi_mmio_mem; - MemoryRegion ipi_iocsr_mem; - MemoryRegion ipi64_iocsr_mem; - uint32_t num_cpu; - IPICore *cpu; }; #endif diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index b43b77bda6..967c70ad1c 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -11,12 +11,30 @@ #include "qom/object.h" #include "hw/sysbus.h" +#define IPI_MBX_NUM 4 + #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" OBJECT_DECLARE_TYPE(LoongsonIPICommonState, LoongsonIPICommonClass, LOONGSON_IPI_COMMON) +typedef struct IPICore { + LoongsonIPICommonState *ipi; + uint32_t status; + uint32_t en; + uint32_t set; + uint32_t clear; + /* 64bit buf divide into 2 32-bit buf */ + uint32_t buf[IPI_MBX_NUM * 2]; + qemu_irq irq; +} IPICore; + struct LoongsonIPICommonState { SysBusDevice parent_obj; + + MemoryRegion ipi_iocsr_mem; + MemoryRegion ipi64_iocsr_mem; + uint32_t num_cpu; + IPICore *cpu; }; struct LoongsonIPICommonClass { diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 03878b896f..347bc26729 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPIState *ipi = s->ipi; + LoongsonIPICommonState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { - LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) static void loongson_ipi_realize(DeviceState *dev, Error **errp) { + LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; @@ -320,18 +321,19 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } - s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); - for (unsigned i = 0; i < s->num_cpu; i++) { + s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu); + for (unsigned i = 0; i < sc->num_cpu; i++) { g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); + &loongson_ipi_core_ops, &sc->cpu[i], name, 0x48); sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } static void loongson_ipi_common_unrealize(DeviceState *dev) { - LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); g_free(s->cpu); } @@ -345,36 +347,6 @@ static void loongson_ipi_unrealize(DeviceState *dev) loongson_ipi_common_unrealize(dev); } -static const VMStateDescription vmstate_ipi_core = { - .name = "ipi-single", - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_UINT32(status, IPICore), - VMSTATE_UINT32(en, IPICore), - VMSTATE_UINT32(set, IPICore), - VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_loongson_ipi = { - .name = TYPE_LOONGSON_IPI, - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, - vmstate_ipi_core, IPICore), - VMSTATE_END_OF_LIST() - } -}; - -static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -384,8 +356,6 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) &lic->parent_realize); device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); - device_class_set_props(dc, ipi_properties); - dc->vmsd = &vmstate_loongson_ipi; } static const TypeInfo loongson_ipi_types[] = { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 43002fe556..47796f7ece 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,6 +8,47 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +static const VMStateDescription vmstate_ipi_core = { + .name = "ipi-single", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_UINT32(status, IPICore), + VMSTATE_UINT32(en, IPICore), + VMSTATE_UINT32(set, IPICore), + VMSTATE_UINT32(clear, IPICore), + VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_loongson_ipi_common = { + .name = "loongson_ipi", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState, + num_cpu, vmstate_ipi_core, + IPICore), + VMSTATE_END_OF_LIST() + } +}; + +static Property ipi_common_properties[] = { + DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_props(dc, ipi_common_properties); + dc->vmsd = &vmstate_loongson_ipi_common; +} static const TypeInfo loongarch_ipi_common_types[] = { { @@ -15,6 +56,7 @@ static const TypeInfo loongarch_ipi_common_types[] = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(LoongsonIPICommonState), .class_size = sizeof(LoongsonIPICommonClass), + .class_init = loongson_ipi_common_class_init, .abstract = true, } }; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e83ec1sm545106766b.182.2024.08.06.05.52.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 07/28] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() Date: Tue, 6 Aug 2024 14:51:35 +0200 Message-ID: <20240806125157.91185-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao In order to get LoongsonIPICommonClass in send_ipi_data() in the next commit, propagate LoongsonIPICommonState. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-8-philmd@linaro.org> --- hw/intc/loongson_ipi.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 347bc26729..8bf16f26d4 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) return NULL; } -static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, - MemTxAttrs attrs) +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) { int i, mask = 0, data = 0; AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); @@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, return MEMTX_OK; } -static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = val & 0xffff; attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, @@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = { static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { + LoongsonIPICommonState *ipi = opaque; MemTxResult ret = MEMTX_OK; addr &= 0xfff; switch (addr) { case MAIL_SEND_OFFSET: - ret = mail_send(val, attrs); + ret = mail_send(ipi, val, attrs); break; case ANY_SEND_OFFSET: - ret = any_send(val, attrs); + ret = any_send(ipi, val, attrs); break; default: break; From patchwork Tue Aug 6 12:51:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817035 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782690wrh; Tue, 6 Aug 2024 05:53:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUokXFrikMUiYDCmdVUD15R5cFjVoSfejJSlZaAncFKg00r11Ifugb+XDXhMUvnydB5yu01zfaYsMuQm/ABuMgU X-Google-Smtp-Source: AGHT+IE2pSJIH3AnICEwnF+MjZrRewA0/XYH8ytXhOoknv8gVAULyeBtSyZ8/SM1O3AxTbVmUv4N X-Received: by 2002:a05:622a:11c1:b0:44f:f7c8:b157 with SMTP id d75a77b69052e-451892c0734mr166470691cf.55.1722948814072; Tue, 06 Aug 2024 05:53:34 -0700 (PDT) ARC-Seal: i=1; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5b83b82c068sm5896520a12.60.2024.08.06.05.52.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 08/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler Date: Tue, 6 Aug 2024 14:51:36 +0200 Message-ID: <20240806125157.91185-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Allow Loongson IPI implementations to have their own get_iocsr_as() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-9-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 2 ++ hw/intc/loongson_ipi.c | 16 ++++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 967c70ad1c..1a2ee41cc9 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -39,6 +39,8 @@ struct LoongsonIPICommonState { struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; + + AddressSpace *(*get_iocsr_as)(CPUState *cpu); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 8bf16f26d4..eb99de9068 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, return loongson_ipi_core_readl(s, addr, data, size, attrs); } -static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) -{ #ifdef TARGET_LOONGARCH64 +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} #endif + #ifdef TARGET_MIPS +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { return &MIPS_CPU(cpu)->env.iocsr.as; } -#endif + return NULL; } +#endif static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, uint64_t val, hwaddr addr, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int i, mask = 0, data = 0; - AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); if (!iocsr_as) { return MEMTX_DECODE_ERROR; @@ -354,11 +360,13 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); device_class_set_parent_realize(dc, loongson_ipi_realize, &lic->parent_realize); device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); + licc->get_iocsr_as = get_iocsr_as; } static const TypeInfo loongson_ipi_types[] = { From patchwork Tue Aug 6 12:51:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817038 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782723wrh; Tue, 6 Aug 2024 05:53:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUOd/cHdDh4xtQHuQbi9H6e6g66YbbjUCOtLbHTz8LOJgD1pp9JhquUj0pGoVJkNKmmCXnqNbTZpWDeV2fNRzQn X-Google-Smtp-Source: AGHT+IH97AwNFaLHiwDa/EfCSwhX679VSGxYPvgEDUrz5st2sOHL9I9HW0bOoDhaURxgLR7M1yD1 X-Received: by 2002:a05:622a:4d09:b0:451:a12d:b9e7 with SMTP id d75a77b69052e-451a12dbddfmr158624771cf.12.1722948818665; Tue, 06 Aug 2024 05:53:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948818; cv=none; d=google.com; s=arc-20160816; b=RMABETfVsweT2cRg0YhUrNf52ZME3HSbiJksKsfJCNFnRlwUMc/bJ7VryL8R78EGPT p23XtKwXaA8ZyBevT7DSns32JRe4UYoGN2fNAfPgcQHuS6K729w9/SMxbPBRHO3UV1wp jtSs7fmDasYM2tbZbqZFTUPaYlmw9TXtWGLSjIvUmKNBVImZky2N9M4rExaA5Ey4IKxR v/ddYe616flMbnVxH3gyWAQMnnx4m8kwRPPbjjQM48GL+besIr44NZ/Rp7IZSd7gM6nD qBWwtlpb2jNM6o4UeSQX2ZAVU7qKnzz5Nbjdrmk0ZJzhz70eVSNzKlGWknmc/MTw7n/Z FC7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Pc4HRKn0ABU9Etyo/i6+qtUkhxyrZpQEkVJjk1kRbzM=; fh=rxGWTSOrq9MmYE4+hMcV/u38d68oc92wX5eFok0A+84=; b=MHnxrMkoKxsfqky1eGTsAQwV7AH86jwWsSq3erhRcPra2o54Fg5oh/5wn0mhJebPBQ RJ0ehT/cPNPS6p8/v5UZWSRjOXNVGo6TJmXfTvIoPmczXxNP4Z4oFixkSg0GnEDu7H/k 4XcKSJEwlKz1dKo8EipjsgR6YBALzSVn4NQIV/Vv/NE64V6kZjE8zM4sEv2TrYm9v10w VMBa+04hzUbwkRzXVwzUA8gZoDgskT5E9oEUVbi4uruCkKw7Vs4Z8goHbAPo1O0RKipp 5tnIKevtppA0vnfokjgLCm8NYTLIgmugPxzOk1dDol1hVEVAObhRUvZWF1XrAyoTUNIL QPPw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zGVH41lO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e83eccsm543566666b.184.2024.08.06.05.52.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:52:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 09/28] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler Date: Tue, 6 Aug 2024 14:51:37 +0200 Message-ID: <20240806125157.91185-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=philmd@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Allow Loongson IPI implementations to have their own cpu_by_arch_id() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-10-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 1 + hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 1a2ee41cc9..8997676f0d 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -41,6 +41,7 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; AddressSpace *(*get_iocsr_as)(CPUState *cpu); + CPUState *(*cpu_by_arch_id)(int64_t id); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index eb99de9068..4a8e743528 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi, static MemTxResult any_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int index = 0; uint32_t cpuid; uint8_t vector; @@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, cpuid = extract32(val, 16, 10); /* IPI status vector */ vector = extract8(val, 0, 5); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { return MEMTX_DECODE_ERROR; } @@ -367,6 +370,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); licc->get_iocsr_as = get_iocsr_as; + licc->cpu_by_arch_id = cpu_by_arch_id; } static const TypeInfo loongson_ipi_types[] = { From patchwork Tue Aug 6 12:51:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817037 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782706wrh; Tue, 6 Aug 2024 05:53:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWcPpv8yy0NI8On1ZYUggjQR2c8zkwKoxLdYEYQp2L5t4hNdvD8tPGqTxi1GGgJm9OCqamuxMh9mVA7yEQQoeAK X-Google-Smtp-Source: AGHT+IGk8MWqTBzAviHVzqCD7ZQcESEtzlPOqeGmf5+r1gh+GXnA7ExP1PMXXkh0QEW/zdS0asE8 X-Received: by 2002:a0d:e484:0:b0:648:baba:542f with SMTP id 00721157ae682-6895964bb05mr166816367b3.0.1722948816049; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c61575sm546609166b.92.2024.08.06.05.53.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 10/28] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers Date: Tue, 6 Aug 2024 14:51:38 +0200 Message-ID: <20240806125157.91185-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao In order to access loongson_ipi_core_read/write helpers from loongson_ipi_common.c in the next commit, make their prototype declaration public. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-11-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 6 ++++++ hw/intc/loongson_ipi.c | 10 ++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 8997676f0d..65f8ef7957 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -10,6 +10,7 @@ #include "qom/object.h" #include "hw/sysbus.h" +#include "exec/memattrs.h" #define IPI_MBX_NUM 4 @@ -44,6 +45,11 @@ struct LoongsonIPICommonClass { CPUState *(*cpu_by_arch_id)(int64_t id); }; +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs); +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs); + /* Mainy used by iocsr read and write */ #define SMP_IPI_MAILBOX 0x1000ULL diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 4a8e743528..c13cb5a1d2 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,9 +24,8 @@ #endif #include "trace.h" -static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; uint64_t ret = 0; @@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi, return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; From patchwork Tue Aug 6 12:51:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817041 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1783059wrh; Tue, 6 Aug 2024 05:54:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUXCfjjxtZJ0Fibl2PzGhF+GlRarutori92ISPxOVZUNs6bUVv+k9wjRmuyg0vQCudZmbCAxZpQJYqViRihA4q/ X-Google-Smtp-Source: AGHT+IEdbz4xmlKF5xqAmdfxwtpXWncr6lkh74Zy/HyqWYO3+xllleH3Igb7QSwd1dKzOf7jmmTg X-Received: by 2002:a05:6358:89d:b0:1ac:f4a9:43 with SMTP id e5c5f4694b2df-1af3ba86eaemr1760638855d.2.1722948880554; Tue, 06 Aug 2024 05:54:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948880; cv=none; d=google.com; s=arc-20160816; b=pwFEnhCu0nnKK/jKFuU7f6oZa8iL4EQVypOOY8fxVeUoUAJ/VPoExh1cKb8C8wRXOd TJuJtEbg4fHjPJj6lyyFQp+HyOyvfqCyoXoy4iT+ghhjT/YiY3atmVUX2HCHIOIMAhXF XsUvOP1bE/SoiGoeL4/VfVK3LFL+cMQmokagFlAjwiwz63VG6MW8/Q48eaF1M/d70tcd rn3buxj6ZIoLP9NdP5wQDaqnSo/Nq/vy9T6N2AQagzV3nDR+iUE2o+Utt3UM0nv+gVrP VhNj+QmO3WmeVWxzjbYplB7zrgivgZxNF+BCPEq4GUF+hJ/afOZrZnkXEtVReXROUQwd 1ffg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fVXH7TtXrVZxOC7TgTKdtLSEQnAvMfiUURH/wkuD2/0=; fh=rxGWTSOrq9MmYE4+hMcV/u38d68oc92wX5eFok0A+84=; b=QbluacHq3bYMiOsUrq5qxrm8MO9wEgOYumYnvCD+yI6VXe2xxidTbGI+irpD6zJ32F i+K7zBXb9Oy9yDXPbUe1Axh8DHLF5qMHX9KTPbDcILb5f8ZVRfcd4tLRav88WwCxStFK z/ucZFtrT3A2qkidTa40kM+zthmDrW95rDyaFa2MzUzcVYKMnHYaxahnVg5VU9IJ56Ze tja0+9MhJp+pJzbagGJzhfdsDotSZ71Dk1Y4xEaGMdiuYkY2azvqW8QuVnOYgJWi74K5 pek4wrlO7LfMA+grJMXYHQfkJBWV5sVnPU+YItKo9LmB+szL0q+Ulz4PMQSxsSs+Fz+Q o6Aw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iAFFqXmg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5b83c22db88sm5838766a12.95.2024.08.06.05.53.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 11/28] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c Date: Tue, 6 Aug 2024 14:51:39 +0200 Message-ID: <20240806125157.91185-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Move the common code from loongson_ipi.c to loongson_ipi_common.c, call parent_realize() instead of loongson_ipi_common_realize() in loongson_ipi_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-12-philmd@linaro.org> --- include/hw/intc/loongson_ipi_common.h | 2 + hw/intc/loongson_ipi.c | 279 +------------------------ hw/intc/loongson_ipi_common.c | 283 ++++++++++++++++++++++++++ 3 files changed, 289 insertions(+), 275 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 65f8ef7957..df9d9c5168 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -41,6 +41,8 @@ struct LoongsonIPICommonState { struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; AddressSpace *(*get_iocsr_as)(CPUState *cpu); CPUState *(*cpu_by_arch_id)(int64_t id); }; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index c13cb5a1d2..0b88ae3230 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,56 +24,6 @@ #endif #include "trace.h" -MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - uint64_t ret = 0; - int index = 0; - - addr &= 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret = s->status; - break; - case CORE_EN_OFF: - ret = s->en; - break; - case CORE_SET_OFF: - ret = 0; - break; - case CORE_CLEAR_OFF: - ret = 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - ret = s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongson_ipi_read(size, (uint64_t)addr, ret); - *data = ret; - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_readl(s, addr, data, size, attrs); -} - #ifdef TARGET_LOONGARCH64 static AddressSpace *get_iocsr_as(CPUState *cpu) { @@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) } #endif -static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, - uint64_t val, hwaddr addr, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int i, mask = 0, data = 0; - AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); - - if (!iocsr_as) { - return MEMTX_DECODE_ERROR; - } - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); - for (i = 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |= 0xff << (i * 8); - } - } - } - - data &= mask; - data |= (val >> 32) & ~mask; - address_space_stl_le(iocsr_as, addr, data, attrs, NULL); - - return MEMTX_OK; -} - -static MemTxResult mail_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -static MemTxResult any_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = val & 0xffff; - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - LoongsonIPICommonState *ipi = s->ipi; - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int index = 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - addr &= 0xff; - trace_loongson_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en = val; - break; - case CORE_SET_OFF: - s->status |= val; - if (s->status != 0 && (s->status & s->en) != 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &= ~val; - if (s->status == 0 && s->en != 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - s->buf[index] = val; - break; - case IOCSR_IPI_SEND: - cpuid = extract32(val, 16, 10); - /* IPI status vector */ - vector = extract8(val, 0, 5); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, - BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } - - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_writel(s, addr, val, size, attrs); -} - static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, .write_with_attrs = loongson_ipi_core_writel, @@ -244,88 +52,15 @@ static const MemoryRegionOps loongson_ipi_core_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static const MemoryRegionOps loongson_ipi_iocsr_ops = { - .read_with_attrs = loongson_ipi_iocsr_readl, - .write_with_attrs = loongson_ipi_iocsr_writel, - .impl.min_access_size = 4, - .impl.max_access_size = 4, - .valid.min_access_size = 4, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - MemTxResult ret = MEMTX_OK; - - addr &= 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret = mail_send(ipi, val, attrs); - break; - case ANY_SEND_OFFSET: - ret = any_send(ipi, val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongson_ipi64_ops = { - .write_with_attrs = loongson_ipi_writeq, - .impl.min_access_size = 8, - .impl.max_access_size = 8, - .valid.min_access_size = 8, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) -{ - LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu == 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), - &loongson_ipi_iocsr_ops, - s, "loongson_ipi_iocsr", 0x48); - - /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard = true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongson_ipi64_ops, - s, "loongson_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu = g_new0(IPICore, s->num_cpu); - for (i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi = s; - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } -} - static void loongson_ipi_realize(DeviceState *dev, Error **errp) { LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; - loongson_ipi_common_realize(dev, &local_err); + lic->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -341,20 +76,14 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) } } -static void loongson_ipi_common_unrealize(DeviceState *dev) -{ - LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); - - g_free(s->cpu); -} - static void loongson_ipi_unrealize(DeviceState *dev) { LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPIClass *k = LOONGSON_IPI_GET_CLASS(dev); g_free(s->ipi_mmio_mem); - loongson_ipi_common_unrealize(dev); + k->parent_unrealize(dev); } static void loongson_ipi_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 47796f7ece..a6ce0181f6 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,8 +8,286 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" #include "migration/vmstate.h" +#include "trace.h" + +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + uint64_t ret = 0; + int index = 0; + + addr &= 0xff; + switch (addr) { + case CORE_STATUS_OFF: + ret = s->status; + break; + case CORE_EN_OFF: + ret = s->en; + break; + case CORE_SET_OFF: + ret = 0; + break; + case CORE_CLEAR_OFF: + ret = 0; + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + ret = s->buf[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); + break; + } + + trace_loongson_ipi_read(size, (uint64_t)addr, ret); + *data = ret; + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int i, mask = 0, data = 0; + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); + + if (!iocsr_as) { + return MEMTX_DECODE_ERROR; + } + + /* + * bit 27-30 is mask for byte writing, + * if the mask is 0, we need not to do anything. + */ + if ((val >> 27) & 0xf) { + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); + for (i = 0; i < 4; i++) { + /* get mask for byte writing */ + if (val & (0x1 << (27 + i))) { + mask |= 0xff << (i * 8); + } + } + } + + data &= mask; + data |= (val >> 32) & ~mask; + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); + + return MEMTX_OK; +} + +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = val & 0xffff; + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int index = 0; + uint32_t cpuid; + uint8_t vector; + CPUState *cs; + + addr &= 0xff; + trace_loongson_ipi_write(size, (uint64_t)addr, val); + switch (addr) { + case CORE_STATUS_OFF: + qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); + break; + case CORE_EN_OFF: + s->en = val; + break; + case CORE_SET_OFF: + s->status |= val; + if (s->status != 0 && (s->status & s->en) != 0) { + qemu_irq_raise(s->irq); + } + break; + case CORE_CLEAR_OFF: + s->status &= ~val; + if (s->status == 0 && s->en != 0) { + qemu_irq_lower(s->irq); + } + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + s->buf[index] = val; + break; + case IOCSR_IPI_SEND: + cpuid = extract32(val, 16, 10); + /* IPI status vector */ + vector = extract8(val, 0, 5); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); + break; + } + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_iocsr_ops = { + .read_with_attrs = loongson_ipi_iocsr_readl, + .write_with_attrs = loongson_ipi_iocsr_writel, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .valid.min_access_size = 4, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +/* mail send and any send only support writeq */ +static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + MemTxResult ret = MEMTX_OK; + + addr &= 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + ret = mail_send(ipi, val, attrs); + break; + case ANY_SEND_OFFSET: + ret = any_send(ipi, val, attrs); + break; + default: + break; + } + + return ret; +} + +static const MemoryRegionOps loongson_ipi64_ops = { + .write_with_attrs = loongson_ipi_writeq, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpu == 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), + &loongson_ipi_iocsr_ops, + s, "loongson_ipi_iocsr", 0x48); + + /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ + s->ipi_iocsr_mem.disable_reentrancy_guard = true; + + sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); + + memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), + &loongson_ipi64_ops, + s, "loongson_ipi64_iocsr", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); + + s->cpu = g_new0(IPICore, s->num_cpu); + for (i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi = s; + + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} + +static void loongson_ipi_common_unrealize(DeviceState *dev) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); + + g_free(s->cpu); +} static const VMStateDescription vmstate_ipi_core = { .name = "ipi-single", @@ -45,7 +323,12 @@ static Property ipi_common_properties[] = { static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + device_class_set_parent_realize(dc, loongson_ipi_common_realize, + &licc->parent_realize); + device_class_set_parent_unrealize(dc, loongson_ipi_common_unrealize, + &licc->parent_unrealize); device_class_set_props(dc, ipi_common_properties); dc->vmsd = &vmstate_loongson_ipi_common; } From patchwork Tue Aug 6 12:51:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817036 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1782702wrh; Tue, 6 Aug 2024 05:53:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWKGZoYDd5U06BglqrhHtp9rBPzcvNPPde54B6jsy5vBNPQMq6+ajBbG2NBPqZaIFraUV8gaok0sfnDJiyoUMGE X-Google-Smtp-Source: AGHT+IFRVGktpu4MTIgVUATEarKWUwAKb4ascyozIVa/MZ2T/pZD29mkp5W+M9/FwBnx635s5tpg X-Received: by 2002:a05:6358:c607:b0:1ac:f854:b68 with SMTP id e5c5f4694b2df-1af3bb8ccd4mr1541180255d.29.1722948815595; Tue, 06 Aug 2024 05:53:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948815; cv=none; d=google.com; s=arc-20160816; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d433fesm553882366b.142.2024.08.06.05.53.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 12/28] hw/intc/loongarch_ipi: Add loongarch IPI support Date: Tue, 6 Aug 2024 14:51:40 +0200 Message-ID: <20240806125157.91185-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Loongarch IPI is added here, it inherits from class TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can be used when ipi is emulated in userspace with KVM mode. Signed-off-by: Bibo Mao [PMD: Rebased and simplified] Co-Developed-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Signed-off-by: Philippe Mathieu-Daudé Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-13-philmd@linaro.org> --- include/hw/intc/loongarch_ipi.h | 25 ++++++++++++ hw/intc/loongarch_ipi.c | 68 +++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 4 ++ hw/intc/meson.build | 1 + 4 files changed, 98 insertions(+) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 hw/intc/loongarch_ipi.c diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h new file mode 100644 index 0000000000..276b3040a3 --- /dev/null +++ b/include/hw/intc/loongarch_ipi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch IPI interrupt header files + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_IPI_H +#define HW_LOONGARCH_IPI_H + +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" + +#define TYPE_LOONGARCH_IPI "loongarch_ipi" +OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI) + +struct LoongarchIPIState { + LoongsonIPICommonState parent_obj; +}; + +struct LoongarchIPIClass { + LoongsonIPICommonClass parent_class; +}; + +#endif diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c new file mode 100644 index 0000000000..2ae1a42c46 --- /dev/null +++ b/hw/intc/loongarch_ipi.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch IPI interrupt support + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/intc/loongarch_ipi.h" +#include "target/loongarch/cpu.h" + +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ + return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} + +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a = (CPUArchId *)a; + CPUArchId *archid_b = (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id = id; + found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, + sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +{ + MachineState *machine = MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid = find_cpu_by_archid(machine, arch_id); + if (archid) { + return CPU(archid->cpu); + } + + return NULL; +} + +static void loongarch_ipi_class_init(ObjectClass *klass, void *data) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + + licc->get_iocsr_as = get_iocsr_as; + licc->cpu_by_arch_id = loongarch_cpu_by_arch_id; +} + +static const TypeInfo loongarch_ipi_types[] = { + { + .name = TYPE_LOONGARCH_IPI, + .parent = TYPE_LOONGSON_IPI_COMMON, + .class_init = loongarch_ipi_class_init, + } +}; + +DEFINE_TYPES(loongarch_ipi_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index a2a0fdca85..dd405bdb5d 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -94,6 +94,10 @@ config LOONGSON_IPI bool select LOONGSON_IPI_COMMON +config LOONGARCH_IPI + bool + select LOONGSON_IPI_COMMON + config LOONGARCH_PCH_PIC bool select UNIMP diff --git a/hw/intc/meson.build b/hw/intc/meson.build index a09a527207..f4d81eb8e4 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c')) From patchwork Tue Aug 6 12:51:41 2024 Content-Type: text/plain; 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5b83b7245f8sm5968354a12.74.2024.08.06.05.53.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 13/28] hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI Date: Tue, 6 Aug 2024 14:51:41 +0200 Message-ID: <20240806125157.91185-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-14-philmd@linaro.org> --- include/hw/loongarch/virt.h | 1 - hw/loongarch/virt.c | 4 ++-- hw/loongarch/Kconfig | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 603c1cebdb..c373e48f27 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e592b1b6b7..29040422aa 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) */ /* Create IPI device */ - ipi = qdev_new(TYPE_LOONGSON_IPI); + ipi = qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 89be737726..0de713a439 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -12,7 +12,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS - select LOONGSON_IPI + select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI From patchwork Tue Aug 6 12:51:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817057 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1786643wrh; Tue, 6 Aug 2024 06:02:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW+aoqUkJXmBWZWZtjq3Vg2vBHLh3LM2C4uXUn+O3JxfiwUoj+zFtUOvyDE5TutiGY2fuLxi6WWHtiSVGYVQVLe X-Google-Smtp-Source: AGHT+IH6Fly4QfRl/zk24S6P8tAJiUf91h8mnk6ZTR5hXUrNy4uT8+b3z7az8h/xXcVleqmun1cQ X-Received: by 2002:a05:622a:1909:b0:447:df2d:7d39 with SMTP id d75a77b69052e-451892a777emr167030031cf.34.1722949357432; Tue, 06 Aug 2024 06:02:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949357; cv=none; d=google.com; s=arc-20160816; b=uPUC/0sEItGkYz2f3Y7f/GuaHbS1cwjLHXlertdGuWJTxSGFOhWVvOAwfr8VYk3LAP tgeBUNoOCDUmmoXKrOVtnEt6Elisr7HjaD0XRlvXZqR968Vz+r+gEBvSUoAIkMTGyVzQ s1XhILqFjfSnAJX7a5dAZdzVPYM8MCzDv3QTLqINymOsJDbgeB1PAFilYj6Zmj2W3G3T cq3kdzMdauW5CVv5FGvGS32+A+/jr9n83QafJyBTXN8PbazCHwM1sLWgb1vVnn3I1OnP I+bhpm3nHtftadAgjSYTQ1GDV5ro4FbpIMVYIlbKVdHw/Ps0mCMTqB1z3tKpjDrbWmLa ceeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0bpORwStJfo7fInBvcfsQRF1HWEiefExBVhtYwf29qI=; fh=rxGWTSOrq9MmYE4+hMcV/u38d68oc92wX5eFok0A+84=; b=ty+4Rv0FC0QxjmXeplOxons3htC+sg5hnkRN/kUH/bF6DmI0Ova+Rq5fPZnLO8/mUg 31LQXGcIYaokmC3LvCvz5vkO39yDuGfucI7Fw7Tps4OpH3uXBNg8XVxoMuW9Kgogt8CV 7pEQ8nnxGiygWtfjbI7GM6BuP/TI+NCEtxEMepK3QbGNUI0M3QigpDFgtcByANbNf8rJ koFBSHbKI72YBjJA8KHSBmjAHeiMo/HB4zcwlWJzTaMwoxKO2Ha5Sm9LQOTyq3oty+aB 9DMk15dkH3AUkEgirwjIVduAcTL3SrOGHGdLkSLQZeNWeFexyx/Nbu3RrHMKaUuXbA76 V5pg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zxu9xYWR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bb9b99f19fsm205716a12.92.2024.08.06.05.53.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bibo Mao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson , Jiaxun Yang Subject: [PULL 14/28] hw/intc/loongson_ipi: Restrict to MIPS Date: Tue, 6 Aug 2024 14:51:42 +0200 Message-ID: <20240806125157.91185-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=philmd@linaro.org; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Now than LoongArch target can use the TYPE_LOONGARCH_IPI model, restrict TYPE_LOONGSON_IPI to MIPS. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Acked-by: Song Gao Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Message-Id: <20240805180622.21001-15-philmd@linaro.org> --- MAINTAINERS | 2 -- hw/intc/loongson_ipi.c | 14 -------------- 2 files changed, 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5ca701cf0c..74a85360fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1251,10 +1251,8 @@ F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h F: include/hw/intc/loongson_ipi_common.h -F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c F: hw/intc/loongson_ipi_common.c -F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c F: gdb-xml/loongarch*.xml diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 0b88ae3230..8382ceca67 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -16,22 +16,9 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "migration/vmstate.h" -#ifdef TARGET_LOONGARCH64 -#include "target/loongarch/cpu.h" -#endif -#ifdef TARGET_MIPS #include "target/mips/cpu.h" -#endif #include "trace.h" -#ifdef TARGET_LOONGARCH64 -static AddressSpace *get_iocsr_as(CPUState *cpu) -{ - return LOONGARCH_CPU(cpu)->env.address_space_iocsr; -} -#endif - -#ifdef TARGET_MIPS static AddressSpace *get_iocsr_as(CPUState *cpu) { if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { @@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } -#endif static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, From patchwork Tue Aug 6 12:51:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817042 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1783066wrh; Tue, 6 Aug 2024 05:54:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX+ZDuABbYcOTIZzeGlE3cbnT8KbqaVjl+bU3SD160yG5ExYwLMhPFIhiVB106eZff/NXxBeQMlhbbkyZRRDwoa X-Google-Smtp-Source: AGHT+IFOek1ZfkyvigM5/fP1U5uelifDRib4NhS4xPR5yWF+edWvnSiBNOmeMp3wEG3IYIMJTDSQ X-Received: by 2002:a05:6830:2105:b0:708:b083:86c8 with SMTP id 46e09a7af769-709b995c407mr22324109a34.21.1722948882295; Tue, 06 Aug 2024 05:54:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948882; cv=none; d=google.com; s=arc-20160816; b=GBGVdkkoisSZqi0Uyhq2yEjGbcjUZViu6XmHjow7knN1yewLXxHNSPaNTlQyhEgyLu RsSNjf0iIMMSQZES5PAkI5s5QThJofFTu/qUkblvEvtxZgDyfMLJIc0mRbvGdaZhX8QZ jrxJoEsAMNs/dyyvpYYgBXjwRhNilAsODflZ3IPwSriQu7pzIJGk0iAXkPrfDIrKS6X9 ggW+oryrwxt/xvSkpQA9vBXMiMgA6p1lryWdARkjgYOJgwWMUBz6NZe+hN8z/j05rIwt 7t1qVkTV72VPAJY9U4M8yr/nhxEXTis7J9Jr40wPPuFjMpuG+YL5YdJuRuWVwXjJX74F A1Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wBx0ReACLauBHHw6c0ZSc7DkdUMOkNRvc02ZcjHiRGU=; fh=qtn8prgQtzf5IzCNvLChUZDElvNECP6ej9YfjQeBz3I=; b=CAFPt+ZusKtAOmFD7NCOFIJJllrDcOzphtdd4a3StPcFm7byzgzjhsA03ejqAJsTuf ANJLzX5SBK9f93x8uRr9H8MBN9dbRNwM1ygVExj8hBX/BnJZhiRwjEvT2sFcA682srvk 1qagZTY+jkqRkEq/81TtiGcEFcyco4c4/KWI+Jo0UNzjDUPlm3y2t6Zp27KtJ0xgtM1u 5jSLMhYRNj5tFqtG7A6UZSVM/BdhTw1aHdBAGgNZeEDlkuS51hltIperMzAswoQ7SVeG cwPeU54smJzkzOvT/x112VvwBvzNj7wXGxXq2r+jVl0NC9iqaqgtbNxs1lSS5+T5uhG2 Vebg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="uuGn/DaC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d43920sm542964866b.102.2024.08.06.05.53.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 15/28] hw/sd/sdcard: Explicit dummy byte value Date: Tue, 6 Aug 2024 14:51:43 +0200 Message-ID: <20240806125157.91185-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org On error the DAT lines are left unmodified to their previous states. QEMU returns 0x00 for convenience. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240730092138.32443-2-philmd@linaro.org> --- hw/sd/sd.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 07cb97d88c..de27e34fc8 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2478,20 +2478,22 @@ void sd_write_byte(SDState *sd, uint8_t value) uint8_t sd_read_byte(SDState *sd) { /* TODO: Append CRCs */ + const uint8_t dummy_byte = 0x00; uint8_t ret; uint32_t io_len; if (!sd->blk || !blk_is_inserted(sd->blk) || !sd->enable) - return 0x00; + return dummy_byte; if (sd->state != sd_sendingdata_state) { qemu_log_mask(LOG_GUEST_ERROR, "%s: not in Sending-Data state\n", __func__); - return 0x00; + return dummy_byte; } - if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION)) - return 0x00; + if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION)) { + return dummy_byte; + } io_len = sd_blk_len(sd); @@ -2517,7 +2519,7 @@ uint8_t sd_read_byte(SDState *sd) if (sd->data_offset == 0) { if (!address_in_range(sd, "READ_MULTIPLE_BLOCK", sd->data_start, io_len)) { - return 0x00; + return dummy_byte; } sd_blk_read(sd, sd->data_start, io_len); } From patchwork Tue Aug 6 12:51:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817045 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1783665wrh; Tue, 6 Aug 2024 05:56:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVhUiL3zXzozP8AolIKVI2buX5pEfxBcCbi7lyhSwaSmqb8Tsu4/udOJ63fgFnk7QGbMa0kPsYkOPjzC1bM6DoX X-Google-Smtp-Source: AGHT+IFww6ya7pYR/JMWCUWoTQDjbU7vQbdHg7rcl5QXAxJKKNgQrzGCvXA9JA8KQS2IaiwAwGuT X-Received: by 2002:a05:6358:3214:b0:1ac:f5dc:5163 with SMTP id e5c5f4694b2df-1af3bb93c3amr1866925055d.29.1722948988319; Tue, 06 Aug 2024 05:56:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948988; cv=none; d=google.com; s=arc-20160816; b=lfUrntRObsq0HEIiBLJBv6ByZtd/QxHUoD/G83Og+Mr0sDk3+8XNAg38L/D3FZKz4v k1ExTu6ii8LzC7B9w/rRsmYb4w7/W5nzyWeMQuxbq2ZNSeO97zkohiqwfU5J7ckGCL3W AcsSv5tjx6gGd8JcJ0YVcb8BbMnKPrJ7/t44Cq5zziPVmOHmrRuqBuXS+ft4JX1HrB5J 8/sRYjzBoR3d/T6l+WU3b9lcYT5i4TF/RZNNpF3sk/SRw5OmtH3cGNsM1TzvzkxrnLbo E7ZIgKPs6fm/YstLzAs/WrZsNxJkFycWjqZdRlZawkH+lqEtRpCVaqw2g3w9m79PdbLT MQog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fSCuGHe+AmukzYVW/13LuZhAtRaauQM2euUp0akLJd4=; fh=SJVSVookgcyZ3xhuRNVfkJ3f/S7xP2f7Ub1ylu5GG5E=; b=hO4f3ZHiXTlm38CC4CxajZxh33gksET+8tt6KPj9dFc22GEIuLtzOQqhLUD1xBOCAp yrnY+UQvOeWGpyLs76NMv+i/M1CvZqfhjmtzprqQbMgMrl9mZnHGHTqisX2i1SMjaHfx MW5AYOg6URiPu2DhmXXw8Lke82l4LUqKmkB8cAuVA5Ule7Q3bJy0Cd7c5sO/MJYKp1DH SGu8Md8/GgWGb9GUZ6F2vZsHXHYeZ3n6+1LY3VNlDwGerhZOVuAaW+An+UHrupchltm/ gyC/yrfPEbPN26J+zrPiwvrSmdsS8nZIv0bf3p5aLZQ3kBs6mbuJ88oeHoqu8TLZXRq1 +wwg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pFbcNHRW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c0c0e0sm549658566b.67.2024.08.06.05.53.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Zheyu Ma , Richard Henderson Subject: [PULL 16/28] hw/sd/sdcard: Do not abort when reading DAT lines on invalid cmd state Date: Tue, 6 Aug 2024 14:51:44 +0200 Message-ID: <20240806125157.91185-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Guest should not try to read the DAT lines from invalid command state. If it still insists to do so, return a dummy value. Cc: qemu-stable@nongnu.org Fixes: e2dec2eab0 ("hw/sd/sdcard: Remove default case in read/write on DAT lines") Reported-by: Zheyu Ma Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2454 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240730092138.32443-3-philmd@linaro.org> --- hw/sd/sd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index de27e34fc8..a140a32ccd 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2540,7 +2540,9 @@ uint8_t sd_read_byte(SDState *sd) break; default: - g_assert_not_reached(); + qemu_log_mask(LOG_GUEST_ERROR, "%s: DAT read illegal for command %s\n", + __func__, sd->last_cmd_name); + return dummy_byte; } return ret; From patchwork Tue Aug 6 12:51:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817044 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1783616wrh; Tue, 6 Aug 2024 05:56:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUqAHhCy+YIXFh/29RsSdAgkMPWc2Leq+XpsV8vBdw3Y4AMwwNObiCM+87OtMZEsSfMI+d4LJVrdxiQApDd8s6F X-Google-Smtp-Source: AGHT+IEgSH8X4d0hJiTXO5qUk43cuF3Li2laV+FhBH32s/rLLZeSCwBUUOi/CR49mI2m+2h13uQv X-Received: by 2002:a05:6830:2807:b0:70a:9876:b781 with SMTP id 46e09a7af769-70a9876b996mr17360674a34.34.1722948977756; Tue, 06 Aug 2024 05:56:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948977; cv=none; d=google.com; s=arc-20160816; b=X3BwMUsp62mzLSoXnQA4ITFAbTAqFVxcVeO9VU7qYPmJfsiTrY9B6/XBokUmxFNuig OzhHezXBzz3DVODMybg5DSuZJrU/Myi8VxNp+nchSLUAthCvoFFhTmNvAmUfmsdUnbSG Ah7JQ46hhAPpK2X87WU2BGauB3tJFzogCY7BCBMzKiRDz3K6IXYsSB5aJ7cK/CJU9s76 eZygn5khCYF+BKnp/yFSQmSI58EPcGDuVKndyayxz0xw8/hzN2ZT9mDzsUx02PW1L3Em tcO9oAKTNQ7FlUN1bW1JczaKLTqrz4VlCeFQZtiASivJIG+l8I0yTQ/7AIshO3KoTu5o LGiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qVol/losEhIcWq2r2tAtbopJaOl9RLGh9SWaxvA4wzc=; fh=SJVSVookgcyZ3xhuRNVfkJ3f/S7xP2f7Ub1ylu5GG5E=; b=0IfjxD+EpFeP4m9SZeaIcaqcCJWXpOY5+uufVXRzYCbeaIEssWJVo8pxTPV+KTFQjZ kweJva1EwslvxnmIzcGsjYxIWClldtdsGLqaleSnwj0wCIWhgfc60WI1AhCgE+veY8yX YQEbid+mI22995v7hcsZjzkFJdnOVcOtU2ntJ6LUmE7E5hmspuIUuaXaSxgVQCazePuG SSiluJmvtWrLYWOyXOUwCKK1PUqjckjoGlN3nAXsGAydQd2c9XtoAic4WvOxA0eqHTqc xSDhhDYGAG44W3eI/9jv1du2zxrugYWd2waKrAbrKkWPyk4rMswvuEjRQwtJcTxF/0iN RZaA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J6JVPJ0X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5baa6b916b8sm3653114a12.22.2024.08.06.05.53.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Zheyu Ma , Richard Henderson Subject: [PULL 17/28] hw/sd/sdhci: Reset @data_count index on invalid ADMA transfers Date: Tue, 6 Aug 2024 14:51:45 +0200 Message-ID: <20240806125157.91185-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We neglected to clear the @data_count index on ADMA error, allowing to trigger assertion in sdhci_read_dataport() or sdhci_write_dataport(). Cc: qemu-stable@nongnu.org Fixes: d7dfca0807 ("hw/sdhci: introduce standard SD host controller") Reported-by: Zheyu Ma Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2455 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240730092138.32443-4-philmd@linaro.org> --- hw/sd/sdhci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d02c3e3963..8293d83556 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -846,6 +846,7 @@ static void sdhci_do_adma(SDHCIState *s) } } if (res != MEMTX_OK) { + s->data_count = 0; if (s->errintstsen & SDHC_EISEN_ADMAERR) { trace_sdhci_error("Set ADMA error flag"); s->errintsts |= SDHC_EIS_ADMAERR; From patchwork Tue Aug 6 12:51:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817047 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1783859wrh; Tue, 6 Aug 2024 05:57:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWUbpnYzP9lUnDXbb6eo8Qv5RqxdpzGPFfuR+UT235C1k/2nihYktWb+4P9e6bN22g4okQNvKLsl7MOmX57umi6 X-Google-Smtp-Source: AGHT+IG4mOkSXWRRH5/h1s33SXvi/XIEhSj7kSYWjB6bO2ZVRKTkUafpD19h8Tbb59l4RHtnYtj6 X-Received: by 2002:a05:6214:4806:b0:6b2:b5c1:72dc with SMTP id 6a1803df08f44-6bb98440e01mr190017416d6.54.1722949027176; Tue, 06 Aug 2024 05:57:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949027; cv=none; d=google.com; s=arc-20160816; b=zIPIn5pG69gehe7Ns/3FeECIObzOtHX1bVs5Zxu7BCkEv+ahEXrcvXYkbwaNeCeT+6 YAeMGYWyxo3w5KbJ5IgbCX9de2AgjORMVIvkle5eI+6/cBhIIOhQprVXSv8Rv2klE/uZ WH2CWVqXBAGg/7Ey+Xsyqpef6OyIT6ildQO/n60stGf659jNC2K3sdlp80AkCm6rvhBF jFe61PmXptWPL4EAWu0SnEtLYDrMl4iUHjlJuBED6XEHx0Kdb4S+mbppj040njYWkcUS Qh1i9pepY1W22OrCgykuufwuy32SqoEe/lddB42pqGTrosyBQLOyhlB297fhp88P4NDq yS5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QOLg5Vi3ZKfkY84yToih/WZzzIJIKq2Y34KfZXOpYeQ=; fh=Hk4Ux6ISdDbx/Dmm9v/vXuLBRqmyPPWWk73tpT75Y8g=; b=t9ytdd07j0hAMRvpuWx4tbdzPb5Swr5zW2cW2pHI0DObhWxTUnZ2pOu5GzUqCzTGFG phuvCLx53Zlc/nZ212efwep/ty0RRK794/CIaARDGeN5U6XMrKSFHLDaEsiJblpzJacu UFbOaSBxoA+rQRS+lOsgE+QUWfseqZYGJG+2Hqe+Wnccuplhm/jWTHL9i32Lt8oxEYEc Ovo9mleGJp1sCwqL1Nqx2TR7gWGae4gz/OfX4V7XkWRANpqvBqJkeIUafiwjhUHJATjv njwZpnNj80BclFWKUAGhmVE9YCvYNDdySeWgUFHun9bcfwo4tDWbFUgorMoLOTey1b/a o+2g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=no95ZLQv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c0ca00sm545543866b.68.2024.08.06.05.53.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 18/28] hw/block/pflash_cfi01: Don't decrement pfl->counter below 0 Date: Tue, 6 Aug 2024 14:51:46 +0200 Message-ID: <20240806125157.91185-19-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In pflash_write() Coverity points out that we can decrement the unsigned pfl->counter below zero, which makes it wrap around. In fact this is harmless, because if pfl->counter is 0 at this point we also increment pfl->wcycle to 3, and the wcycle == 3 handling doesn't look at counter; the only way back into code which looks at the counter value is via wcycle == 1, which will reinitialize the counter. But it's arguably a little clearer to break early in the "counter == 0" if(), to avoid the decrement-below-zero. Resolves: Coverity CID 1547611 Signed-off-by: Peter Maydell Reviewed-by: Kevin Wolf Message-ID: <20240731143617.3391947-4-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index c8f1cf5a87..2f3d1dd509 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -614,6 +614,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, if (!pfl->counter) { trace_pflash_write(pfl->name, "block write finished"); pfl->wcycle++; + break; } pfl->counter--; From patchwork Tue Aug 6 12:51:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817054 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1786123wrh; Tue, 6 Aug 2024 06:01:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVWTgyRsHx77l+9Ljs9Od/2vJ8Ds/kxUvURidCTud73wpdvIiVUoY2rr4oe9FN3TT1E8taCXDi4P/6jpAEpq+lj X-Google-Smtp-Source: AGHT+IHkPbCy7ycGTIOyOPtBJWwaEYw295f97+LfbIQn9aWFz/YTa3oCGOXdvcgRqzdWHcsvLJFe X-Received: by 2002:a05:6214:4a02:b0:6b7:a81a:1340 with SMTP id 6a1803df08f44-6bb98441dabmr193422706d6.51.1722949310635; Tue, 06 Aug 2024 06:01:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949310; cv=none; d=google.com; s=arc-20160816; b=cNIA9MSYD6owOhob0r8Z81pIul16Uh2wiacQAVgOLX420BbZitLSYY26f5DhHlz0hV SmgOANbfyAcwYtznSbhpJ3HcXbJ96zs9raH6hIXvAQpFfR8TLK6NISgwfHvRGvYFnag1 mi0c7uAkikCbBv5JzJRKhCE5jMovVFzVpUBLERvHyeNnMJavXxTIiGiPhrpJ2RhSrM/O k/ysH+DrvZiNfpvLa/HktIYIbdN8aqie6F/j0txmXMrXuLreZJLpuQN56SL2GW3lFKxb l1F0LgjPRE52ce9Vzi04ptLwR/l22tAV/UuwFcpV5Rp3ydMWcGAyQvEy51l5hCzBKPq6 JLjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AMipe/hXLqtb3Ef8XbFqx4kLNXFlOJjSHmZuoVlilTA=; fh=OLWhW9PY8FnpOdOagGj3ODHuSts21bG5U9QIV67xEBE=; b=Mi1s5xNrGDI6xFr5zZ2+pT05P+FjmbgCV00Fafz4Qh3Js09HcHlij2Gkt5vmvKGEYV bhp0+OH/zwy61+8lAEYmTgAnweNCdJ0fKlQzZ9pDfGUy0NLF7KEahJjH711NcXKqWRZJ YQPeKGYB5YDf+jjXD4hbacWiDG6SprfrsJH0OqmVC3JmcqDrU40txjHKyZ2QIlFinLUh Ke1OqNjdFEdtH/ygDPnXoQCc0HnRxdm1UA4W1lkYamharFnR73BSHAEoDmwwxC5IUlZN TDirm/2M4d9MznHtEaeD93WgKTdxawOCmMiCkEfRRBVd3vzWKRpob/XTHJ76BhdElnaI 739Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M7lEONhJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e7fe3csm539363066b.162.2024.08.06.05.53.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:53:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Markus Armbruster , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 19/28] hw/ide/atapi: Be explicit that assigning to s->lcyl truncates Date: Tue, 6 Aug 2024 14:51:47 +0200 Message-ID: <20240806125157.91185-20-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In ide_atapi_cmd_reply_end() we calculate a 16-bit size, and then assign its two halves to s->lcyl and s->hcyl like this: s->lcyl = size; s->hcyl = size >> 8; Coverity warns that the first line here can overflow the 8-bit s->lcyl variable. This is true, and in this case we're deliberately only after the low 8 bits of the value. The code is clearer to both humans and Coverity if we're explicit that we only wanted the low 8 bits, though. Resolves: Coverity CID 1547621 Signed-off-by: Peter Maydell Reviewed-by: Markus Armbruster Reviewed-by: Kevin Wolf Message-ID: <20240731143617.3391947-5-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/ide/atapi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c index fcb6cca157..e82959dc2d 100644 --- a/hw/ide/atapi.c +++ b/hw/ide/atapi.c @@ -265,7 +265,7 @@ void ide_atapi_cmd_reply_end(IDEState *s) byte_count_limit--; size = byte_count_limit; } - s->lcyl = size; + s->lcyl = size & 0xff; s->hcyl = size >> 8; s->elementary_transfer_size = size; /* we cannot transmit more than one sector at a time */ From patchwork Tue Aug 6 12:51:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817056 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1786556wrh; Tue, 6 Aug 2024 06:02:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU71oFYWxEmAa2CsTPJTRLuXHMRsrceaZ2azpNYw9JwEZw27xkiBuGwrcTKEmwIS9j3JwXKEx42jVVdsc2JGKts X-Google-Smtp-Source: AGHT+IHHwM+aeJZu7hYwullFZuIhRKvUQLVjA4qx4gI5g3TrB/Ml8qXipNWpmor4aHcgSAgonf6z X-Received: by 2002:a05:6214:5d84:b0:6b7:a3da:1cdb with SMTP id 6a1803df08f44-6bb9837871amr154500866d6.21.1722949349133; Tue, 06 Aug 2024 06:02:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949349; cv=none; d=google.com; s=arc-20160816; b=in+5lQCTtvmzY1I+bZfCUp9mrnKmYrnzD1ch9BdRBGpZCQ3NNsA5E1w71jiD2hidb2 beiyv7atGadocuQ8g1xlucnuhxqQG8YHRkx4oreFY4844ewXKJbsGr1lvdxCCoynnbF/ zqMN4s/Jjy4uFp1dHPRXjNYmH3j4bUM0WeY4dBqq95+OutE0RU9ZCiQA+wVn/bnun0rd C6mNRmISCK5AtdyDp01CfmsBpzPcMRDmHrx6vhIBKp7x70tVKFxhzjTDZriNv+Gf97To prkXMk59RCnCbOhDoSWB5BT/fHze74outLZk10Rg81ltPcIM9O2B44eaUpnTjryLv0gE tpnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T2BNzJT5/rzAun9sis8NChUOI8pg5PZFtzu3546w0iw=; fh=OLWhW9PY8FnpOdOagGj3ODHuSts21bG5U9QIV67xEBE=; b=hIjXIUcHReMgHC4kR42JbaXIOpsXl0dxn1cin8o27ne2sycED77BK4vNeidZEj+kM1 0yQAjUqYIEK0KU1jQLax8kHghpEwooBbGE53wu24UsuWU9I0b23aB1pF9GS3L2Kx1c+z YVANTn7cMfsFfLLVkYQtJOWmGUNeAFlYU/gFfj7x8k5/eCFv1KculjiPIkN0uZMmTXPd oJJhS4kgbrlI4DQrb49kKAmdgsBJaKwfVG4m3zKsEqKYZajI+96TwOoCkE2aTYL9ckz4 2vHPslqAjCprblFyeuo/JeLEXbSxBDmBnlxCr7yQunCUtG3hpVhpXFXPVGsZ7oEGKbPX +Ixw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=luom6VsD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ec7575sm539465766b.205.2024.08.06.05.54.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Markus Armbruster , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 20/28] hw/block/fdc-isa: Assert that isa_fdc_get_drive_max_chs() found something Date: Tue, 6 Aug 2024 14:51:48 +0200 Message-ID: <20240806125157.91185-21-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell Coverity complains about an overflow in isa_fdc_get_drive_max_chs() that can happen if the loop over fd_formats never finds a match, because we initialize *maxc to 0 and then at the end of the function decrement it. This can't ever actually happen because fd_formats has at least one entry for each FloppyDriveType, so we must at least once find a match and update *maxc, *maxh and *maxs. Assert that we did find a match, which should keep Coverity happy and will also detect possible bugs in the data in fd_formats. Resolves: Coverity CID 1547663 Signed-off-by: Peter Maydell Reviewed-by: Markus Armbruster Reviewed-by: Kevin Wolf Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240731143617.3391947-6-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/fdc-isa.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c index e43dc532af..796835f57b 100644 --- a/hw/block/fdc-isa.c +++ b/hw/block/fdc-isa.c @@ -147,6 +147,8 @@ static void isa_fdc_get_drive_max_chs(FloppyDriveType type, uint8_t *maxc, *maxs = fdf->last_sect; } } + /* fd_formats must contain at least one entry per FloppyDriveType */ + assert(*maxc); (*maxc)--; } From patchwork Tue Aug 6 12:51:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817059 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1786808wrh; Tue, 6 Aug 2024 06:02:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUm+wcaQE2hfc+u+Yi4u5+HT2ghqvq17p2hJKqjR6qDKsNX1Dtj2m0DG9IckpFpjFTgKuaZgKTTpnRnttBMxxFs X-Google-Smtp-Source: AGHT+IGje1S3Xr4dEXivC3IN10pRAexexwdzUNACXtG7jDCC6R4yxBtDHsXAoFEypVmDIXFwFX20 X-Received: by 2002:a05:622a:294:b0:447:ea47:8fe7 with SMTP id d75a77b69052e-451892a4587mr160209271cf.39.1722949370787; Tue, 06 Aug 2024 06:02:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949370; cv=none; d=google.com; s=arc-20160816; b=r+1a1rbT2ZFjbJwnjHLEU8/GNHpoGXidojenB1RuTgLJWGYLBjF/smjlwZH1M7a2IP nbgH1LbhTri8ZYg+b5gBrIPMUe5HKZhtuTKZwPm1cyALQRNA6hGaXcJIZQ/DK/XTIinR /RQrgwUo1grEwWf8CrKapc1xohkyVWlssS4d9bEtAhNlG8Hi6+fGDnvCNib5cMhhymf3 aLfKSYpugerUTi2pLgPrEqjpOGzkKEYUVestKyEz9CQShHUEufJMeA2jN2NtCLEbeCtd D1cM8yyBPcBpYBb9C6kYJ0JpKRA92kM47UMWJySxyv6u5Cw+AJCSfVsXVCICRvj25ng+ m0NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gv+R0AOxTRNRr/YYta1DbILbzN2/ozjvln37VG+akqw=; fh=lqP0lF5ukwjxbxUF0Z/REflxpcqXoyuD5wuFRnwwNwk=; b=U3swWlUdV+YOv+0Y1AXbCE5NAIXoYvtTPKC4Y1+RaSGpupdOJaAgoIVQYxuAirj6T4 5VhDvx8z1218OJnpjpcDd/vkk1mDy2fRLbcF26LkIwOKV17M52NwNGxWVNt2ZrWZLQDZ nXCAGcyi64tKMz14TePX7xrmDP0VRAYzZkN7hCU9jAPwGWyFLEM45xgWq/0PMXUYtyh8 jcRtegEAUm/DpiVZ6YExEE7RY+D24cmoussdoBktNWTFwKgNNxFTnxZyisMTPJYBlQiH 3w9rYemBl0zEZBGuDuWagjuhoiwJzFYFjxUk7J3VfF6vlRu7KdFRN/B65iK7lMITnBFj fK8Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pMqQlNuh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bb88d1d9a3sm2558061a12.26.2024.08.06.05.54.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Kevin Wolf , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 21/28] hw/ide/pci: Remove dead code from bmdma_prepare_buf() Date: Tue, 6 Aug 2024 14:51:49 +0200 Message-ID: <20240806125157.91185-22-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell Coverity notes that the code at the end of the loop in bmdma_prepare_buf() is unreachable. This is because in commit 9fbf0fa81fca8f527 ("ide: remove hardcoded 2GiB transactional limit") we removed the only codepath in the loop which could "break" out of it, but didn't notice that this meant we should also remove the code at the end of the loop. Remove the dead code. Resolves: Coverity CID 1547772 Signed-off-by: Peter Maydell Reviewed-by: Kevin Wolf Reviewed-by: Philippe Mathieu-Daudé [PMD: Break and return once at EOF] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240805182419.22239-1-philmd@linaro.org> --- hw/ide/pci.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 4675d079a1..a008fe7316 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -237,7 +237,7 @@ static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit) /* end of table (with a fail safe of one page) */ if (bm->cur_prd_last || (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) { - return s->sg.size; + break; } pci_dma_read(pci_dev, bm->cur_addr, &prd, 8); bm->cur_addr += 8; @@ -266,10 +266,7 @@ static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit) s->io_buffer_size += l; } } - - qemu_sglist_destroy(&s->sg); - s->io_buffer_size = 0; - return -1; + return s->sg.size; } /* return 0 if buffer completed */ From patchwork Tue Aug 6 12:51:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817049 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1784446wrh; Tue, 6 Aug 2024 05:58:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU7i9rm3jNy8ej3MHMwiCfTONmLTNAwGR7LbyzaMnsmUDpdRIcQv+44niz1ITG1UKhvn3hB8JlfmLw/qh+qGb0t X-Google-Smtp-Source: AGHT+IEkVrwMXdWz+2mBFd5pVXko73N7WpFOSEZ9FfCrw9PfovG3c92OBEq0n0RdK8c+zR1dgaKB X-Received: by 2002:a05:6808:1489:b0:3d9:235b:185a with SMTP id 5614622812f47-3db55809957mr17540623b6e.18.1722949126502; Tue, 06 Aug 2024 05:58:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949126; cv=none; d=google.com; s=arc-20160816; b=acspae22g4jnS0yzlpeIytSf6j5COnOBaf72JXPpPyDS3tioDngef6KNmnwvVOEaCY 29saXruXTsHVhhoCM3kGSmZxTJUsDYK5neKmru5aJ8z+LM2Bx0O58OpQD1/EPa28hfme wtvuuRnuU/6cDmCscKyBa8Q/9kv20QgxgdgCc0RqjBeIBd4RcmW29o09zL4BVcZT4Khq LrJPkH6XFEXuv39xyismOPn4Arb7JQc0KfPmVOCHFHAE6YcvGDhfivZLnxY9h079wZHl 8KbLG1Q9GE8f+NyjnsxL092Fwco0EohQq3TXswBIOVA4t1Xo9WKwNOnFm4mOrG+Ms8l/ iShQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nMm3A0DabsjolGXhyPhZ1sZzpOJXfaTPvfWzaUzLVvw=; fh=CxGANQnxl0w34GvKO0j3aLxcHGRl2QR9Bm7QFKqLsvg=; b=edsJSSh9HJXNSZ/oy9szhgcbUih781jTQhZa5e3US/Pl0GYk802kcCaw6ehxt1hZzu kMYsm5K13VDTaxfGWFuqmdzcLD07r9ZYpIkx/zyb41wXiJSwzAJM6+hgmiVy3YE32kFg jjOyPDB6QmyyAP77uO+HlczGERewYW0hoJutb8R+NLpQCFsT0I3MqRvV1+Bab+Pwj9DR qfflJ0CGY4amUL+K2PcZlGuqER1MxTk+BWwQ1MmncOvNzgkHvwv+fOrqF7VaKdRk/IS8 jl7wvJwSZHMINt0yB4pBISQIDYaAqpHsjFV99ILh9Hpx4S/i8BW06DBB8DR486AknGBq BQNw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SmbFAtbB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bc3c7asm558455666b.14.2024.08.06.05.54.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PULL 22/28] hw/display/virtio-gpu: Improve "opengl is not available" error message Date: Tue, 6 Aug 2024 14:51:50 +0200 Message-ID: <20240806125157.91185-23-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell If the user tries to use the virtio-gpu-gl device but the display backend doesn't have OpenGL support enabled, we currently print a rather uninformative error message: $ qemu-system-aarch64 -M virt -device virtio-gpu-gl qemu-system-aarch64: -device virtio-gpu-gl: opengl is not available Since OpenGL is not enabled on display frontends by default, users are quite likely to run into this. Improve the error message to be more specific and to suggest to the user a path forward. Note that the case of "user tried to enable OpenGL but the display backend doesn't handle it" is caught elsewhere first, so we can assume that isn't the problem: $ qemu-system-aarch64 -M virt -device virtio-gpu-gl -display curses,gl=on qemu-system-aarch64: OpenGL is not supported by the display (Use of error_append_hint() requires us to add an ERRP_GUARD() to the function, as noted in include/qapi/error.h.) With this commit we now produce the hopefully more helpful error: $ ./build/x86/qemu-system-aarch64 -M virt -device virtio-gpu-gl qemu-system-aarch64: -device virtio-gpu-gl: The display backend does not have OpenGL support enabled It can be enabled with '-display BACKEND,gl=on' where BACKEND is the name of the display backend to use. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2443 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Marc-André Lureau Message-ID: <20240731154136.3494621-2-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/display/virtio-gpu-gl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/display/virtio-gpu-gl.c b/hw/display/virtio-gpu-gl.c index 952820a425..29d20b0132 100644 --- a/hw/display/virtio-gpu-gl.c +++ b/hw/display/virtio-gpu-gl.c @@ -106,6 +106,7 @@ static void virtio_gpu_gl_reset(VirtIODevice *vdev) static void virtio_gpu_gl_device_realize(DeviceState *qdev, Error **errp) { + ERRP_GUARD(); VirtIOGPU *g = VIRTIO_GPU(qdev); #if HOST_BIG_ENDIAN @@ -119,7 +120,12 @@ static void virtio_gpu_gl_device_realize(DeviceState *qdev, Error **errp) } if (!display_opengl) { - error_setg(errp, "opengl is not available"); + error_setg(errp, + "The display backend does not have OpenGL support enabled"); + error_append_hint(errp, + "It can be enabled with '-display BACKEND,gl=on' " + "where BACKEND is the name of the display backend " + "to use.\n"); return; } From patchwork Tue Aug 6 12:51:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817050 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1785427wrh; Tue, 6 Aug 2024 06:00:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVB8HvdGJVpA9uMEH5PDy08d6tX8D46JDLbEHydFsRXn9D7WMVx71SdZZWJPtxp5Emy4dklUiqVm2sDMSGBzb9/ X-Google-Smtp-Source: AGHT+IEPUbpUMBlrjHG/gfd5/xHUTvnmPDupqbEE0uzPAA6ZjqJ/wUXy65keK2djDmjxNp05phid X-Received: by 2002:a05:6214:5bc3:b0:6b2:a333:2a9f with SMTP id 6a1803df08f44-6bb987ae578mr260410716d6.23.1722949253770; Tue, 06 Aug 2024 06:00:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949253; cv=none; d=google.com; s=arc-20160816; b=x3sOXO1rs4PDE0FX+33G7pRYDaO2kcMcUOYCTu+GiarSHG5J3vUIBL1oLAMazqKnZG Il39EIIAg9SCsXZuFbxcGOxTYKxMZcY4UeRK9np/XBE5+lW/Nf9qUkQ64YFNs3jjsYpq vukMNIUKaYFgMCz+IM9p0aAk6Omh6cbrSi08onvt+wDIAWvdPKK//BY3eSxwPM4HHbEV 2coYiFmAMGrFyRAXXP4wAhITfWH4v9qQbbBXAT/7RofKQQaKcAzmm1f+lflTMOaV+xxa 45lhdTxXnAKRJI5dH/hwHMOBt+v7FvYNysVocBLwmw5ZVj0dk2ywV52aHYDIKod09HyM Rngg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0GHmHGgb11iYqcqPSgHHl5+4znvZdtn/oYi94we9BmQ=; fh=CxGANQnxl0w34GvKO0j3aLxcHGRl2QR9Bm7QFKqLsvg=; b=st2Cglze+ElbFQJiSdhlEhkFTUtnOm8R3UdYQ97U+Zkw4+BLDFWcTRQM5egb/sqzbO XHo9m1in9yROjoCyKcM43x758vBkIvnXi85uw4PMZo27ZyvZJj9bBOwZT+lLRMxM2w9f k/+PeFeRAw5qC+DPYfEvbfHMP1I94DENLRjSlf/KWfPwDj8K8g/kj4uhyGan0k3S22oh 99G4ks3qtbmTUtdLUqYpl5wLUBOy9/MM5LcpwI4h8FULPVJvfJXlR2bkv0SbXjkf21y8 xq6o4nxXYqbWC5HbrRGgEUasdmSshLBFA9dZZm33eEx2Qe3coZO3oZ5pJdCEIt8vxRuq p2tA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F8p8PwSP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9bc9d7dsm547291966b.9.2024.08.06.05.54.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PULL 23/28] system/vl.c: Expand OpenGL related errors Date: Tue, 6 Aug 2024 14:51:51 +0200 Message-ID: <20240806125157.91185-24-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell Expand the OpenGL related error messages we produce for various "OpenGL not present/not supported" cases, to hopefully guide the user towards how to fix things. Now if the user tries to enable GL on a backend that doesn't support it the error message is a bit more precise: $ qemu-system-aarch64 -M virt -device virtio-gpu-gl -display curses,gl=on qemu-system-aarch64: OpenGL is not supported by display backend 'curses' Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Marc-André Lureau Message-ID: <20240731154136.3494621-3-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- system/vl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/system/vl.c b/system/vl.c index 9e8f16f155..213ee6a6a9 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1973,9 +1973,10 @@ static void qemu_create_early_backends(void) if (dpy.has_gl && dpy.gl != DISPLAYGL_MODE_OFF && display_opengl == 0) { #if defined(CONFIG_OPENGL) - error_report("OpenGL is not supported by the display"); + error_report("OpenGL is not supported by display backend '%s'", + DisplayType_str(dpy.type)); #else - error_report("OpenGL support is disabled"); + error_report("OpenGL support was disabled when QEMU was compiled"); #endif exit(1); } From patchwork Tue Aug 6 12:51:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817043 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1783408wrh; Tue, 6 Aug 2024 05:55:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVN4rcCAYR+MfUdEhdKGSwVuFNFqObmEAyqq48mjkxFarw4uiTbQiAOhC7imw+AnXZzBzQrzgHlQO+h6rANSiSt X-Google-Smtp-Source: AGHT+IE1pevrLYRssZ05+PQ3UowlCjHhVOaRafJZxhOSowo+HE0jYnLznYs3gJ3r2O0vTV7UXQJx X-Received: by 2002:a05:6214:4a02:b0:6b7:9fe3:b2be with SMTP id 6a1803df08f44-6bb984351a0mr211750316d6.53.1722948937456; Tue, 06 Aug 2024 05:55:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722948937; cv=none; d=google.com; s=arc-20160816; b=W00UIT039vHH5+oj0llX+lJyzolFkbCw7cmJY4AH7QlypjAHI5MMznkEgN0wZf/MFX eNdI5FxjItUalTJiAB0bPlIG9OQd02N5BENmjj52dCbvF4DnjodGpPC2Y2u5u1HaG4BD nFeVy7mGWHQzNdxwpFDr7fG3Xv9DC0f6YkfxdFJhnlARRG6P9jCuxBc7a30WKcSAMhzF htwuPFQSRlHp3C37QbAeKzavRXVLQg8+hkcZGwWlH+61YHQS2bwoWXTtaW9zeTrFkA1E vUO5EuJHZxDWe52sVtJ2kwR86JEO9c4DQVL4R5+i6fipPSgSrgIuOrJH11QsQEk98wsK 7xqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lTDAhFeBz9GijM5OI6/yGi13UeAA7K13kn7Zuxhnv+U=; fh=CxGANQnxl0w34GvKO0j3aLxcHGRl2QR9Bm7QFKqLsvg=; b=NJDBExUpaTpkOmWxpQNh9W3i5wa75I2HlfJug1whrrXyXL913g1JmfrMy+eYrE98pR BR21eclWw92YRgrdEqRsv7BxFrUaK4X3PHHsn0A1JGHWpZWTO9XlkVdOcTlBX1TR9hIx g3IjfhLVdqnVkiEp9Uj2PhAuJ26XHWXEprt+G4SmHHfdigHbfygjZoIVBV9rHuytIBw0 zmOafp57odlGdQiBv07ihLvvI+X/YD9hynBL+xoaFSDvUykQs+hux9LO+1wHf9KTH1NK iNrixyTrGh8kYGX0RZ8c642eUewHTWEDUvw2fXvmwJfxtIG3ScsATX68wYe+UpLcLt7k I0oQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NPNVgoVs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7de2d923ccsm423738866b.79.2024.08.06.05.54.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PULL 24/28] ui/console: Note in '-display help' that some backends support suboptions Date: Tue, 6 Aug 2024 14:51:52 +0200 Message-ID: <20240806125157.91185-25-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell Currently '-display help' only prints the available backends. Some of those backends support suboptions (e.g. '-display gtk,gl=on'). Mention that in the help output, and point the user to where they might be able to find more information about the suboptions. The new output looks like this: $ qemu-system-aarch64 -display help Available display backend types: none gtk sdl egl-headless curses spice-app dbus Some display backends support suboptions, which can be set with -display backend,option=value,option=value... For a short list of the suboptions for each display, see the top-level -help output; more detail is in the documentation. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Marc-André Lureau Message-ID: <20240731154136.3494621-4-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- ui/console.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/ui/console.c b/ui/console.c index e8f0083af7..105a0e2c70 100644 --- a/ui/console.c +++ b/ui/console.c @@ -1632,4 +1632,9 @@ void qemu_display_help(void) printf("%s\n", DisplayType_str(dpys[idx]->type)); } } + printf("\n" + "Some display backends support suboptions, which can be set with\n" + " -display backend,option=value,option=value...\n" + "For a short list of the suboptions for each display, see the " + "top-level -help output; more detail is in the documentation.\n"); } From patchwork Tue Aug 6 12:51:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817046 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1783789wrh; Tue, 6 Aug 2024 05:56:51 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVTNDEhlwCuHX7FgWGiatXo+iQcIkFTmHvk30e+C2aqYwdtxh9QUD61cL7VGiJLGpHdoAdqnlzNUdU1zffAhQBH X-Google-Smtp-Source: AGHT+IHdIzQDaoViXKZi6wcDKrZ8soOcsYBQB6lCVupo+P4xKVPex2g6Lm4W+gz7SjE4Y8qFYJio X-Received: by 2002:a05:622a:5c8:b0:44f:dcb3:782b with SMTP id d75a77b69052e-45189442958mr258343301cf.29.1722949011187; Tue, 06 Aug 2024 05:56:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949011; cv=none; d=google.com; s=arc-20160816; b=NtDSUEkZFTf39Q4BwRTN1iWwaFrJTi2MqxynGUFKBRa/dwDsJwehbO5FODfv0ZfEfl RsYkp347hbLj06Cj7ru28YC8JMEIwiHLg5xRewqlhpYXIBe+MzvIO4DN/jCKzFt/C2sq 8XqMxNpVyNIrv5ZlX5uPx5vxVDCi+PuA/FDy5mK8eR0hxhfXw5qWEXGzzMW8DoZc/T/9 bKfXlophh+KTQbbGYYAsQnGG+I+8LjfSDWebC/pCIxpyhTg6FtallboGsePCKbQ1jau6 jPM1+Sm87IuZao0kvlO7FaSKH8rzkYOGPmvoegKGz4RHiKQzQmd8LUMNW/VknQz1tu4p M8ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ypdbeuI3/3zkqxrrQlfqtvt5UnR+ONpIVnv+X7Sc7F4=; fh=zHtHAuA8LADr4MRt4nXJtB51OHRL6WdmArQw1AAPiTQ=; b=UJwdZqrpFUsxcB2CjFISZzM263+/bRlrSBRk7qDPpMbuNyjFX+yx6a97IBtj6t95Vn A52ZRdprST4XSoZho1gPgkjm9UqHXBAjm+KVxfeeTcZK9yH2p1YB4af495xLoor54S20 9FsDq2g6rRY47Sem2lkAZwgX05OZ+ApnSujcVE50yFTl5gx2g5tzIooBWNyqGbdzpPBH 2RevHUVTMg1fXy820P/oS0sOYnvP9HTJ4zqBdLGlZNrF3Q9ZzkC9655TtPl+5CJ4RfQU 0WwHvwhwCVnZeN7VD6+hArDRbEkDeBuYNmjlf+chhhqEB8lMtdQG05qeWDHOmETRmCjb HQqQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UOwVR5EU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9c0c0d5sm545644666b.48.2024.08.06.05.54.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PULL 25/28] hw/pci-host/gt64120: Set PCI base address register write mask Date: Tue, 6 Aug 2024 14:51:53 +0200 Message-ID: <20240806125157.91185-26-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When booting Linux we see: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) This is due to missing base address register write mask. Add it to get: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000fff] Since this device is only used by MIPS machines which aren't versioned, we don't need to update migration compat machinery. Mention the datasheet referenced. Remove the "Malta assumptions ahead" comment since the reset values from the datasheet are used. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan Message-Id: <20240802213122.86852-2-philmd@linaro.org> --- hw/pci-host/gt64120.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index e02efc9e2e..573d2619ee 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1,6 +1,8 @@ /* * QEMU GT64120 PCI host * + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) + * * Copyright (c) 2006,2007 Aurelien Jarno * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -1213,17 +1215,27 @@ static void gt64120_realize(DeviceState *dev, Error **errp) static void gt64120_pci_realize(PCIDevice *d, Error **errp) { - /* FIXME: Malta specific hw assumptions ahead */ + /* Values from chapter 17.16 "PCI Configuration" */ + pci_set_word(d->config + PCI_COMMAND, 0); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */ + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */ + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); + pci_set_byte(d->config + 0x3d, 0x01); } From patchwork Tue Aug 6 12:51:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817058 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1786661wrh; Tue, 6 Aug 2024 06:02:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVbIaEbZKwFQo0vE4DZ8LX2ZcSmfqH0a+KMbpGN+9Kzex2AW0xHQ8TIrUC2M/CYyYcU5++/H+y0Ytl0bSNec3xR X-Google-Smtp-Source: AGHT+IF3/fouUtA+t+Nm+7rwcLr1/jsgghzmf5FYJ6IPpyWi6VKSmlE9StOJ76LTwsuAbVRytoHS X-Received: by 2002:a05:620a:2955:b0:79f:e9a:5ae5 with SMTP id af79cd13be357-7a34efc749dmr1749856785a.60.1722949358721; Tue, 06 Aug 2024 06:02:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949358; cv=none; d=google.com; s=arc-20160816; b=x4DwTGWf+16EbTnhD9fkHYi3QCQ2KejXYbsrB3y36jD9ZwnheBayLPR6Ei61r29lyj +fSV00NT+kHRX4D5FTo5whzYyZ+PNZMVaYmIdY0VLOMbitsRtV3ClH9nEjmiAMkR0ykJ kq0GIRQyaWTpGKGOuLHm8E4Cw5Nr2H+JQuAIXLIn9u1MSu37IJpfXPR4WD1/CvKjwy0d qzKaZ2IFPaOalvKRhmRDxBlhMG3zn3AnqysWSFMa8YzJtDfSMAooklGkiNAvEN/aVkDY KHsnHIvMgoQV1yn3WEKx7p6Vbcjke1rkEZStarP8ZNCvJNl5DhbrOaK2aRemUPZbMYLE hyQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qK43iUJyWAfHzKeE0GH3CsavBGdCBQ3nQYJeK6ymPbo=; fh=xOM3PbYJjarox7kiUOhdn+2peZtZZKnou+DGo8TRhT8=; b=mqtwBdWG7MJ6wHhnc9Kh43vVbobBjyuAf66BGLVk2CY4SCZAShi2mtct2kNUkfjuxe 4cC34iAo5kPFmxAYrRoKC/ZQi8EAY24RZrqHMypPCSz4IZGsue5GNiqIGYroW63xsC7g OWhzJN+omcN71hSahV1IdFxMdD2+j6s3e/ykXOxxQOC1D9Wp3/VH+k211dovv+sK4bDn IgCEDdg6s+6tz7UkDF6DkLFFtrk5O/96J1D3KiLbFkNnuyS8ut0nNZUjKZdZe8RS5d77 NCFNXRoHz9fmpHfNzrDxdxr52clkggOijKCHuvoawPtXcgBDxDZJciKp/dIb09QPFWoG HB3Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sELFRUdu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e80e04sm553901866b.175.2024.08.06.05.54.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" , BALATON Zoltan Subject: [PULL 26/28] hw/pci-host/gt64120: Reset config registers during RESET phase Date: Tue, 6 Aug 2024 14:51:54 +0200 Message-ID: <20240806125157.91185-27-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reset config values in the device RESET phase, not only once when the device is realized, because otherwise the device can use unknown values at reset. Since we are adding a new reset method, use the preferred Resettable API (for a simple leaf device reset, a DeviceClass::reset method and a ResettableClass::reset_hold method are essentially identical). Reported-by: Michael S. Tsirkin Reviewed-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240802213122.86852-3-philmd@linaro.org> --- hw/pci-host/gt64120.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 573d2619ee..33607dfbec 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1217,17 +1217,24 @@ static void gt64120_pci_realize(PCIDevice *d, Error **errp) { /* Values from chapter 17.16 "PCI Configuration" */ - pci_set_word(d->config + PCI_COMMAND, 0); - pci_set_word(d->config + PCI_STATUS, - PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); - pci_config_set_prog_interface(d->config, 0); - pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */ pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */ +} + +static void gt64120_pci_reset_hold(Object *obj, ResetType type) +{ + PCIDevice *d = PCI_DEVICE(obj); + + /* Values from chapter 17.16 "PCI Configuration" */ + + pci_set_word(d->config + PCI_COMMAND, 0); + pci_set_word(d->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); + pci_config_set_prog_interface(d->config, 0); pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); @@ -1243,7 +1250,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + rc->phases.hold = gt64120_pci_reset_hold; k->realize = gt64120_pci_realize; k->vendor_id = PCI_VENDOR_ID_MARVELL; k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; From patchwork Tue Aug 6 12:51:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817048 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1784014wrh; Tue, 6 Aug 2024 05:57:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW7pj2ztuwbagWdo56t5fQT0pPDJyET2KeYHXwjsVNwP+Ef2V/Az88oEH2QS45XBdQ+7cMzSSLnYn4Zd2f/Dr/k X-Google-Smtp-Source: AGHT+IEcGxVOJ1OAwxS56OX+gTlpyzRPLen9AYVnrpPgdoRz0I72Zzot8ivSwQeaKlvEdNyqShRc X-Received: by 2002:a05:6808:3094:b0:3d9:3538:8cff with SMTP id 5614622812f47-3db557fcffcmr18806383b6e.8.1722949056074; Tue, 06 Aug 2024 05:57:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949056; cv=none; d=google.com; s=arc-20160816; b=BHTT6gSEyEdAZyTpTRap/pAnnFp07gLZ5z+1J3u6Cx0NMlzlcqdAz5fWNhYUuJQYub W0I/16W/EPY8MvkbQou/RaKGUiLRoZi1rosma3Gyo0HzDFX9SctqzmQJJctWKTrLZQxp YBOfbedSePXfsyFrYhxqwzPbDDitaN6Wti16zQyBoHuwO8lOD/H8OzWoUji148vTZto6 GxpSnxHNVwUlfHS1cmEkDm6htdKbftc5a8c+/vNfvNAqjhNIl60jb6iIYt/3a/wMKizG cyHppK6Fwgt/DGrn1hsWA31vthq2PjOHjoEe3oX9v9ee4vzH5Ula+b+ttn/hvGal4a+1 Nssg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mHh1GCcnST+B2sXjSnUGRo9NlbeZggGy0/xN/r51vXs=; fh=aOsZGQ/p3mC68by/bkWof0As1imtzrtf122RdbJmidA=; b=QSbH+kWVLDDdaXtCi+1SSnBjZetf60Oy9dqrnEKO1gymhAHNgb+BDztb7LORvmvWfn JsOiSkMVt0Ng12f4jbePBb+WwYYJC7tCBpa0DcDcD1fKlxd5GiKc+S/qEm+o+WWlKuug 4uHWY4xewGD6f00mAHZF7U3zJDeOn+P9evy44l1fBHa568BYn7BSz5FZyFizGJzP+Eon lHkEdRz3ysg7g8YCJa2OP0RTo9a9jn6KjtevHHvLpFsgnQjCrhdnL87aqozaJY5HxZyi jylx+GZRB2i2Sgsw+Y51l+5tqBjdTfS9IRYiXkHcG3SLfJ+2RgzNMkwYmEumPlxtpL7R uZyQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fy3VdGmR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e80e77sm541169966b.169.2024.08.06.05.54.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: George Matsumura , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 27/28] docs/specs/pci-ids: Add missing devices Date: Tue, 6 Aug 2024 14:51:55 +0200 Message-ID: <20240806125157.91185-28-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: George Matsumura Add the missing devices 1b36:000c (PCIe root port) and 1b36:000e (PCIe-to-PCI bridge). Signed-off-by: George Matsumura Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240805031012.16547-2-gorg@gorgnet.net> Signed-off-by: Philippe Mathieu-Daudé --- docs/specs/pci-ids.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst index c0a3dec2e7..0de13de1e4 100644 --- a/docs/specs/pci-ids.rst +++ b/docs/specs/pci-ids.rst @@ -82,8 +82,12 @@ PCI devices (other than virtio): PCI-PCI bridge (multiseat) 1b36:000b PCIe Expander Bridge (-device pxb-pcie) +1b36:000c + PCIe Root Port (``-device pcie-root-port``) 1b36:000d PCI xhci usb host adapter +1b36:000e + PCIe-to-PCI bridge (``-device pcie-pci-bridge``) 1b36:000f mdpy (mdev sample device), ``linux/samples/vfio-mdev/mdpy.c`` 1b36:0010 From patchwork Tue Aug 6 12:51:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 817053 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp1785632wrh; Tue, 6 Aug 2024 06:01:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWaEsMVUu/Lo5Yfaa26V7zJk8Km97BzEYHMbCh8HMu+viMyzKADL/TB1fJSMWXWOFQCmF1tGP5W1GLe1Cke+NAu X-Google-Smtp-Source: AGHT+IFQqs3FLndHdoynpDs4kVZFvghdio7bROIiZhf6zGzS275NRENsdTOTC/LxJN0EV0Yi6ryI X-Received: by 2002:a05:620a:3713:b0:79e:fd21:c352 with SMTP id af79cd13be357-7a34c068e48mr2595620185a.19.1722949274605; Tue, 06 Aug 2024 06:01:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722949274; cv=none; d=google.com; s=arc-20160816; b=GIX9V0nuL7SYlZ6h1B8fra5qeNcyIP7BFHPy7nlu0dQHjQWUdd8pkSnq2yDLjZkBLl RhjBrXNYSZnLkw/zjZZu64R+Ie8i96nutMjhLS9Z7dTsaD3QMVhf8bfbpY0NnU6mynC2 s2/TIRrhPznCC13WAY/B5T27m9aZPWO6mIleuQrIIbx52iTYovVrVYXJCUMAa8dy/eoM o++j36i1DtwF+w0FSvrd0/kjvuqKMZaeCCJkwAAuoCoMy4Z0a/+UhbZCoZxbYq/XwXsj oGBQmpZ7P1ZVT3um7mQECwSFPaTB7hlwP/pIuj/RPUOXfgJY5XJDuA+yPrD2ooASoXxY j7gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=77mKDDwsQ4N9EU0OpMBcpTovtWIwsiedBtivnY0Iukw=; fh=aOsZGQ/p3mC68by/bkWof0As1imtzrtf122RdbJmidA=; b=GhXHrlwlYkI8NIDFqdnudcfxJLQ6dh8QiDVPYEK79X8sS+VJJ7/a7YaJJO9FyBRmwk Pkp6dElaqeoaY8NfleTfOrC2hq5HyEpf2fZho164jix1SIXmgpEKoPubn3gOHEgoJw/D WZripeNOV/Dhawsth1bSdUg8ct5+5MxzewuhFmnEsMFZnQByIDZYQgF5FXn6vDwjHucV iWj8gZPeES+PQqArVEzleS+yeSlv2+idjkSPW02aQ4un1E6UobVZ+is0Vq2oj56ue03f rFgThkAoVuSfnx7DYAepcgbzoM4sYGHuZtO4ef8a05GyaciUQHwZyahXsCxX/UNQA1o4 jFUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qu2lRgvt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.30.206]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9e7fe2fsm548850866b.178.2024.08.06.05.54.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 06 Aug 2024 05:54:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: George Matsumura , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 28/28] docs/specs/pci-ids: Fix markup Date: Tue, 6 Aug 2024 14:51:56 +0200 Message-ID: <20240806125157.91185-29-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240806125157.91185-1-philmd@linaro.org> References: <20240806125157.91185-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: George Matsumura This fixes the markup of the PCI and PCIe Expander Bridge entries to be consistent with the rest of the file. Signed-off-by: George Matsumura Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240805031012.16547-4-gorg@gorgnet.net> Signed-off-by: Philippe Mathieu-Daudé --- docs/specs/pci-ids.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst index 0de13de1e4..328ab31fe8 100644 --- a/docs/specs/pci-ids.rst +++ b/docs/specs/pci-ids.rst @@ -77,11 +77,11 @@ PCI devices (other than virtio): 1b36:0008 PCIe host bridge 1b36:0009 - PCI Expander Bridge (-device pxb) + PCI Expander Bridge (``-device pxb``) 1b36:000a PCI-PCI bridge (multiseat) 1b36:000b - PCIe Expander Bridge (-device pxb-pcie) + PCIe Expander Bridge (``-device pxb-pcie``) 1b36:000c PCIe Root Port (``-device pcie-root-port``) 1b36:000d