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Fri, 9 Aug 2024 11:55:00 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20240809115500epsmtrp2c80367f8d87080c5a19cf92e7fb19545~qDVz2GAPg2146221462epsmtrp2X; Fri, 9 Aug 2024 11:55:00 +0000 (GMT) X-AuditID: b6c32a39-8f9ff70000002606-a7-66b6039443c7 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id 7F.43.19367.49306B66; Fri, 9 Aug 2024 20:55:00 +0900 (KST) Received: from [127.0.1.1] (unknown [10.113.111.204]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240809115500epsmtip191c8ab68ce01f1f077dc7530ec32c4d0~qDVzjDugK0371703717epsmtip1h; Fri, 9 Aug 2024 11:55:00 +0000 (GMT) From: Kwanghoon Son Date: Fri, 09 Aug 2024 20:54:12 +0900 Subject: [PATCH v3 1/3] dt-bindings: clock: exynosautov9: add dpum clock Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240809-clk_dpum-v3-1-359decc30fe2@samsung.com> In-Reply-To: <20240809-clk_dpum-v3-0-359decc30fe2@samsung.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Chanho Park , Tomasz Figa , Krzysztof Kozlowski Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kwanghoon Son X-Mailer: b4 0.14.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCJsWRmVeSWpSXmKPExsWy7bCmnu4U5m1pBue/alk8mLeNzeLyfm2L NXvPMVlc//Kc1WL+kXOsFr1rrjJZvJx1j83i/PkN7BabHl9jtfjYc4/V4vKuOWwWM87vY7K4 eMrV4v+eHewWh9+0s1r8u7aRxWLVrj+MDoIe72+0snvsnHWX3WPTqk42j81L6j36tqxi9Pi8 SS6ALSrbJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwfo dCWFssScUqBQQGJxsZK+nU1RfmlJqkJGfnGJrVJqQUpOgWmBXnFibnFpXrpeXmqJlaGBgZEp UGFCdsa1+xeZC44LV/zo7WZuYDzE38XIySEhYCJxedt6RhBbSGAHo8T//yVdjFxA9idGib7J jaxwTsfaZSwwHc29H9kgEjsZJRrXbYeqesUocfDST7BZbALqEkva1rKD2CwCqhLzru4D6xYW 8JC43feRGcTmFRCUODnzCVicWUBeYvvbOVBxW4mfvR/B4pwCdhLHjp0CWyAisJ9Z4tTD52Cr mQVOMEr8ur2AEeImYYnPu9eAJSQETnBILJj6kB0i4SKx+cFRFpiiV8e3QMWlJD6/28sGYWdL HP0IY5dIXJ+1iBXCNpbYv3QyUxcjB9A2TYn1u/QhLuWTePe1hxUkLCHAK9HRJgRhykvc6iyH aBSVOPMUFEIgYQ+JSf91IeEzkVGi/VAj+wRG+VlI3p+F5P1ZCLsWMDKvYhRLLSjOTU8tNiww hcdqcn7uJkZw8tWy3ME4/e0HvUOMTByMhxglOJiVRHibwzelCfGmJFZWpRblxxeV5qQWH2I0 BUbCRGYp0eR8YPrPK4k3NLE0MDEzMjaxMDQzVBLnPXOlLFVIID2xJDU7NbUgtQimj4mDU6qB SSFtTVCq9JPywqN6k3v42npn7f/+6e5Bjja1FM3Unfyno+YZR2vVlbw8Jm5/tHXG1zmqTyc6 mNz3Weaw7gPrSevEJvEN/58uP/9sDruZNa+VANtCr7bc1CJebVvxGeyVXo/1j8Yf/PIqc3LW 9tBCsTr+Jx9L53p91pwZM9c+b/MW8XMGGQ0VRgt4ZX7P9u3ap6sb4e+1qvnH4nvSfbx72WXb DkTJS69Ntzsvffa7suw29frG46/DGOYfPsW4ZPOZZbsK/3/bsOrm/DPnPO13/chQkHadI53w 9EKcoFK2rWt/1RIze/PO07NeMcasDFxiaLBSfZru9yD1+Jar7M01ZhnSHrptmp8jmS/wsagq sRRnJBpqMRcVJwIAjN9AcUcEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42LZdlhJTncK87Y0g5VL+SwezNvGZnF5v7bF mr3nmCyuf3nOajH/yDlWi941V5ksXs66x2Zx/vwGdotNj6+xWnzsucdqcXnXHDaLGef3MVlc POVq8X/PDnaLw2/aWS3+XdvIYrFq1x9GB0GP9zda2T12zrrL7rFpVSebx+Yl9R59W1Yxenze JBfAFsVlk5Kak1mWWqRvl8CVce3+ReaC48IVP3q7mRsYD/F3MXJySAiYSDT3fmTrYuTiEBLY zigxa81DdoiEqETH5UbGLkYOIFtY4vDhYoiaF4wS51ongtWwCahLLGlbC2azCKhKzLu6jwXE FhbwkLjd95EZxOYVEJQ4OfMJC8gcZgFNifW79EHCzALyEtvfzoEqsZX42fsRrEQIyD7/hA0k zClgJ3Hs2ClWkLUiAgeZJX6/+cYO4jALnGSUmLhgO9SdwhKfd69hm8AoOAvJulkI62YhWbeA kXkVo2hqQXFuem5ygaFecWJucWleul5yfu4mRnCMaQXtYFy2/q/eIUYmDsZDjBIczEoivM3h m9KEeFMSK6tSi/Lji0pzUosPMUpzsCiJ8yrndKYICaQnlqRmp6YWpBbBZJk4OKUamFbJ1+2r rSp18HU3+5zR2stVqqB2/MkPy7VCvFGXnAT5V099u6V18Q6NjVkX1VTeJdyc0l/sPftg2KPP cz9oC34TfCy1TmJC1e+TrjPkLJpfaeyczt+fsut+hNFK45/7c65cvtsVz8bbNeOl6hGu8gTR a6e3MzvYxlyZurxkueGjvHU+2wwezGfy1oh4yBO8ivsz5+aJc1u/ny+S5nm+ROAD02rWpp28 XfzCnrsmPbkdo83w6cX+IHO2J5k5/gq3rq7MC1ljc3Cbg+y3W3ll57iuB6Xs94/Xm7Ez8dNP 4z05rj/+71s371jfUpmtr1y7u+a+CmCr91HfM1Hw48m0GeJR7qvLd78R3rb+7yJF611KLMUZ iYZazEXFiQBvmRBBIAMAAA== X-CMS-MailID: 20240809115500epcas1p32a698c821765e1a0d5fa998e6e08f1cd X-Msg-Generator: CA CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240809115500epcas1p32a698c821765e1a0d5fa998e6e08f1cd References: <20240809-clk_dpum-v3-0-359decc30fe2@samsung.com> Add dpum clock definitions and compatibles. Also used clock name 'bus' instead of full clock name dout_clkcmu_dpum_bus like other board cmu schema (GS101). Signed-off-by: Kwanghoon Son --- .../bindings/clock/samsung,exynosautov9-clock.yaml | 19 +++++++++++++++++++ include/dt-bindings/clock/samsung,exynosautov9.h | 11 +++++++++++ 2 files changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml index 55c4f94a14d1..32f39e543b36 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -35,6 +35,7 @@ properties: - samsung,exynosautov9-cmu-top - samsung,exynosautov9-cmu-busmc - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-dpum - samsung,exynosautov9-cmu-fsys0 - samsung,exynosautov9-cmu-fsys1 - samsung,exynosautov9-cmu-fsys2 @@ -109,6 +110,24 @@ allOf: - const: oscclk - const: dout_clkcmu_core_bus + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-dpum + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: DPU Main bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index 3065375c2d8b..ce8fb8f7d718 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -179,6 +179,17 @@ #define CLK_GOUT_CORE_CCI_PCLK 4 #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 +/* CMU_DPUM */ +#define CLK_MOUT_DPUM_BUS_USER 1 +#define CLK_DOUT_DPUM_BUSP 2 +#define CLK_GOUT_DPUM_ACLK_DECON 3 +#define CLK_GOUT_DPUM_ACLK_DMA 4 +#define CLK_GOUT_DPUM_ACLK_DPP 5 +#define CLK_GOUT_DPUM_SYSMMU_D0_CLK 6 +#define CLK_GOUT_DPUM_SYSMMU_D1_CLK 7 +#define CLK_GOUT_DPUM_SYSMMU_D2_CLK 8 +#define CLK_GOUT_DPUM_SYSMMU_D3_CLK 9 + /* CMU_FSYS0 */ #define CLK_MOUT_FSYS0_BUS_USER 1 #define CLK_MOUT_FSYS0_PCIE_USER 2 From patchwork Fri Aug 9 11:54:13 2024 Content-Type: text/plain; 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Fri, 9 Aug 2024 11:55:00 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20240809115500epsmtrp286e6eab320d9cc97c0418703f68f4318~qDV0AU9fs2146221462epsmtrp2c; Fri, 9 Aug 2024 11:55:00 +0000 (GMT) X-AuditID: b6c32a36-ef9ff70000002597-19-66b603949296 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 03.17.07567.49306B66; Fri, 9 Aug 2024 20:55:00 +0900 (KST) Received: from [127.0.1.1] (unknown [10.113.111.204]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240809115500epsmtip1722a39cd18b3a29652fac75e15101e29~qDVzswwKm0525105251epsmtip1J; Fri, 9 Aug 2024 11:55:00 +0000 (GMT) From: Kwanghoon Son Date: Fri, 09 Aug 2024 20:54:13 +0900 Subject: [PATCH v3 2/3] arm64: dts: exynosautov9: add dpum clock DT nodes Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240809-clk_dpum-v3-2-359decc30fe2@samsung.com> In-Reply-To: <20240809-clk_dpum-v3-0-359decc30fe2@samsung.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Chanho Park , Tomasz Figa , Krzysztof Kozlowski Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kwanghoon Son X-Mailer: b4 0.14.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGJsWRmVeSWpSXmKPExsWy7bCmvu4U5m1pBg0HzSwezNvGZnF5v7bF mr3nmCyuf3nOajH/yDlWi941V5ksXs66x2Zx/vwGdotNj6+xWnzsucdqcXnXHDaLGef3MVlc POVq8X/PDnaLw2/aWS3+XdvIYrFq1x9GB0GP9zda2T12zrrL7rFpVSebx+Yl9R59W1Yxenze JBfAFpVtk5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIToOuWmQN0 upJCWWJOKVAoILG4WEnfzqYov7QkVSEjv7jEVim1ICWnwLRArzgxt7g0L10vL7XEytDAwMgU qDAhO2NGzzfGgv3sFXtn7mVrYJzB1sXIySEhYCLx7+5lIJuLQ0hgB6PE7Mb/jBDOJ0aJKW+X MUE43xglWs+dYoJpeX6kgxkisZdR4sfu2VAtrxgl+h7eYQGpYhNQl1jStpYdxGYRUJVYsnkV mC0s4CmxfP4BRhCbV0BQ4uTMJ2D1zALyEtvfzmGGiNtKHLy5FszmFLCTOHbsFCvIAhGB/cwS px4+B7uWWeAEo8Sv2wsYIW4Slvi8ew1YQkLgAofEyem32CESLhJr1i+EK3p1fAtUXEri87u9 0DDIljj6EcYukbg+axErhG0ssX/pZKCnOYC2aUqs36UPcSmfxLuvPawgYQkBXomONiEIU17i Vmc5RKOoxJmnH6EGekgsPfaNFRJAExkluiYsZ5zAKD8Lyf+zkPw/C2HZAkbmVYxiqQXFuemp xYYFRvB4Tc7P3cQITsBaZjsYJ739oHeIkYmD8RCjBAezkghvc/imNCHelMTKqtSi/Pii0pzU 4kOMpsBYmMgsJZqcD8wBeSXxhiaWBiZmRsYmFoZmhkrivGeulKUKCaQnlqRmp6YWpBbB9DFx cEo1ME1vTe38+IexdE1L3IPGeauXzLwid4Hdb5qGMJeKyfyctzPvmLza9rBWtvdg5Vb9OZOv mt+M6FWUe2Jz6U5Tr+PRirIby95fZKt6/WWvsu+0LYzH9WZYf65J3mDn72thF/1NQqzxVYja BqZ5T1wmKW2cGe8n6L0zpDz51U7DkONsctxhf5zbF6SqNk9ft1lwWnGaT2Z/p8Trno5zNjVb eaY5pcy99Ld52p253ZdnCG/afjt2ib3MJbnwWWvXG4QcP7J2usWpU8kH1Cb/kj2o0H9Z94Re uc62iscNojwLmmon1monb1+/tUZs36y1ByXD4/ycX9rXCn5ocXwkt2vx/elKMp8TPh31eeKc +lywjluJpTgj0VCLuag4EQBvynJUSQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsWy7bCSnO4U5m1pBsePiVs8mLeNzeLyfm2L NXvPMVlc//Kc1WL+kXOsFr1rrjJZvJx1j83i/PkN7BabHl9jtfjYc4/V4vKuOWwWM87vY7K4 eMrV4v+eHewWh9+0s1r8u7aRxWLVrj+MDoIe72+0snvsnHWX3WPTqk42j81L6j36tqxi9Pi8 SS6ALYrLJiU1J7MstUjfLoErY0bPN8aC/ewVe2fuZWtgnMHWxcjJISFgIvH8SAdzFyMXh5DA bkaJBUfOM0MkRCU6LjcydjFyANnCEocPF0PUvGCUWHvyHStIDZuAusSStrXsIDaLgKrEks2r wGxhAU+J5fMPMILYvAKCEidnPmEBmcMsoCmxfpc+SJhZQF5i+9s5zBAlthIHb65lBikRArLP PwE7jVPATuLYsVOsIGtFBA4yS/x+840dxGEWOMkoMXHBdnaIO4UlPu9ewzaBUXAWknWzENbN QrJuASPzKkbJ1ILi3PTcZMMCw7zUcr3ixNzi0rx0veT83E2M4FjT0tjBeG/+P71DjEwcjIcY JTiYlUR4m8M3pQnxpiRWVqUW5ccXleakFh9ilOZgURLnNZwxO0VIID2xJDU7NbUgtQgmy8TB KdXA5B/xmyvlU57uxRn9B2rETlpN57Cfdj58sm721E9i74/tPaqQ8XvtfFvGnGnrHzRcerpv Sj2zy4qvd5JP3bnxy7NRXkj1gHxYt7T/5Iqn3HMmWPDN6mTwUKrs+7bDR2fDWpk6z0+2mz7a BRrfFOdoWde7eNckzzTG5YtSApZ+qlc6YRLykcm4cuqJsv3Cvs9FEqcbCYrsl1t6efvqqzIz nmefmDFDOrSSkdXh4tdVRaVHTrPdsy0WTQmbrprU4BCYvn7K77nateJ1E5La/3wv2dG5ZL52 IoO3LN/twpd/ldmVby+/mx6c8vO3kqm59htxZ/cS/vfKuov0Ld4sDZDu2M//2Ob31q8JfsF/ nMynKLEUZyQaajEXFScCAPs2wREkAwAA X-CMS-MailID: 20240809115500epcas1p34ab112e1a0da7247257b9cb8f7eafbe9 X-Msg-Generator: CA CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240809115500epcas1p34ab112e1a0da7247257b9cb8f7eafbe9 References: <20240809-clk_dpum-v3-0-359decc30fe2@samsung.com> Add dpum clock for sysmmu, dpu. Signed-off-by: Kwanghoon Son --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 0248329da49a..599e72824875 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -251,6 +251,16 @@ cmu_fsys2: clock-controller@17c00000 { "dout_fsys2_clkcmu_ethernet"; }; + cmu_dpum: clock-controller@18c00000 { + compatible = "samsung,exynosautov9-cmu-dpum"; + reg = <0x18c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_DPUM_BUS>; + clock-names = "oscclk", "bus"; + }; + cmu_core: clock-controller@1b030000 { compatible = "samsung,exynosautov9-cmu-core"; reg = <0x1b030000 0x8000>; From patchwork Fri Aug 9 11:54:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwanghoon Son X-Patchwork-Id: 818756 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B135194090 for ; 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Signed-off-by: Kwanghoon Son --- drivers/clk/samsung/clk-exynosautov9.c | 83 ++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index f04bacacab2c..5971e680e566 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -20,6 +20,7 @@ #define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1) #define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1) #define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1) +#define CLKS_NR_DPUM (CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1) #define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1) #define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1) #define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1) @@ -1076,6 +1077,85 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .clk_name = "dout_clkcmu_core_bus", }; +/* ---- CMU_DPUM ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_DPUM (0x18c00000) */ +#define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER 0x0600 +#define CLK_CON_DIV_DIV_CLK_DPUM_BUSP 0x1800 +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON 0x202c +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA 0x2030 +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP 0x2034 +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1 0x207c +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1 0x2084 +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1 0x208c +#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1 0x2094 + +static const unsigned long dpum_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, + CLK_CON_DIV_DIV_CLK_DPUM_BUSP, + CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, + CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, + CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1, +}; + +PNAME(mout_dpum_bus_user_p) = { "oscclk", "dout_clkcmu_dpum_bus" }; + +static const struct samsung_mux_clock dpum_mux_clks[] __initconst = { + MUX(CLK_MOUT_DPUM_BUS_USER, "mout_dpum_bus_user", + mout_dpum_bus_user_p, PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, 4, 1), +}; + +static const struct samsung_div_clock dpum_div_clks[] __initconst = { + DIV(CLK_DOUT_DPUM_BUSP, "dout_dpum_busp", "mout_dpum_bus_user", + CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock dpum_gate_clks[] __initconst = { + GATE(CLK_GOUT_DPUM_ACLK_DECON, "gout_dpum_decon_aclk", + "mout_dpum_bus_user", + CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, 21, + 0, 0), + GATE(CLK_GOUT_DPUM_ACLK_DMA, "gout_dpum_dma_aclk", "mout_dpum_bus_user", + CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, 21, + 0, 0), + GATE(CLK_GOUT_DPUM_ACLK_DPP, "gout_dpum_dpp_aclk", "mout_dpum_bus_user", + CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, 21, + 0, 0), + GATE(CLK_GOUT_DPUM_SYSMMU_D0_CLK, "gout_dpum_sysmmu_d0_clk", + "mout_dpum_bus_user", + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1, 21, + 0, 0), + GATE(CLK_GOUT_DPUM_SYSMMU_D1_CLK, "gout_dpum_sysmmu_d1_clk", + "mout_dpum_bus_user", + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1, 21, + 0, 0), + GATE(CLK_GOUT_DPUM_SYSMMU_D2_CLK, "gout_dpum_sysmmu_d2_clk", + "mout_dpum_bus_user", + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1, 21, + 0, 0), + GATE(CLK_GOUT_DPUM_SYSMMU_D3_CLK, "gout_dpum_sysmmu_d3_clk", + "mout_dpum_bus_user", + CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1, 21, + 0, 0), +}; + +static const struct samsung_cmu_info dpum_cmu_info __initconst = { + .mux_clks = dpum_mux_clks, + .nr_mux_clks = ARRAY_SIZE(dpum_mux_clks), + .div_clks = dpum_div_clks, + .nr_div_clks = ARRAY_SIZE(dpum_div_clks), + .gate_clks = dpum_gate_clks, + .nr_gate_clks = ARRAY_SIZE(dpum_gate_clks), + .nr_clk_ids = CLKS_NR_DPUM, + .clk_regs = dpum_clk_regs, + .nr_clk_regs = ARRAY_SIZE(dpum_clk_regs), + .clk_name = "bus", +}; + /* ---- CMU_FSYS0 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS2 (0x17700000) */ @@ -2085,6 +2165,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = { }, { .compatible = "samsung,exynosautov9-cmu-core", .data = &core_cmu_info, + }, { + .compatible = "samsung,exynosautov9-cmu-dpum", + .data = &dpum_cmu_info, }, { .compatible = "samsung,exynosautov9-cmu-fsys0", .data = &fsys0_cmu_info,