From patchwork Mon Nov 11 03:04:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179045 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp6076046ilf; Sun, 10 Nov 2019 19:04:55 -0800 (PST) X-Google-Smtp-Source: APXvYqxID6le3ylfqtAc2lZzfSCXHbZ3MYlB6+l7JjdeX85h3xZzcwi1h5fsojWWUBsmLWYEM/5a X-Received: by 2002:aa7:c453:: with SMTP id n19mr24728831edr.103.1573441495442; Sun, 10 Nov 2019 19:04:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573441495; cv=none; d=google.com; s=arc-20160816; b=CIPJJwIrd4d72t5wU7gumn6AvpU8bbzBPbBmMcIETRh0lvz6p258iSNCb6QbPdp7I0 K0J0D2yPHp/Gv193lCjwvpRTCnersK1qwz9rGMeZ5vvNQnrcyoHEf42OW8cIaPs7mxw4 e04+RIEJ8Baebyb5OPSezotWXXnYWRs39EKd8gHyvQLiPPb7DTWtVqW3YwrdYmHLLZAM BIOSAqz+GUih2NhrPhQk2GiROIbFIMTw6cBka28MS652b5tZh7ZloXMpRhaBBJ5cW4DO INn+ZOjLes4I93aKayABfj6VthED2axHi1DH9kcuhL/AbcmGoDjf41Q7DuRAtkFCvcGw GD2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=HnTKFHKiDGm/1WpINjqpiPE/bMj2p9BcDWIGuIVM99E=; b=MmFNom0iiFlVyq3bfO7tXil32TD6viHJf3MvQ+GsXHlUkMh8/XFbAlvJ+mc38bji9G sImYRtwd3G7WUlKb1f0BjhpC+q9ZGP5tll+UB9bLHma9Js7Bd053plCslIw91BQXoVEw 6sjgfzFbRIQOYRh1Uez2TI+1SgsVPlTNFIG519xiCCm7d3RsLAF65qQKIMjVRlbARyLq 3588LlR+RIyh7uVcF5ipsPSVRnn7Dw28KZgxdvBiDsjHncw2leRpKbVP+reUINlftOvS Z6RAvx487cVgpWu7S6Yq/L+HGUAO59xMebr1B+WkeaAZgAnFE1FNdavzIin10DCWf2lO DO8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w8si11625068edi.304.2019.11.10.19.04.55; Sun, 10 Nov 2019 19:04:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726830AbfKKDEw (ORCPT + 8 others); Sun, 10 Nov 2019 22:04:52 -0500 Received: from mx2.suse.de ([195.135.220.15]:54314 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726742AbfKKDEw (ORCPT ); Sun, 10 Nov 2019 22:04:52 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id B4830B150; Mon, 11 Nov 2019 03:04:49 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 3/7] arm64: dts: realtek: rtd129x: Introduce r-bus Date: Mon, 11 Nov 2019 04:04:30 +0100 Message-Id: <20191111030434.29977-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191111030434.29977-1-afaerber@suse.de> References: <20191111030434.29977-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Model Realtek's register bus in DT. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd129x.dtsi | 136 ++++++++++++++++--------------- 1 file changed, 72 insertions(+), 64 deletions(-) -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 8d80cca945bc..c4533a2555aa 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -55,70 +55,78 @@ /* Exclude up to 2 GiB of RAM */ ranges = <0x80000000 0x80000000 0x80000000>; - reset1: reset-controller@98000000 { - compatible = "snps,dw-low-reset"; - reg = <0x98000000 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@98000004 { - compatible = "snps,dw-low-reset"; - reg = <0x98000004 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@98000008 { - compatible = "snps,dw-low-reset"; - reg = <0x98000008 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@98000050 { - compatible = "snps,dw-low-reset"; - reg = <0x98000050 0x4>; - #reset-cells = <1>; - }; - - iso_reset: reset-controller@98007088 { - compatible = "snps,dw-low-reset"; - reg = <0x98007088 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@98007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x98007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@98007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x98007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; - }; - - uart1: serial@9801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; - }; - - uart2: serial@9801b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b400 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; + rbus: r-bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x100000>; + + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; + + iso_reset: reset-controller@7088 { + compatible = "snps,dw-low-reset"; + reg = <0x7088 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; }; gic: interrupt-controller@ff011000 { From patchwork Mon Nov 11 03:04:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179049 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp6076272ilf; Sun, 10 Nov 2019 19:05:11 -0800 (PST) X-Google-Smtp-Source: APXvYqz4ysDMy66Bk5avqYa9zg6v1v6CQHag4We3kZ2I9epqFoO/c3MFjCWDyMhwnOw+QJCFqEOh X-Received: by 2002:a17:906:85c8:: with SMTP id i8mr20642061ejy.46.1573441511001; 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[209.132.180.67]) by mx.google.com with ESMTP id p20si10606050edi.252.2019.11.10.19.05.10; Sun, 10 Nov 2019 19:05:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726927AbfKKDFF (ORCPT + 8 others); Sun, 10 Nov 2019 22:05:05 -0500 Received: from mx2.suse.de ([195.135.220.15]:54342 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726857AbfKKDEw (ORCPT ); Sun, 10 Nov 2019 22:04:52 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 8DFF5B157; Mon, 11 Nov 2019 03:04:50 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus Date: Mon, 11 Nov 2019 04:04:32 +0100 Message-Id: <20191111030434.29977-6-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191111030434.29977-1-afaerber@suse.de> References: <20191111030434.29977-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Model Realtek's register bus in DT. Signed-off-by: Andreas Färber --- This could be squashed into the original RTD1195 patch. arch/arm/boot/dts/rtd1195.dtsi | 52 ++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 22 deletions(-) -- 2.16.4 diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index a8cc2d23e7ef..3439647ecf97 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -92,28 +92,36 @@ <0x18100000 0x18100000 0x01000000>, <0x40000000 0x40000000 0xc0000000>; - wdt: watchdog@18007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x18007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@18007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x18007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; - }; - - uart1: serial@1801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; + rbus: r-bus@18000000 { + compatible = "simple-bus"; + reg = <0x18000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x100000>; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; }; gic: interrupt-controller@ff011000 { From patchwork Mon Nov 11 03:04:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179047 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp6076055ilf; Sun, 10 Nov 2019 19:04:56 -0800 (PST) X-Google-Smtp-Source: APXvYqzV22wBtOiyew+UPLQ/5AA5Lzf9H1T1Bx2VJ0+4eHjivGcKDkOUCLqfMRxVXO8PDAoBgbge X-Received: by 2002:a50:fe96:: with SMTP id d22mr24159730edt.227.1573441496200; Sun, 10 Nov 2019 19:04:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573441496; cv=none; d=google.com; s=arc-20160816; b=RcGt1cLgziF7OXvlOiaOajoJ8sUu0Yw00Jy/iDaGt9jZrhZXm1Z+PnW6B4OKBS/5B7 jfkQmC8SRRC9pnVyG1/4N4LNvwT/n0KQWKpeJYfbXSEB5UDJojbFlmGYpAy3Ykbc9p2l wwnq9I8pEldjuE+CoF2uRI1Dw92TtZg9S0VV3j6TFjH/E9v8IjLm1pgCfp8a5DqphKBl SNICh8VBJUiUMV7Wvr5h9lR1GZjpfUZiMtmP4jJJSkcIyZGYVJkrkE4Og9JPd95XGVy+ kAdYoplDhPACNjTb2gbNI6W5ttxmGeM/6b255kp/g+63b82tgWWz+wvJ1DYJBn1OVoXz yq3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Goi3uzA9Z/sJ1bPbrPCLVi1a7i5+d3TL1kV52gQkSMk=; b=iG+lIGLYN9UlUU4O6a7hcvvGI83dHrMJmA2WGitStAGdBAtfzm15hkP0zatbLEdQfF OpCymETkw1vJLdDZrFDIzYFlszV4FGIuOc9PFbuQCYLfT5FG3vXqqHTIKYpFO6wWYWaH /sLUvXvKL0KBIt8XCbzOXcxsFA/yS0So2/U976DCuvj2hiGLscX9zpeVgXdCss8VdYv8 j3gkTtjf5G1pDR4kd/46lnBcSrCva/FlBuX3D6zl5AlzoxjK6YcgYr3jb2FPkT3dejhK zrbE3sNxuKuh8zYOvfxVvAuOyKUcLOqXx+3cBnqbAf2hWjiYJE7nJYisvd8Y9/oi65VW UGrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w8si11625068edi.304.2019.11.10.19.04.56; Sun, 10 Nov 2019 19:04:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726985AbfKKDEy (ORCPT + 8 others); Sun, 10 Nov 2019 22:04:54 -0500 Received: from mx2.suse.de ([195.135.220.15]:54330 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726927AbfKKDEy (ORCPT ); Sun, 10 Nov 2019 22:04:54 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id CB503B18D; Mon, 11 Nov 2019 03:04:51 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: realtek: Add RTD1395 and BPi-M4 Date: Mon, 11 Nov 2019 04:04:34 +0100 Message-Id: <20191111030434.29977-8-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191111030434.29977-1-afaerber@suse.de> References: <20191111030434.29977-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Device Trees for Realtek RTD1395 SoC and Banana Pi BPi-M4 SBC. For now reuse RTD1295 reset constants. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/Makefile | 2 + arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts | 30 ++++++ arch/arm64/boot/dts/realtek/rtd1395.dtsi | 65 ++++++++++++ arch/arm64/boot/dts/realtek/rtd139x.dtsi | 141 +++++++++++++++++++++++++ 4 files changed, 238 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1395.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd139x.dtsi -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 555638ada721..edc85ee8c4bf 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -7,3 +7,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts new file mode 100644 index 000000000000..2163353fb132 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1395.dtsi" + +/ { + compatible = "bananapi,bpi-m4", "realtek,rtd1395"; + model = "Banana Pi BPI-M4"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi new file mode 100644 index 000000000000..05c9216a87ee --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1395 SoC + * + * Copyright (c) 2019 Andreas Färber + */ + +#include "rtd139x.dtsi" + +/ { + compatible = "realtek,rtd1395"; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi new file mode 100644 index 000000000000..3f5f308a4a10 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1395 SoC family + * + * Copyright (c) 2019 Andreas Färber + */ + +/memreserve/ 0x0000000000000000 0x0000000000030000; +/memreserve/ 0x0000000000030000 0x00000000000d0000; + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x98000000>; + + rpc_comm: rpc@2f000 { + reg = <0x2f000 0x1000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x1ffe000 0x4000>; + }; + + tee: tee@10100000 { + reg = <0x10100000 0xf00000>; + no-map; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x0 0x98000000 0x68000000>; + + rbus: r-bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x100000>; + + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; + + iso_reset: reset-controller@7088 { + compatible = "snps,dw-low-reset"; + reg = <0x7088 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,gic-400"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +};