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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4536a00291esi137667071cf.178.2024.08.20.19.27.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Aug 2024 19:27:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ff83HT2+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sgb30-0000eO-A9; Tue, 20 Aug 2024 22:26:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sgb2y-0000VH-Ac for qemu-devel@nongnu.org; Tue, 20 Aug 2024 22:26:04 -0400 Received: from mail-ot1-x336.google.com ([2607:f8b0:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sgb2v-0006DM-Uc for qemu-devel@nongnu.org; Tue, 20 Aug 2024 22:26:03 -0400 Received: by mail-ot1-x336.google.com with SMTP id 46e09a7af769-7093c94435bso2381032a34.0 for ; Tue, 20 Aug 2024 19:25:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1724207157; x=1724811957; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S39pbsi04lxxgffqB3S31UEXKo2fS7pxTQUq/De0mMM=; b=Ff83HT2+bhzCkN8PtwxeEw6vJ26ve01tJoWokh4hhWdjQ1UwFvds7mJSdpB+AVW1bh Z+APVO99bbSGnYnlcVxG9rv2MT/1p2k8xbuaOyWP8F/EVybAhlMa6shEvuBUbGLs3WUf zWvU3b5gsXwPNbIKLPObzQP5pUsmM1NGpUATORAqFWxP+M7JF6dhVFIaidYSAcgWz3YL Ooe6YBvL7j9ignw/TEzBDRT9n44xO1PYX+jN2AZmC7nq73SiE9ZRPMWPhFlpa7yS3pPQ 1tyx5REKwVvqQneq7elKdJhFjaeAj0Fuebat/lbEzf7NFt8zE9DlagV52fkyGIzMjjOj GTvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724207157; x=1724811957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S39pbsi04lxxgffqB3S31UEXKo2fS7pxTQUq/De0mMM=; b=ehxB/ypFojd7qNpBmlyQq+J+xvfoEcsDX8YvQEYc8xYQPcJw2/7NMCFHf63SrAEN08 Zyhhu37w1b1NGzWh3yW0Mw1aypkzDIN8olG/bHF773f3EXsT/YjoHEZT8Z9BLtF5sSzm Dtoiwy5wKBAIiYaV+8i3+8X9hpSAP7Sd/4uJyq/k3y1CPxduRl2k3Kj006vxHDNcRGhU 9KhyCb82uFipLMcjR3fFi4b3TZ8Fp9mSBTZozNmp8MddJH+Al+64aAy+flR1PlBIQoGt 3J7kWB2xB3q5iNuzktq1xAoIJdHHYR74k7t8qdvUbxUdu7InLHua3lMPFejTvMSbPt2X WXfQ== X-Gm-Message-State: AOJu0YyAfSFZOwCr+XskAz+g66w/Xku7AeEQYJBSZAGtnZJmu71rOWQx hZ9EVVkGkOXlGrkcq+Xixb1st13qf1wbdb2AzMhe8nvK0yfrWCrPuBBd30W6v/kn6uM/RaBIlB+ 0HiM= X-Received: by 2002:a05:6870:82a2:b0:258:5143:a21a with SMTP id 586e51a60fabf-2737ef0023bmr845403fac.13.1724207156792; Tue, 20 Aug 2024 19:25:56 -0700 (PDT) Received: from stoup.. ([203.56.140.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127af1888esm9210774b3a.149.2024.08.20.19.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 19:25:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 1/5] linux-user: Handle short reads in mmap_h_gt_g Date: Wed, 21 Aug 2024 12:25:44 +1000 Message-ID: <20240821022548.421745-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240821022548.421745-1-richard.henderson@linaro.org> References: <20240821022548.421745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In particular, if an image has a large bss, we can hit EOF before reading all host_len bytes of the mapping. Create a helper, mmap_pread to handle the job for both the larger block in mmap_h_gt_g itself, as well as the smaller block in mmap_frag. Cc: qemu-stable@nongnu.org Fixes: eb5027ac618 ("linux-user: Split out mmap_h_gt_g") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2504 Signed-off-by: Richard Henderson Message-Id: <20240820050848.165253-2-richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé --- linux-user/mmap.c | 44 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 6418e811f6..e4bf5d5f39 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -283,6 +283,40 @@ static int do_munmap(void *addr, size_t len) return munmap(addr, len); } +/* + * Perform a pread on behalf of target_mmap. We can reach EOF, we can be + * interrupted by signals, and in general there's no good error return path. + * If @zero, zero the rest of the block at EOF. + * Return true on success. + */ +static bool mmap_pread(int fd, void *p, size_t len, off_t offset, bool zero) +{ + while (1) { + ssize_t r = pread(fd, p, len, offset); + + if (likely(r == len)) { + /* Complete */ + return true; + } + if (r == 0) { + /* EOF */ + if (zero) { + memset(p, 0, len); + } + return true; + } + if (r > 0) { + /* Short read */ + p += r; + len -= r; + offset += r; + } else if (errno != EINTR) { + /* Error */ + return false; + } + } +} + /* * Map an incomplete host page. * @@ -357,10 +391,9 @@ static bool mmap_frag(abi_ulong real_start, abi_ulong start, abi_ulong last, /* Read or zero the new guest pages. */ if (flags & MAP_ANONYMOUS) { memset(g2h_untagged(start), 0, last - start + 1); - } else { - if (pread(fd, g2h_untagged(start), last - start + 1, offset) == -1) { - return false; - } + } else if (!mmap_pread(fd, g2h_untagged(start), last - start + 1, + offset, true)) { + return false; } /* Put final protection */ @@ -853,8 +886,7 @@ static abi_long mmap_h_gt_g(abi_ulong start, abi_ulong len, } if (misaligned_offset) { - /* TODO: The read could be short. */ - if (pread(fd, p, host_len, offset + real_start - start) != host_len) { + if (!mmap_pread(fd, p, host_len, offset + real_start - start, false)) { do_munmap(p, host_len); return -1; } From patchwork Wed Aug 21 02:25:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 820949 Delivered-To: patch@linaro.org Received: by 2002:adf:e98a:0:b0:367:895a:4699 with SMTP id h10csp504903wrm; Tue, 20 Aug 2024 19:27:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV72BP6dx1M1ZNvEO/tIRZwQwmKyLtTwlYABHs+d9RM1wSgaPuCDyKMBBAkZGYqvgkIzc6nRw==@linaro.org X-Google-Smtp-Source: AGHT+IF7VL4KKoNypcg2OpqBMep9vv5RuQH9I0y2vWkrvh90r6GQthmcSzRJx5GXWPW3djXIZjZo X-Received: by 2002:a05:6358:5242:b0:19e:fa9c:5ec9 with SMTP id e5c5f4694b2df-1b59f96c37amr160371155d.9.1724207244693; Tue, 20 Aug 2024 19:27:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1724207244; cv=none; d=google.com; s=arc-20160816; b=oUs+yR7VTXtK5/bWbZulGRSyhu2mdLdJMudVuPLGZj8L9chEGUJj9i6TKuo7SWkMra vUetohLWfr4Efiqk9V7dKxjqrQU0+tkB7RT9nKm/m8acGVORHUYx7gjOkcH2m4uEVIKY fRaC/GNBZsdhYew4+VlS00fOO1F9LWq2bBWt7qMVOOaYHZjPVMCglDSMGtnMdQctHRQV mSWYuQmAHRyOT6f5MibaWdKeCYB9EAysw9QoT/HIRqtgd1BS+oQHcgjjzNnEYvvCqYVY 6E2TwyrNnPtKSa7SUKgMcFpnjFPaKyu2JCYp4Ls9XqgN/MU+wXJSR4Dm+TRSD0Sxsdmv JewQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DVcCgltg45eJ8LECAIKCmNL12zJBy0OXmSR3imxiWNo=; fh=kQadAhxV42GJ3cd2VUw1RyURv/zJQGvmUdF7iLEVTtc=; b=gM0jFM9eqYYOfvxT53UskzpagCqA9rKVGerg1whEhhihjYYFtRwiWa2nSvIIkrY/Ub jpuvVaviX8a29rQku98E7CHyFhHDPecOS5mwowqvyvdHL3nGXLlUOqDDA5vfYVNgI+LN UM+4dNrX7lX4NEXAJr97CcolZeZu111KpOAGYV/WV9+Zi9Y8n7ZpcAisFWwowKK88wFi hy1J1h9QqfXP6N6Q/lDSjp5DcBWFbiY1RKjDV1fE2M8RpA6LYSxX8Xlqk1cQZPpy/TGj FAe6QV6YIuPHHDDZOsiklWcjvqUP8jwvB9OIjPBEHHrYkVLUlbzxgfmaqGXII2a7sSEF ISXA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evdP1HR6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([203.56.140.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127af1888esm9210774b3a.149.2024.08.20.19.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 19:25:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 2/5] bsd-user: Handle short reads in mmap_h_gt_g Date: Wed, 21 Aug 2024 12:25:45 +1000 Message-ID: <20240821022548.421745-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240821022548.421745-1-richard.henderson@linaro.org> References: <20240821022548.421745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In particular, if an image has a large bss, we can hit EOF before reading all bytes of the mapping. Mirror the similar change to linux-user. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240820050848.165253-3-richard.henderson@linaro.org> --- bsd-user/mmap.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index f3a4f1712d..775e905960 100644 --- a/bsd-user/mmap.c +++ b/bsd-user/mmap.c @@ -128,6 +128,40 @@ error: return ret; } +/* + * Perform a pread on behalf of target_mmap. We can reach EOF, we can be + * interrupted by signals, and in general there's no good error return path. + * If @zero, zero the rest of the block at EOF. + * Return true on success. + */ +static bool mmap_pread(int fd, void *p, size_t len, off_t offset, bool zero) +{ + while (1) { + ssize_t r = pread(fd, p, len, offset); + + if (likely(r == len)) { + /* Complete */ + return true; + } + if (r == 0) { + /* EOF */ + if (zero) { + memset(p, 0, len); + } + return true; + } + if (r > 0) { + /* Short read */ + p += r; + len -= r; + offset += r; + } else if (errno != EINTR) { + /* Error */ + return false; + } + } +} + /* * map an incomplete host page * @@ -190,7 +224,7 @@ static int mmap_frag(abi_ulong real_start, mprotect(host_start, qemu_host_page_size, prot1 | PROT_WRITE); /* read the corresponding file data */ - if (pread(fd, g2h_untagged(start), end - start, offset) == -1) { + if (!mmap_pread(fd, g2h_untagged(start), end - start, offset, true)) { return -1; } @@ -565,7 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, -1, 0); if (retaddr == -1) goto fail; - if (pread(fd, g2h_untagged(start), len, offset) == -1) { + if (!mmap_pread(fd, g2h_untagged(start), len, offset, false)) { goto fail; } if (!(prot & PROT_WRITE)) { From patchwork Wed Aug 21 02:25:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 820948 Delivered-To: patch@linaro.org Received: by 2002:adf:e98a:0:b0:367:895a:4699 with SMTP id h10csp504856wrm; Tue, 20 Aug 2024 19:27:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVR5lcAexTq2PUCD1FTrBlWUbo0ypwi8GCcnoYcOovkaF0z8HfCSvrUVNDXICfN6rUeCvaSwQ==@linaro.org X-Google-Smtp-Source: AGHT+IFeeRzSv0+mlfirg4kNMxzMxYXpCuvUcpVI0fcF7bm92gwVz0PrcPiLZxlTEsebfrXRLwEm X-Received: by 2002:a05:620a:31a3:b0:79d:7149:764e with SMTP id af79cd13be357-7a674002c87mr162226885a.14.1724207232898; Tue, 20 Aug 2024 19:27:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1724207232; cv=none; d=google.com; s=arc-20160816; b=fKVvUYgQwEgNQMtRnPlR4KGQY/s0nL4gGFh5mYpAJq33K2RniacTrefFbYP+8eCJ4e bRhPL7XBq6e1IEZmB64i91/N/H3DvumUISJPwlMzhBxCqgtCm0bC+YEFyWpa0dSJZVTB sTwkjGhK8FHBEMlEkWcciiTjNduIM/dDRubTJ9ahED2O0zGNk3jX2bPVp1aAEosZJK89 GQ/gq8RF3zWVOCK0rYgb5JU1+jA0EuU3bxidPQtYM0gF6NM+o4FG19sB8NDqt0gctA/B ZLymbWQHD7/zpRQNg9b6K6QpJyKTK+l7Z24BNfziRcWvAm17apBlTSSREZ4X39VDjLfD WFNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/AkyOxiQ4TXnW/njwRxZXuZWiuFAeAcYAa7CbQEQtFY=; fh=kQadAhxV42GJ3cd2VUw1RyURv/zJQGvmUdF7iLEVTtc=; b=hMYGFsXmIy0xAUN7Z9iD/xAkxwCobPsLiAjnR9wkx3CmGb63y52jewpOCjPpZPtrE3 w5uUASv+2NRR1eUdNBWpc4X7pBiLHVNrocrGmJujiVwZf9FSnQA1+5eCkYmXrfSpCFpD FxcV/Ue99qAM3McMLtGngV1hpDCyqJOiZDoD4nyHz/qS+dhNh44fWXPeS52mLvIuASTC jtBzPEfhx9ujR4DZ7HkSWNnB8l117jBTekSQHyVRe/9XPEcw8iLiDcD40ET21w8RIoiL sTpJDdbmIXc7wyZbWYcNON0eIel0tpp2KLALA/3CWjsbNqUiv1r4gHr5o9JPI+fleChW EMBA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=klDUVP8e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([203.56.140.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127af1888esm9210774b3a.149.2024.08.20.19.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 19:26:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 3/5] target/i386: Split out gen_prepare_val_nz Date: Wed, 21 Aug 2024 12:25:46 +1000 Message-ID: <20240821022548.421745-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240821022548.421745-1-richard.henderson@linaro.org> References: <20240821022548.421745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split out the TCG_COND_TSTEQ logic from gen_prepare_eflags_z, and use it for CC_OP_BMILG* as well. Prepare for requiring both zero and non-zero senses. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20240801075845.573075-2-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b72864bf01..4af282e626 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -865,6 +865,18 @@ static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size) } } +static CCPrepare gen_prepare_val_nz(TCGv src, MemOp size, bool eqz) +{ + if (size == MO_TL) { + return (CCPrepare) { .cond = eqz ? TCG_COND_EQ : TCG_COND_NE, + .reg = src }; + } else { + return (CCPrepare) { .cond = eqz ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + .imm = MAKE_64BIT_MASK(0, 8 << size), + .reg = src }; + } +} + /* compute eflags.C, trying to store it in reg if not NULL */ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) { @@ -908,8 +920,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) case CC_OP_BMILGB ... CC_OP_BMILGQ: size = s->cc_op - CC_OP_BMILGB; - gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); - return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src }; + return gen_prepare_val_nz(cpu_cc_src, size, true); case CC_OP_ADCX: case CC_OP_ADCOX: @@ -1006,12 +1017,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) default: { MemOp size = (s->cc_op - CC_OP_ADDB) & 3; - if (size == MO_TL) { - return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst }; - } else { - return (CCPrepare) { .cond = TCG_COND_TSTEQ, .reg = cpu_cc_dst, - .imm = (1ull << (8 << size)) - 1 }; - } + return gen_prepare_val_nz(cpu_cc_dst, size, true); } } } From patchwork Wed Aug 21 02:25:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 820946 Delivered-To: patch@linaro.org Received: by 2002:adf:e98a:0:b0:367:895a:4699 with SMTP id h10csp504702wrm; Tue, 20 Aug 2024 19:26:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX1OSC3f5xIZ2+YWgNeOrEzqgnbbr9OMOxPNdZR1dCyomxsznzv65VO2xXVKmws1zUJIpahUw==@linaro.org X-Google-Smtp-Source: AGHT+IEhG5C/234lxAdemRX/L4D14ccrOflThiHQvDGW21T0pETTvUIUomYpjTFJ7ovIDi6W05Zg X-Received: by 2002:a05:6358:52c1:b0:1ac:1492:8d5a with SMTP id e5c5f4694b2df-1b59f97aad0mr164966255d.14.1724207188881; Tue, 20 Aug 2024 19:26:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1724207188; cv=none; d=google.com; s=arc-20160816; b=rQdK0hMwSxG+lB0onGu6RZ7h6ID5+adVeMnMZEYlpWjPW7ldsdqRbdcADGDn6A5VpF 5aOiSfDjarqIATS81408YFcFPccjxHgEl+u70nDIuy3aZ9enDDu7C+OscO+nGu0IHyBa hIQNba8cJjyxA8rm6W89auUARFD3OHljCU2fEmu1gJofkwQ16gOFMz9rokDaT81v9989 sb0VS2AumlBpONFLGBdZN1GcEVJZS/CCvBU+obLgI8qhg7uneXpA1Cf2jdi3O5942Z6E xLMLWRTH1PtaqdZk8wNHAO6KXVLdA7jx0xi/yQ2B9228i+Km0ba2MiaNrXscMoahh647 GPfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MzQq+okHryK0atM5VhMyw1ZWBZUUJZorcvwNEKWon4U=; fh=kQadAhxV42GJ3cd2VUw1RyURv/zJQGvmUdF7iLEVTtc=; b=vN/+HuAPEQeIQg+9bJslGTUtRGdhwIze9n6s8csy1UwJqRUVi5Y+g4C7nlMpDxgxfQ QiE5E5TukccdCz3PM8brl73aFrpiE/zMm3JAfsORYchRUsOPKh1eQo5SHFT9SKVKg34+ iXi5PiCbzHDJ4VOtbeK/NSR2y3gTAJG+1pW94iJas9S0Pc/iADE5xbmp+sM2i5Fgw22/ IiwbIRTVxbWWwjB1OZQ/smxZoUIVEYycn2gdqmxw/UAt3wu824/motmT2cr7m0rlGSgG kMK0D4R8xliK5XvNS2jG3jgOitzJQh0tRKasXkoc+g61mRmOVbELAgp87OgQdZmSgcCM EE8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yNxWZUbh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([203.56.140.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127af1888esm9210774b3a.149.2024.08.20.19.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 19:26:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 4/5] target/i386: Fix carry flag for BLSI Date: Wed, 21 Aug 2024 12:25:47 +1000 Message-ID: <20240821022548.421745-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240821022548.421745-1-richard.henderson@linaro.org> References: <20240821022548.421745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org BLSI has inverted semantics for C as compared to the other two BMI1 instructions, BLSMSK and BLSR. Introduce CC_OP_BLSI* for this purpose. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2175 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240801075845.573075-3-richard.henderson@linaro.org> --- target/i386/cpu.h | 5 +++++ target/i386/tcg/cc_helper.c | 18 ++++++++++++++++++ target/i386/tcg/translate.c | 5 +++++ tests/tcg/x86_64/test-2175.c | 24 ++++++++++++++++++++++++ target/i386/tcg/cc_helper_template.h.inc | 18 ++++++++++++++++++ target/i386/tcg/emit.c.inc | 2 +- tests/tcg/x86_64/Makefile.target | 1 + 7 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/x86_64/test-2175.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c6cc035df3..14edd57a37 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1339,6 +1339,11 @@ typedef enum { CC_OP_BMILGL, CC_OP_BMILGQ, + CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */ + CC_OP_BLSIW, + CC_OP_BLSIL, + CC_OP_BLSIQ, + /* * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size) * is used or implemented, because the translation needs diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index 301ed95406..dbddaa2fcb 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -186,6 +186,13 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1, case CC_OP_BMILGL: return compute_all_bmilgl(dst, src1); + case CC_OP_BLSIB: + return compute_all_blsib(dst, src1); + case CC_OP_BLSIW: + return compute_all_blsiw(dst, src1); + case CC_OP_BLSIL: + return compute_all_blsil(dst, src1); + case CC_OP_ADCX: return compute_all_adcx(dst, src1, src2); case CC_OP_ADOX: @@ -216,6 +223,8 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1, return compute_all_sarq(dst, src1); case CC_OP_BMILGQ: return compute_all_bmilgq(dst, src1); + case CC_OP_BLSIQ: + return compute_all_blsiq(dst, src1); #endif } } @@ -308,6 +317,13 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1, case CC_OP_BMILGL: return compute_c_bmilgl(dst, src1); + case CC_OP_BLSIB: + return compute_c_blsib(dst, src1); + case CC_OP_BLSIW: + return compute_c_blsiw(dst, src1); + case CC_OP_BLSIL: + return compute_c_blsil(dst, src1); + #ifdef TARGET_X86_64 case CC_OP_ADDQ: return compute_c_addq(dst, src1); @@ -321,6 +337,8 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1, return compute_c_shlq(dst, src1); case CC_OP_BMILGQ: return compute_c_bmilgq(dst, src1); + case CC_OP_BLSIQ: + return compute_c_blsiq(dst, src1); #endif } } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4af282e626..98f5fe61ed 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -304,6 +304,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = { [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC, + [CC_OP_BLSIB ... CC_OP_BLSIQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC, [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2, [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, @@ -922,6 +923,10 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) size = s->cc_op - CC_OP_BMILGB; return gen_prepare_val_nz(cpu_cc_src, size, true); + case CC_OP_BLSIB ... CC_OP_BLSIQ: + size = s->cc_op - CC_OP_BLSIB; + return gen_prepare_val_nz(cpu_cc_src, size, false); + case CC_OP_ADCX: case CC_OP_ADCOX: return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_dst, diff --git a/tests/tcg/x86_64/test-2175.c b/tests/tcg/x86_64/test-2175.c new file mode 100644 index 0000000000..aafd037bce --- /dev/null +++ b/tests/tcg/x86_64/test-2175.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* See https://gitlab.com/qemu-project/qemu/-/issues/2185 */ + +#include + +int test_setc(unsigned int x, unsigned int y) +{ + asm("blsi %1, %0; setc %b0" : "+r"(x) : "r"(y)); + return (unsigned char)x; +} + +int test_pushf(unsigned int x, unsigned int y) +{ + asm("blsi %1, %0; pushf; pop %q0" : "+r"(x) : "r"(y)); + return x & 1; +} + +int main() +{ + assert(test_setc(1, 0xedbf530a)); + assert(test_pushf(1, 0xedbf530a)); + return 0; +} + diff --git a/target/i386/tcg/cc_helper_template.h.inc b/target/i386/tcg/cc_helper_template.h.inc index bb611feb04..c5425e57cf 100644 --- a/target/i386/tcg/cc_helper_template.h.inc +++ b/target/i386/tcg/cc_helper_template.h.inc @@ -235,6 +235,24 @@ static int glue(compute_c_bmilg, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1) return src1 == 0; } +static int glue(compute_all_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1) +{ + int cf, pf, af, zf, sf, of; + + cf = (src1 != 0); + pf = 0; /* undefined */ + af = 0; /* undefined */ + zf = (dst == 0) * CC_Z; + sf = lshift(dst, 8 - DATA_BITS) & CC_S; + of = 0; + return cf | pf | af | zf | sf | of; +} + +static int glue(compute_c_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1) +{ + return src1 != 0; +} + #undef DATA_BITS #undef SIGN_MASK #undef DATA_TYPE diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 22a06897fb..9b50419918 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1304,7 +1304,7 @@ static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode) /* input in T1, which is ready for prepare_update2_cc */ tcg_gen_neg_tl(s->T0, s->T1); tcg_gen_and_tl(s->T0, s->T0, s->T1); - prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); + prepare_update2_cc(decode, s, CC_OP_BLSIB + ot); } static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode) diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target index eda9bd7396..783ab5b21a 100644 --- a/tests/tcg/x86_64/Makefile.target +++ b/tests/tcg/x86_64/Makefile.target @@ -16,6 +16,7 @@ X86_64_TESTS += noexec X86_64_TESTS += cmpxchg X86_64_TESTS += adox X86_64_TESTS += test-1648 +X86_64_TESTS += test-2175 TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64 else TESTS=$(MULTIARCH_TESTS) From patchwork Wed Aug 21 02:25:48 2024 Content-Type: text/plain; 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([203.56.140.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127af1888esm9210774b3a.149.2024.08.20.19.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 19:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , Pierrick Bouvier Subject: [PULL 5/5] target/i386: Fix tss access size in switch_tss_ra Date: Wed, 21 Aug 2024 12:25:48 +1000 Message-ID: <20240821022548.421745-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240821022548.421745-1-richard.henderson@linaro.org> References: <20240821022548.421745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The two limit_max variables represent size - 1, just like the encoding in the GDT, thus the 'old' access was off by one. Access the minimal size of the new tss: the complete tss contains the iopb, which may be a larger block than the access api expects, and irrelevant because the iopb is not accessed during the switch itself. Fixes: 8b131065080a ("target/i386/tcg: use X86Access for TSS access") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2511 Signed-off-by: Richard Henderson Message-Id: <20240819074052.207783-1-richard.henderson@linaro.org> Reviewed-by: Peter Maydell Reviewed-by: Pierrick Bouvier --- target/i386/tcg/seg_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index bab552cd53..3b8fd827e1 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -378,7 +378,7 @@ static int switch_tss_ra(CPUX86State *env, int tss_selector, /* X86Access avoids memory exceptions during the task switch */ mmu_index = cpu_mmu_index_kernel(env); - access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max, + access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max + 1, MMU_DATA_STORE, mmu_index, retaddr); if (source == SWITCH_TSS_CALL) { @@ -386,7 +386,8 @@ static int switch_tss_ra(CPUX86State *env, int tss_selector, probe_access(env, tss_base, 2, MMU_DATA_STORE, mmu_index, retaddr); } - access_prepare_mmu(&new, env, tss_base, tss_limit, + /* While true tss_limit may be larger, we don't access the iopb here. */ + access_prepare_mmu(&new, env, tss_base, tss_limit_max + 1, MMU_DATA_LOAD, mmu_index, retaddr); /* save the current state in the old TSS */