From patchwork Wed Aug 28 15:46:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 824149 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85BBE83A18; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; cv=none; b=RNeyoMlrrg2mcJ1TbX2ZUoCd4JCrYwvA6s7U/QUy1Vb2fcijJqbU8wpJSvN5CjAX1HsaxCD91pDQj84UDyhYwplLn/vG2EvydVI5IHOUt/rs5Lp7tm6CdKv1bYhmzlqBqDNjeX2S8NQRQO8agamJ/TmpPevI3y95WmIOglKHNZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; c=relaxed/simple; bh=+Tkqhar4vQYGZIgL28NlgG1tVNG3i9So+0zA8BWKYOU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kpY0Wz0lbGNON+wOeUxgqHEsiiuSL/GfquLyJREiAQVRKPGlAE7KqrKB7H3b6WAS6N7Yeq7ek5l/uw1G3LXXIcQYVvVE8HK6ge0DOVbb5+5sqbCd9N5ZpUsYqLihd8/jabfobhju2QckMVukkGIzgLFUrQPIdShw3fYkxq+xXFM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Wni5p08Y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Wni5p08Y" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3B09CC4AF17; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=+Tkqhar4vQYGZIgL28NlgG1tVNG3i9So+0zA8BWKYOU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Wni5p08Y4poqJ7JER7adnz1qawx2bLu9g3YNgIuzMOYx9sidu3IqiZYbUk+wnR1iI ZozrhbHH+XRKdmv9+0EB5xQCkgpsKtKY1yacx61cSHK2xgFDDQja4LDyIPxw5o3KSd peVqNOmQz0aYvU0BFOywptpS07TnwFnvcTajpAAoXDQC+SVBmv5KtKvZYhUkR8dkKK PwP9Q9xUYFJJ3YP5y/Vc3XkB0UbiS1BXf7dDeyg8boMlL07U74IzjnJIZCGbi3cEn3 AOOid9h/+I03RurhNbQkbMFYOJ4kxv+Q/akh0YGsUKuMlksxs9f4SRpB/VxYmhuvk5 nsx8KCyFv62iA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24E2CC61CF0; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:12 +0530 Subject: [PATCH v4 02/12] PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-2-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1256; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=B8RUdvVv9QEg4h2fDtSWIh3luhRVOKTDULQMHpO/Rk0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZLNt9QNPKv9NKAKbZ5eVVEDlJxVPTsCl4yZ H4jVagxg8KJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GSwAKCRBVnxHm/pHO 9cEpB/4hP+YKCmtIoOu2Hobc2nRJn8ozN5UY9byuFg1YQ5A1UEpxS1qIj/AsDmQdV9VTq5uHzGM 328jQY5jYgixBeIhqP4j1hMIWYRj1u/IsKn0n+dIuIU3dG6LE/YZ7nEKXToBSR72kQDRqO59alz WzXQTeR8g87j1LgD4ZjW61UaFEEWMFrDZFHezITn8NV9Oy0lbwJRaV7QDzlVgpuIWPkP2a7Kzhl dc2+VD7cLBgch/22b8vPvycHUyVl+UzorHJhFDRkSBx8eu7jpX78UD738y9xO7ESP5/Z9JwJNKC ucR+cweFjvWOdffPpzPYLz3GBumFwjJcJEGsVOy2gwP8c/UG X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Current error message just prints the contents of PARF_INT_ALL_STATUS register as if like the IRQ event number. It could mislead the users. Reword it to make it clear that the error message is actually showing the interrupt status register to help debug spurious IRQ events. While at it, let's also switch over to dev_WARN_ONCE() so that any IRQ storm won't flood the kernel log buffer. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 972a90eba494..0bb0a056dd8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -679,7 +679,8 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dw_pcie_ep_linkup(&pci->ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; } else { - dev_err(dev, "Received unknown event: %d\n", status); + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); } return IRQ_HANDLED; From patchwork Wed Aug 28 15:46:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 824147 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EDC81A2C20; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; cv=none; b=AQBs+JqsdwNaiSVEpgx27RTju6cmXnx9/a5bK1wcKAcuk2am7i2c2qekeQB3OXax/qDFzOpFZwLXulzZzEyP6YDQAQS/6BdtCKWtoBhtA6d8Vh2rW7CqBH7F6Jk5b/bao+x8z08ZfEoD6imiBp6OqijLDp0OJ3CYVB2WI5f2KH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859984; c=relaxed/simple; bh=Dynz9QHhPHZXKKO8GD6i2AnmK4GVgprdx9YpUpdCd88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I55X1T8b/h+GIbFnrzBzFOxJmxw/gsi42Ee7wHxpTifP1L5y1b8bW774PEevXHuRaprT1fOOxHPWL42uI7J98+9qunIZ6M9ELWVXQ3AlhO8uWuXKQW608UCN/tKOdSoBkvjq+GAExPkGz9g1WxouYHXPTJg8aYw3/ASKd37f+7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F4Z4rbfF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F4Z4rbfF" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4DB6AC4CECE; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=Dynz9QHhPHZXKKO8GD6i2AnmK4GVgprdx9YpUpdCd88=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=F4Z4rbfFbsYLAEqCjFwS63fu1HWvCe5kXa1Ylq2xDV1rbs92LDmR/3+Uk2A9SePNl NwHmWsdNIPGQioyz2NrocKh3Myc6dF+MeovRBlXg/sHyACGGiBZngZSzyd9Hz4Y98i zTHqSmQ3qjvOQSlyKNT9xDQQkR+cutf2oKnB2maHxmJBh95ubA4OmlP439SCrkbN/J lZaW1J23nAEMsNHEYyFN4o41kxtWWXzQrT5PINQt+Eg2tDou+MG4W9GHLTk0UrEy+V 2UAZVqsDIXKuIEt5Uk4JUisaUGAz0ZXNYoYZvN1chNE6YJ+1IG8RiVC+XcJQpHrxTe 26L6z+75OYPJQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 374A6C61DB8; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:13 +0530 Subject: [PATCH v4 03/12] dt-bindings: PCI: pci-ep: Update Maintainers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-3-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1035; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5QyilnsJ9fmtdU7GTZXO3WdPGs0Omyndpvk9fplsO9U=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZL9jhf9luAKQ8qfWImj9qozgYiGeIAlxwGL prt2m7x4peJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GSwAKCRBVnxHm/pHO 9T1+CACHbI2AivhKTRkze2MUArBxKQMu0jB/2dJ5a9eEid1AW1bg1voHlMvfKVnfrBW/PkvFf+1 bd6g/ZBNzp1wu1vLZKCMmZU/jhNBOdb1ANYCE0hYmHd4VvBBO2tbPpPcjBcbicni6Jkf78JqcH9 ssFKzRDcMViCUF/0Afu02ovq4o9PQTptUGVYksvd/pzlPLQlE1ndFgIvWvnzxua8xuz5ix29ceA giFSwuEkggtV0xcbedZUKkZmhO74SihSSYVRA4ElnStGan9MiZX4kl5BJj/Vq6jFvSfh5Gk8mR7 DAei/rpgIHWqKfTpNlBNV517jJakADUbRc+D2XOn/HPgwI4g X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Kishon's TI email ID is not active anymore, so use his korg ID. Also, since I've been maintaining the PCI endpoint framework, I'm willing to maintain the DT binding as well. So add myself as the Co-maintainer. Acked-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index d1eef4825207..0b5456ee21eb 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -10,7 +10,8 @@ description: | Common properties for PCI Endpoint Controller Nodes. maintainers: - - Kishon Vijay Abraham I + - Kishon Vijay Abraham I + - Manivannan Sadhasivam properties: $nodename: From patchwork Wed Aug 28 15:46:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 824146 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D61841A38FC; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V+gTKry5" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6C1CEC4CEDB; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=xZou4yYTmrNODLhCzXW2Q/Fu7bpHNuL+kgj7Jhe8ZXU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=V+gTKry5Ve807aOn5WR479TpGgrA1NSOdZgvx4Vi0r90t5+1Umnrsi+oiipHsaZBQ U0FbAHnEBM3KsoQQDApFhBnze8OrzkBNyGoVrU08xgcFqEcLZQe3lApLUw9xqcZowt 247Y2azLLa8jLY3v+95JVRsxRAWXCn+Dbd75cw2WRMUOaxBNfSZjpQR109htP371Uj uoeA12h5pILt3UP3xD5cPxqPsTw2tJPnOzws8ag0yossyiGKxFeVhaJ+jCMu6TEc4n JuPWyYewxta6PkC0qMAjWCgQWxFGZVw09f0SxQxGg0W340dq+v1BEHygc5r1KShRZo avRUtCTjB3wVA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61936C63685; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:15 +0530 Subject: [PATCH v4 05/12] PCI: endpoint: Assign PCI domain number for endpoint controllers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-5-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3110; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5oeMGhfukDvga7v0phuNZcmCcF8YceRyJh0rWzD+y8Y=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZLMf4c60sIeK74cdHIg0yL5hYSc4llzQR4Y atcIdalTDuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GSwAKCRBVnxHm/pHO 9ZNRB/9Nmlg/e7/yWhzNE70DQZ3sD6X3ZNNWNXP3QiZI3eTyxL3sL52VAr8qBP7dYF6gIMvDt+j ZxL/EmnrHNI2IU7/TM4AiL0lwBdf8v8/e1+wX5+eFgdNOy1MuIreVI96czTDDgKC/1XcilPzs1A REas1z53pYxuDsgyOdyiPpNBWgMyNhykp7Xbdy7/noruzAqiZwgu0+cmTp0nQctuMcUbPe6Ke3Q e/IiItuCxWHQz2zy6dkJs7NEsJ3NfgJRTctBK08Eh74STgTM4PTTW0reqkk/haPvpZZn26+gnHV R2zGO1hI06vFFAzao2IbKNm4yQLgJoREtlSnltxo2G9qoDrC X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Right now, PCI endpoint subsystem doesn't assign PCI domain number for the PCI endpoint controllers. But this domain number could be useful to the EPC drivers to uniquely identify each controller based on the hardware instance when there are multiple ones present in an SoC (even multiple RC/EP). So let's make use of the existing pci_bus_find_domain_nr() API to allocate domain numbers based on either Devicetree (linux,pci-domain) property or dynamic domain number allocation scheme. It should be noted that the domain number allocated by this API will be based on both RC and EP controllers in a SoC. If the 'linux,pci-domain' DT property is present, then the domain number represents the actual hardware instance of the PCI endpoint controller. If not, then the domain number will be allocated based on the PCI EP/RC controller probe order. If the architecture doesn't support CONFIG_PCI_DOMAINS_GENERIC (rare), then currently a warning is thrown to indicate that the architecture specific implementation is needed. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 14 ++++++++++++++ include/linux/pci-epc.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 84309dfe0c68..085a2de8b923 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -838,6 +838,10 @@ void pci_epc_destroy(struct pci_epc *epc) { pci_ep_cfs_remove_epc_group(epc->group); device_unregister(&epc->dev); + +#ifdef CONFIG_PCI_DOMAINS_GENERIC + pci_bus_release_domain_nr(NULL, &epc->dev); +#endif } EXPORT_SYMBOL_GPL(pci_epc_destroy); @@ -900,6 +904,16 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, epc->dev.release = pci_epc_release; epc->ops = ops; +#ifdef CONFIG_PCI_DOMAINS_GENERIC + epc->domain_nr = pci_bus_find_domain_nr(NULL, dev); +#else + /* + * TODO: If the architecture doesn't support generic PCI + * domains, then a custom implementation has to be used. + */ + WARN_ONCE(1, "This architecture doesn't support generic PCI domains\n"); +#endif + ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); if (ret) goto put_dev; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 85bdf2adb760..8e3dcac55dcd 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -128,6 +128,7 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number + * @domain_nr: PCI domain number of the endpoint controller * @init_complete: flag to indicate whether the EPC initialization is complete * or not */ @@ -145,6 +146,7 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; unsigned long function_num_map; + int domain_nr; bool init_complete; }; From patchwork Wed Aug 28 15:46:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 824145 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E97CB1A3BCE; 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a=openpgp-sha256; l=986; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+Lb2vcF7RPFdOyct+N0+V3AMTmLDYS+SRQY7Fw3HIuE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZM83Z35engVsqec9Qy5XqLnwNrE3yue0oFr R5aI0n2kJ2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTAAKCRBVnxHm/pHO 9ZQpB/4urQR2QZAmwGp5/dqgmYbmQpFMcVLNKBSE5clsO6sHL7t11dfZG4AGzvrMULZXnV6717K qs9cNsufZRyYLTxFB55wWkQtv71t9YRVEPxcF+LvPaA1v7yDqzcxKTouj5ns2A4/3J1ZQNS7TVG ApV1piB+JCX4nHLpRMBohk9FLJuxiYcxYMFmxeb44g/6McxFxxPMDCjVIq7SHf9hz54oTDvNfzi bjQ2DChgd3UxwTO65qM9FoS5LRvtQDVGIxhy94lHrq8QdizvRwFdxh0kSTD5KGr2d5wfVBVzqwi ZxV6yzDbVtJ7SFIJEgXiLKwVgmH3C0OlqVcez+LACnod1wl9 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX55 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..d0f6120b665d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Aug 28 15:46:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 824143 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 570961AAE1C; Wed, 28 Aug 2024 15:46:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859987; cv=none; b=RTMAWYp2pmqjzsSFFpMUjIA1A7blfy8nT8Invn7NQbLIBeldAGSmflUETkRNhkd4qMV/D8L556NQ8x2aQu+lz/h5o0aqSGGsSbV5J4wbnrKMmXTWb80lFccgNIjOJD5gO3qEsPxrYjSRv0Ft9qtJnb5AiQ5gOX5A53a46UjDmE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859987; c=relaxed/simple; bh=F3tlcZYkq7aH9cd8XiPnDgHNXtfM6IsBl+yJgxAu458=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WjtwDeJ7aXOFJtvFVXAyLUHkr+hYiYqflqZpRivOzzUHMXCYPZIqHcuCV7QnaTPtr7A+K9GWdKjDQV39hIHsGAhG0KOx46cYY0Qfd6BJ+BXySlaRbO5vsZ/aqUkeHqO91HwSwrhN/hmJ+j4JImc9oj6XKm6lnswVagNCC6iIIgo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G02gvhg3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G02gvhg3" Received: by smtp.kernel.org (Postfix) with ESMTPS id D97A0C4CEF3; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724859984; bh=F3tlcZYkq7aH9cd8XiPnDgHNXtfM6IsBl+yJgxAu458=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=G02gvhg3wzK4EFaGx02Cv+sihP8gBSxncT4a7lDK1nyXyf3mPBczATbikiTvaXqYf UD+3kkygagizZqcR00HNNpQEeRiLMOyV3rmeMTmJKeAoAsfahCr5J4LA28nVxfbLi/ mxAZhj/yquUOcuXJxt5Eb+qYy6HK3oAmVTOVwccTVxYYBCiuwvUFTXWLpiI62tPt5H Lm1dDwrj1Yvnf8Q7kjDqctnD2zFXB+vzpQ6xpWNIqFn55rnt3PXysJ4Z6HE5SDIBFD rKpS2RcE7/DfLAhRanTyYiqtNZs2CLEDg7odnyxgUSZYfFfo6Hn/pOikrz50SWcNla Bv9PT5tLY+8rg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0822C61DB8; Wed, 28 Aug 2024 15:46:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 28 Aug 2024 21:16:20 +0530 Subject: [PATCH v4 10/12] dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-pci-qcom-hotplug-v4-10-263a385fbbcb@linaro.org> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2750; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=DyBVQRLO1Cvv6lhUcJR+pkpUwb9nrOEo4mxqLaOumRw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZN73vihZy1iEXaEcTGQKkDZREqQZS/aQCIQ Tp/HiXFbxiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTQAKCRBVnxHm/pHO 9f0+B/wK7H1XmDJUhCBbN/HOdnPxMEI0TodYU5qwzRf3wBq/v5DsKb0wHx7u5Rb4FogLmE+qbjI nU77ZbDUQezrMrbsl4V3lbw6d/rG0n9cbTCvUOnD+8IGa2XsCe0YcfO7jGIl8kh1qZiDGOnF2l5 YJuOVQCwPabpmmjZNiQkiNxz9ZqRjquNgxOWb7uziTlelaMEyAf2HPvVJ7HpsklfoHB9UKAIIc7 PGZajtULee1PLbSn3M6FdsGnWLtYiPRQFR6r1dGnj0afaDRjCKf9AjZK45Se79yVqCnEN9MxOkx EtB/ypOK7rC3vrpDjrb1Z0lDviYTaFxx73w5P0LVuqjrMKPL X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Though adding a new interrupt will break the ABI, it is required to accurately describe the hardware. Reviewed-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++-- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0a39bbfcb28b..704c0f58eea5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -21,11 +21,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index d8c0afaa4b19..46bd59eefadb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -55,8 +55,8 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 interrupt-names: items: @@ -68,6 +68,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global operating-points-v2: true opp-table: @@ -149,9 +150,10 @@ examples: , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Wed Aug 28 15:46:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 824144 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29D671A4F10; Wed, 28 Aug 2024 15:46:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724859985; cv=none; b=ed4o0fvq0wjC+gPzrDaOS2FU/Ua8VLfmw03rMhtlWnH4iOWyK8a44D+p7/64vJ0cemJiH5V/8lYUtICYsHftVZaykGt2QDQZJnqng6Sbg/LMSVOY/P82ZcfWy0oJ/EFyIYzhO+FTufubIpK4YYhfqmY3KfkSeNM9EGQ4tfNSbGg= ARC-Message-Signature: i=1; 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a=openpgp-sha256; l=2085; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=VT44obotCPUBbxvMUSiK7oaxSibx2Iio+dz6SHI7KhE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmz0ZNBNEoQ6DDVkJpBpWEeTqtGnAT1t6acgVxO fhtJqbI0YSJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZs9GTQAKCRBVnxHm/pHO 9ctxCACdpEZvp66AumYcDrmPBiFVKFQOJonvGKpRxJYoNv7ls/TRuhgqFUep1DT3szRCzS0gubk uXfm/jYLELujibLiWaQeu59MZiGPSe57TDrS5pODkUjd9g3/C5gMCvodV6+178X6JB5XDTeNHlt sQIPRitYy/G75mlZ47EF5P55eqsdPVBGeIHa64xxg2bjuKIGHQM3xY2fCsGgpQCfeUIpnPqLcP3 GJrUDvQlV1VED8gF52EeSBZ+2lp0bd3WWrOD+jURXLBZj8NGsMw5sYfIVMDs13F7qz4qAcY4NAx xIWDYCzYmBFKcbhDsVqkyjv2+qHH5kM0xCDkrqqnfzIvTTbv X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..564b071eb77c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1787,7 +1787,8 @@ pcie0: pcie@1c00000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1795,7 +1796,8 @@ pcie0: pcie@1c00000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1949,7 +1951,8 @@ pcie1: pcie@1c08000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1957,7 +1960,8 @@ pcie1: pcie@1c08000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */