From patchwork Wed Aug 28 15:06:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 824152 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E720188CD3; Wed, 28 Aug 2024 15:07:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724857634; cv=none; b=M9tBsEna8S96undlleeeIySnRgHQzkEwN06cRtMWqUd6vFMhPsh2Mx7ipz/A5fgewsLu6GT8wEjobH+8oG0KHwzK7yMkxouV5XitcD6aLvykUyENcBf+q3KCjYX2A+OHOLIQvHv/EMWRvo3uMdFG8482muuTRwzlC6+4vpzSoMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724857634; c=relaxed/simple; bh=AY5kElfZ7HDWUh1XY4xXIxxSiqg9NsEMxp3JQGCRdGY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LkcXd/IOdWSXlRfMeP7z9Qf18r9+SLKJobDKSNl6t8md970l8717rTs+kry0T6xqiCCMvkrhYVtkVTQc6SqmVdJKSqN7mYTaHmSv44WbZ50OtUMV3PEf0NBjMnWOFiLI378IZkqi4mZ+oBNU1yPMXG6whrxVp56OpzfHWFGeYWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VZlzjUOd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VZlzjUOd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 76E44C4CEC4; Wed, 28 Aug 2024 15:07:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724857634; bh=AY5kElfZ7HDWUh1XY4xXIxxSiqg9NsEMxp3JQGCRdGY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VZlzjUOddAds8Qe1QwxMyIyY69mce4Lz/KiJfHT8JVgpF/eI5uLMbZ3UMKTbYooMA f9QyD5pGqcmm9YPj9wkblFpUAM+mnQu9QEeC921EZ2tff5z482qsriFrl0wHX3KR+S Qll2lF+Qmjq3HnYO6GCGzj3UJNy9EZkWH0buOLryTVTyWBYEVPccsm1fW3FB6qVNYy fOZ0Sak14LSAvRhcwtc7WJn4fugeoAm9SiMfMClFD9OGZRNwIo4+XexQPwW7dsKDim dyDVPZEpodLLQnXTuYHc57sbq5pxv0g1biABIYUDULvOrgRLwTT83tMy1CbWErQzgX xq8HHibnaMLjg== From: Konrad Dybcio Date: Wed, 28 Aug 2024 17:06:54 +0200 Subject: [PATCH v2 1/6] drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-topic-a621-v2-1-1882c6b57432@kernel.org> References: <20240828-topic-a621-v2-0-1882c6b57432@kernel.org> In-Reply-To: <20240828-topic-a621-v2-0-1882c6b57432@kernel.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724857626; l=964; i=konradybcio@kernel.org; s=20230215; h=from:subject:message-id; bh=LKnGEsq0uRQq3Nql0V5gTQSfevwlmeAxbznSDZQfJTg=; b=bNh/7s8qgiCnyg6E10kgxQ9KLEeVVmDUBmE8UE2Fot1oMxwKO1gTcydvsOJdIY8i3R2Bo44Si tcoxfvANwSyDt0ZmFmseeY6RH1MK9mAgH8xlZOA9SYHf7hZ/D7NM36R X-Developer-Key: i=konradybcio@kernel.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio A650 family includes A660 family (they've got a big family), A650 itself, and some more A6XX_GEN3 SKUs, all of which should fall into the same branch of the if-condition. Simplify that. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index cb538a262d1c..6f168f1f32d8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -525,8 +525,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) if (IS_ERR(pdcptr)) goto err; - if (adreno_is_a650(adreno_gpu) || - adreno_is_a660_family(adreno_gpu) || + if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) pdc_in_aop = true; else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu)) From patchwork Wed Aug 28 15:06:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 824151 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F30D1A38E0; Wed, 28 Aug 2024 15:07:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724857641; cv=none; b=ZBca9Niw8+1R102l2c3tQdzZ5MvuJcgXtqn/3480ozhdnadzn1HzyapMu7wUh3WhJNLQgyz3sG+tw95h4Bbidw5EjwONlwDmEeXrd36LGiy36FZdZhAbX+fxiE+4wZ6qnrg+5gbXdiM0vJd18a+bWMNRdi6kvYeJZZENmofwbYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724857641; c=relaxed/simple; bh=fJN/wBB6IdVRV/C/0AvIDADf/BcfqwLjLXBn8yCJISU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K4xGU/YmR4HbyGdKp2gxFb1mQ5Gd0ESERb3OSlpdv2HEJt14fE3nT0xLo6FRJD7+576G3CCzXUBVIgW6sz2VXP+g070x7SYM/gjHpHDtqG15SjdHK9KiWTIR7dGlMTNpPNC9FiIwXW9Mb0DXhCuw2qcmSKksKnhyfl4/WaTWddc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dN9wwMwG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dN9wwMwG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 269C0C4CEC1; Wed, 28 Aug 2024 15:07:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724857641; bh=fJN/wBB6IdVRV/C/0AvIDADf/BcfqwLjLXBn8yCJISU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dN9wwMwG9h3unCF3TjdVyyeL384blKNsEVJpqvsL5VSsqNLJrBdAeN4MDv+ClOmM9 z6/WmgkmMnJB04HKWqsiGmZRr6CL5465uDx1qbBS9G6RZvadCBs7mItKG+Y2t0J1jt thMqabGPvA7FggSdciNrGzeZhHTcO1zU8uk9/Be53VPCypd3zHVZl8QfQg48Q0cC08 CYldVT8RzOX5w6/A4+F6Lt8EtuW2vFVfbwaDbLYLbu+xLtcDUsiKyYvQK958sCn9MO HTxIRy7nIMzKrQ1c8O2PQEN7GVOrdx6a5enk+4sbnT+ULAB1QRKfraYp7ckxzmACDC 7156JPSUdRJWw== From: Konrad Dybcio Date: Wed, 28 Aug 2024 17:06:56 +0200 Subject: [PATCH v2 3/6] drm/msm/a6xx: Store correct gmu_cgc_mode in struct a6xx_info Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-topic-a621-v2-3-1882c6b57432@kernel.org> References: <20240828-topic-a621-v2-0-1882c6b57432@kernel.org> In-Reply-To: <20240828-topic-a621-v2-0-1882c6b57432@kernel.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724857626; l=5876; i=konradybcio@kernel.org; s=20230215; h=from:subject:message-id; bh=HDul3oea/s0VFDTA8cmBURLRDU8BwSstHumQgxqDetA=; b=QHUAqqyPCivttCwMg+fGojXhiU9T0ZYPubqeEOJlIzWyAbvMfLn5G1+ArhzvbbfDR6Fca8br0 x4MctrDUGI3BtWFjiv+pR0G6TCN6AGeghE/2Wfy9kUf9isWyb8OcyK4 X-Developer-Key: i=konradybcio@kernel.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Store the correct values that we happen to have for some A7xx SKUs in the GPU info struct and fill out the missing information for A6xx GPUs based on downstream kernel information. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 1ea535960f32..6cd73abd95d4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -636,6 +636,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a612_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00080000, }, /* @@ -668,6 +669,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a615_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00180000, }, .speedbins = ADRENO_SPEEDBINS( @@ -691,6 +693,7 @@ static const struct adreno_info a6xx_gpus[] = { .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .protect = &a630_protect, + .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00180000, }, .speedbins = ADRENO_SPEEDBINS( @@ -714,6 +717,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a615_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00018000, }, .speedbins = ADRENO_SPEEDBINS( @@ -737,6 +741,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a615_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00018000, }, .speedbins = ADRENO_SPEEDBINS( @@ -760,6 +765,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a615_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00000222, .prim_fifo_threshold = 0x00018000, }, .speedbins = ADRENO_SPEEDBINS( @@ -788,6 +794,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a630_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00180000, }, }, { @@ -806,6 +813,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a640_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00180000, }, .speedbins = ADRENO_SPEEDBINS( @@ -829,6 +837,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a650_hwcg, .protect = &a650_protect, + .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00300200, }, .address_space_size = SZ_16G, @@ -855,6 +864,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a660_hwcg, .protect = &a660_protect, + .gmu_cgc_mode = 0x00020000, .prim_fifo_threshold = 0x00300200, }, .address_space_size = SZ_16G, @@ -874,6 +884,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a660_hwcg, .protect = &a660_protect, + .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00200200, }, .address_space_size = SZ_16G, @@ -899,6 +910,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a640_hwcg, .protect = &a630_protect, + .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x00200200, }, }, { @@ -917,6 +929,7 @@ static const struct adreno_info a6xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a690_hwcg, .protect = &a690_protect, + .gmu_cgc_mode = 0x00020200, .prim_fifo_threshold = 0x00800200, }, .address_space_size = SZ_16G, @@ -1178,6 +1191,7 @@ static const struct adreno_info a7xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a702_hwcg, .protect = &a650_protect, + .gmu_cgc_mode = 0x00020202, .prim_fifo_threshold = 0x0000c000, }, .speedbins = ADRENO_SPEEDBINS( @@ -1202,6 +1216,7 @@ static const struct adreno_info a7xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a730_hwcg, .protect = &a730_protect, + .gmu_cgc_mode = 0x00020000, }, .address_space_size = SZ_16G, }, { @@ -1221,6 +1236,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .gmu_chipid = 0x7020100, + .gmu_cgc_mode = 0x00020202, }, .address_space_size = SZ_16G, }, { @@ -1239,6 +1255,7 @@ static const struct adreno_info a7xx_gpus[] = { .hwcg = a740_hwcg, .protect = &a730_protect, .gmu_chipid = 0x7050001, + .gmu_cgc_mode = 0x00020202, }, .address_space_size = SZ_256G, }, { @@ -1257,6 +1274,7 @@ static const struct adreno_info a7xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .protect = &a730_protect, .gmu_chipid = 0x7090100, + .gmu_cgc_mode = 0x00020202, }, .address_space_size = SZ_16G, } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index bc37bd8c7f65..0fb7febf70e7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -22,6 +22,7 @@ struct a6xx_info { const struct adreno_reglist *hwcg; const struct adreno_protect *protect; u32 gmu_chipid; + u32 gmu_cgc_mode; u32 prim_fifo_threshold; }; From patchwork Wed Aug 28 15:06:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 824150 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC3831DFCF; Wed, 28 Aug 2024 15:07:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724857649; cv=none; b=ZimgqFe8poC2eepl/YuwiVqzpXXZivfkSlEjMssgo/+lguZBjcWX5I+FuLfo/Bv5GNLpPEa4FcM5ZHeE1y8uWKkpX2F2X6fyr4LEDjtI3Heeo8gLVbPYKaCVIwmIApdKg8J+aRKJmyydK86YOP7nBS7nDYpIERlqbinvKVAV23Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724857649; c=relaxed/simple; bh=KzCV689rRHj9LTg/b6rrYCx7sCt+nSxr+RJmwcuxtlw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fDTl/4Gu5DLEZTY+YCn2RuDbMZ6Qu0yMow9mn8HuZHKQ1Hv7V70Cs6g9RPzUQa13uCbc9FojcrPllcfCqTZRenSmsjz2jcPlV6ouBeTZQSJMfX4CfzTs5TL52NaKLRfclZvfbLW+eWY3dJ2RNwJ5c/32DqgjaBhAdQ4iTpUVTzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eL4JVlZs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eL4JVlZs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B9CCC4CECB; Wed, 28 Aug 2024 15:07:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724857649; bh=KzCV689rRHj9LTg/b6rrYCx7sCt+nSxr+RJmwcuxtlw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=eL4JVlZs+xnXJzFZJPl2ctO0iGzMSa1PtOBVrROwbuMBk8IRynYeovRNi4e8O3otE t4RpcFOEDLep5RYn1oL3ppCKuGd96+K2kyLhnyqmVenAh8fykXBDWsT6gEP5uE14Mc fR+dpPmaFMZhSyF9DJNJgrymolBqLtLvrTJ6rIQC5wFhfY6FOpno3Gp0cEH8qO295n HnT9caG5T3VdBLIlCzRkVE62NvR1qH+nRbKDX1yGg7FJX7rBb/fLslxB4Q/Ir5/Ad8 diqHiAKtEXdffRSr2t/n0VDGtREgPwxVyiHPALkhME9+aj0z5Jjg3Jr2XgwzUx5+DP 3r5tVxfohmCdg== From: Konrad Dybcio Date: Wed, 28 Aug 2024 17:06:58 +0200 Subject: [PATCH v2 5/6] drm/msm/a6xx: Set GMU CGC properties on a6xx too Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240828-topic-a621-v2-5-1882c6b57432@kernel.org> References: <20240828-topic-a621-v2-0-1882c6b57432@kernel.org> In-Reply-To: <20240828-topic-a621-v2-0-1882c6b57432@kernel.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724857626; l=3400; i=konradybcio@kernel.org; s=20230215; h=from:subject:message-id; bh=nN1jIdmgpJFQCKZJ2uyox0t9bNkXH+G8RpT+oJBTlJQ=; b=Zm/qGzoLNLIItno0Ae/hVTOEfKCnrnDl7lvXipzVsVPrU/nsK8wN8IZSoKMufOJCFNJgE5oQY 8GzIVsU06quDxfmeGHbGhJO83y+C0rVNt7gmYFu4ptbSYcTNjiEUfIp X-Developer-Key: i=konradybcio@kernel.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio This was apparently never done before.. Program the expected values. This also gets rid of sneakily setting that register through the HWCG reg list on A690. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 - drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++++++++++-------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +++++++- 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 6cd73abd95d4..deee0b686962 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -448,7 +448,6 @@ static const struct adreno_reglist a690_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200}, {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111}, {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555}, {} diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 871452daa189..33a319f7d200 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -402,6 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) struct a6xx_gmu *gmu = &a6xx_gpu->gmu; const struct adreno_reglist *reg; unsigned int i; + u32 cgc_delay, cgc_hyst; u32 val, clock_cntl_on; if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) @@ -416,14 +417,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) else clock_cntl_on = 0x8aa8aa82; - if (adreno_is_a7xx(adreno_gpu)) { - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, - state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, - state ? 0x10111 : 0); - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, - state ? 0x5555 : 0); - } + cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; + cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; + + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, + state ? cgc_delay : 0); + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, + state ? cgc_hyst : 0); if (!adreno_gpu->info->a6xx->hwcg) { gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 1ab523a163a0..26972b2cc896 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -433,7 +433,13 @@ static inline int adreno_is_a610_family(const struct adreno_gpu *gpu) return adreno_is_a610(gpu) || adreno_is_a702(gpu); } -/* check for a615, a616, a618, a619 or any a630 derivatives */ +/* TODO: 615/616 */ +static inline int adreno_is_a615_family(const struct adreno_gpu *gpu) +{ + return adreno_is_a618(gpu) || + adreno_is_a619(gpu); +} + static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info))