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Signed-off-by: Raviteja Laggyshetty --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 21dae0b92819..de2c59ddc94a 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -33,6 +33,8 @@ properties: - qcom,sm6375-cpucp-l3 - qcom,sm8250-epss-l3 - qcom,sm8350-epss-l3 + - qcom,sa8775p-epss-l3-cl0 + - qcom,sa8775p-epss-l3-cl1 - const: qcom,epss-l3 reg: From patchwork Wed Sep 4 17:12:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 825806 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C2831E0B99; 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Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index e8dbc8d820a6..06bf2ba556b8 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -3777,6 +3778,15 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,sa8775p-epss-l3-cl0", + "qcom,epss-l3"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sa8775p-cpufreq-epss", "qcom,cpufreq-epss"; @@ -3790,6 +3800,15 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,sa8775p-epss-l3-cl1", + "qcom,epss-l3"; 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Wed, 4 Sep 2024 17:12:47 GMT Received: from 0e63825dadb5.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Sep 2024 10:12:43 -0700 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Andy Shevchenko , Sibi Sankar , , , , Subject: [PATCH 3/3] interconnect: qcom: Add EPSS L3 support on SA8775P Date: Wed, 4 Sep 2024 17:12:09 +0000 Message-ID: <20240904171209.29120-4-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240904171209.29120-1-quic_rlaggysh@quicinc.com> References: <20240904171209.29120-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nls1X0YWTswSdAw6t14ShnQQ4ROnKrP_ X-Proofpoint-ORIG-GUID: nls1X0YWTswSdAw6t14ShnQQ4ROnKrP_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-04_15,2024-09-04_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2409040131 Add Epoch Subsystem (EPSS) L3 interconnect provider support on SA8775P SoCs. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/osm-l3.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 61a8695a9adc..e97d61a9d8d7 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -74,6 +75,11 @@ enum { OSM_L3_SLAVE_NODE, }; +enum { + EPSS_L3_CL1_MASTER_NODE = 20000, + EPSS_L3_CL1_SLAVE_NODE, +}; + #define DEFINE_QNODE(_name, _id, _buswidth, ...) \ static const struct qcom_osm_l3_node _name = { \ .name = #_name, \ @@ -99,6 +105,15 @@ static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, }; +DEFINE_QNODE(epss_l3_cl1_master, EPSS_L3_CL1_MASTER_NODE, 32, + EPSS_L3_CL1_SLAVE_NODE); +DEFINE_QNODE(epss_l3_cl1_slave, EPSS_L3_CL1_SLAVE_NODE, 32); + +static const struct qcom_osm_l3_node * const epss_l3_cl1_nodes[] = { + [MASTER_EPSS_L3_APPS] = &epss_l3_cl1_master, + [SLAVE_EPSS_L3_SHARED] = &epss_l3_cl1_slave, +}; + static const struct qcom_osm_l3_desc osm_l3 = { .nodes = osm_l3_nodes, .num_nodes = ARRAY_SIZE(osm_l3_nodes), @@ -115,6 +130,14 @@ static const struct qcom_osm_l3_desc epss_l3_perf_state = { .reg_perf_state = EPSS_REG_PERF_STATE, }; +static const struct qcom_osm_l3_desc epss_l3_cl1_perf_state = { + .nodes = epss_l3_cl1_nodes, + .num_nodes = ARRAY_SIZE(epss_l3_cl1_nodes), + .lut_row_size = EPSS_LUT_ROW_SIZE, + .reg_freq_lut = EPSS_REG_FREQ_LUT, + .reg_perf_state = EPSS_REG_PERF_STATE, +}; + static const struct qcom_osm_l3_desc epss_l3_l3_vote = { .nodes = epss_l3_nodes, .num_nodes = ARRAY_SIZE(epss_l3_nodes), @@ -284,6 +307,10 @@ static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, + { .compatible = "qcom,sa8775p-epss-l3-cl0", + .data = &epss_l3_perf_state }, + { .compatible = "qcom,sa8775p-epss-l3-cl1", + .data = &epss_l3_cl1_perf_state }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match);