From patchwork Fri Nov 15 12:15:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 179491 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp12371686ilf; Fri, 15 Nov 2019 04:18:02 -0800 (PST) X-Google-Smtp-Source: APXvYqwisUCvIXvWegz5rFnHpXs4wYMMEbcv3tymLtF/P3yeEFSN2LvejqgGceJJesMFmNMe7erR X-Received: by 2002:adf:db4e:: with SMTP id f14mr14070754wrj.257.1573820282174; Fri, 15 Nov 2019 04:18:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573820282; cv=none; d=google.com; s=arc-20160816; b=FJ1uO0DmJO50XLKxoHWDfFW0gxyWbK6s5SdqrTqwSBiarL+xhIJB+C6UxpGmQ9DTOB KoLlj1AvbpZ/j5zzHiDLGLLnr12bfjvQkukiL7Sv94QStJNdoOCgcB2LT3nVw/2WAXlH EaHmXATmdfvl20QYJayy8uQGPYOVj0yXpd7rvJcpA1yW/GUuo8Tm8RvJGXrATQzm3bXB AEd+/uOwNI+/srkPueuK/zFGoNj9dmOhG5RgvacsK6Hp+c8TIiwWNHLKHPGaK4Z/z3cc O8THyRwZlyqCeS+dCJprDcOqVepNthlNpuFdjluPK06NlpXAaEqUl9pWeX6o/HALaCKL t24w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GzXbFQkPrKMVsons+QpYWmVJ2fxp7Rx5snNgvCvieVY=; b=b40Ik4dd9tkWOwLJZ1dbcXzHAl5a2HLJgan9EybC2/Q9ulNemKOOotmSNr0zFWsyTx 03CQUOReR41+tk9PLoIAW4LcmaeezcX+4oRdafiCwFEgMpwaXi3nGzKiq8FifEwzcAjW pgZwbrUUdQQkZyxUkwFNsczjt49Pp670MrQ3bQ4I6bVj6lyItB20ByaVS7QrFk7DJuaN h2VCDk6T4XXDwuuyyy7FyH/hP0GN3tBdpu29veN5Jdd4ESQSv6dHPiaNWtj4kZ774p/A xY42GAHk+PyZ6EJGI+L90XLENaE0CFtbTUcRjNZGldOim02hMjoYBurx9Z4p+P2R06wW gZWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="yG/n0v4M"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p92si6451481edd.407.2019.11.15.04.18.01; Fri, 15 Nov 2019 04:18:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="yG/n0v4M"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727483AbfKOMSB (ORCPT + 8 others); Fri, 15 Nov 2019 07:18:01 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40732 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727413AbfKOMSB (ORCPT ); Fri, 15 Nov 2019 07:18:01 -0500 Received: by mail-lj1-f194.google.com with SMTP id q2so10483456ljg.7 for ; Fri, 15 Nov 2019 04:17:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GzXbFQkPrKMVsons+QpYWmVJ2fxp7Rx5snNgvCvieVY=; b=yG/n0v4MhRYVnb5vUXGkRi6oDV6K/u1lsPBGqqDtMe9eQPej0mbaUgAxww7zpeDK3V 0yAsmiPtDAfY89uW8P19F6ARJ03M6WTr8BJ/Qgo82odDvha5POqGBBtsEFiek1YoOUMs +Rgk4MvL/tX7GyolCqh71czAJXhVeYhVCzX8tS6Ix5JvtzkB7/oxMFEz4vgV4zVHIx8D 79iMkpCODZXATEcqCTGdIw9ICPeSxz4GUmIX5oFsZ1CuanHEQtNuISSmvmoK7zyNASvH aKY2eXwIDPXiv5Yn2cjuwUSmX0z/mLlKFwd8eRcaH3DBDOEQ4r3xjZqdVZN2//o/jQLk oNsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GzXbFQkPrKMVsons+QpYWmVJ2fxp7Rx5snNgvCvieVY=; b=FvUwF7dy8XD6JXx6qzSOeL+nCx5TLbyvKZCuDOgKvLcyAOw6B26pX66SlHth9kYdhw cAaQ9D4ULRw3N4fHi7zh+toNaZ48GEw7kCCsCQJrkCs2C67Deb4e435s3LXU/jrppyEU 3ZiOULVfM6h3OTUOlySKN2sjlIipftAL2Zw+Tf0nw+oEXkTV4sQQ1Ooy7jWQawmrZy+8 SepToW2T/v65h33GoEM2nCSexVKo8QK5HgHoRqjTHOdjFh5V2z1YuO1Sg7dJgP7PGaDt adhF4zr15MNk3p7ls7QLUCr5Ndt/aBd8WZsLr+EsYf65GeG4b+zDAeUD1VKx2GxshHqK KvBw== X-Gm-Message-State: APjAAAXEos50KIuRVTu85oH0LC9FrIIfaFNmdEiPQjtS6lRP0If7n+do HYbnRUpaParRj0lDmiGn4YhoCw== X-Received: by 2002:a2e:9659:: with SMTP id z25mr11200659ljh.132.1573820279064; Fri, 15 Nov 2019 04:17:59 -0800 (PST) Received: from centauri.lan (ua-84-217-220-205.bbcust.telenor.se. [84.217.220.205]) by smtp.gmail.com with ESMTPSA id c16sm331070lfp.93.2019.11.15.04.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 04:17:58 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, sboyd@kernel.org, vireshk@kernel.org, ulf.hansson@linaro.org, Niklas Cassel , Jorge Ramirez-Ortiz , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/5] arm64: dts: qcom: qcs404: Add CPR and populate OPP table Date: Fri, 15 Nov 2019 13:15:40 +0100 Message-Id: <20191115121544.2339036-4-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191115121544.2339036-1-niklas.cassel@linaro.org> References: <20191115121544.2339036-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add CPR and populate OPP table. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 132 +++++++++++++++++++++++++-- 1 file changed, 124 insertions(+), 8 deletions(-) -- 2.23.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d03782e7bc11..30b9c7f8f200 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -44,7 +44,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; CPU1: cpu@101 { @@ -57,7 +58,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; CPU2: cpu@102 { @@ -70,7 +72,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; CPU3: cpu@103 { @@ -83,7 +86,8 @@ #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&pms405_s3>; + power-domains = <&cpr>; + power-domain-names = "cpr"; }; L2_0: l2-cache { @@ -107,20 +111,37 @@ }; cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2-kryo-cpu"; opp-shared; opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; - opp-microvolt = <1224000 1224000 1224000>; + required-opps = <&cpr_opp1>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-microvolt = <1288000 1288000 1288000>; + required-opps = <&cpr_opp2>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-microvolt = <1384000 1384000 1384000>; + required-opps = <&cpr_opp3>; + }; + }; + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cpr_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cpr_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <3>; }; }; @@ -310,6 +331,62 @@ tsens_caldata: caldata@d0 { reg = <0x1f8 0x14>; }; + cpr_efuse_speedbin: speedbin@13c { + reg = <0x13c 0x4>; + bits = <2 3>; + }; + cpr_efuse_quot_offset1: qoffset1@231 { + reg = <0x231 0x4>; + bits = <4 7>; + }; + cpr_efuse_quot_offset2: qoffset2@232 { + reg = <0x232 0x4>; + bits = <3 7>; + }; + cpr_efuse_quot_offset3: qoffset3@233 { + reg = <0x233 0x4>; + bits = <2 7>; + }; + cpr_efuse_init_voltage1: ivoltage1@229 { + reg = <0x229 0x4>; + bits = <4 6>; + }; + cpr_efuse_init_voltage2: ivoltage2@22a { + reg = <0x22a 0x4>; + bits = <2 6>; + }; + cpr_efuse_init_voltage3: ivoltage3@22b { + reg = <0x22b 0x4>; + bits = <0 6>; + }; + cpr_efuse_quot1: quot1@22b { + reg = <0x22b 0x4>; + bits = <6 12>; + }; + cpr_efuse_quot2: quot2@22d { + reg = <0x22d 0x4>; + bits = <2 12>; + }; + cpr_efuse_quot3: quot3@230 { + reg = <0x230 0x4>; + bits = <0 12>; + }; + cpr_efuse_ring1: ring1@228 { + reg = <0x228 0x4>; + bits = <0 3>; + }; + cpr_efuse_ring2: ring2@228 { + reg = <0x228 0x4>; + bits = <4 3>; + }; + cpr_efuse_ring3: ring3@229 { + reg = <0x229 0x4>; + bits = <0 3>; + }; + cpr_efuse_revision: revision@218 { + reg = <0x218 0x4>; + bits = <3 3>; + }; }; rng: rng@e3000 { @@ -952,6 +1029,45 @@ clocks = <&sleep_clk>; }; + cpr: power-controller@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>;