From patchwork Fri Nov 15 16:28:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 179505 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp12679764ilf; Fri, 15 Nov 2019 08:29:33 -0800 (PST) X-Google-Smtp-Source: APXvYqyP9trBxKMKDfPrPhmtnhce9KSSxlohVxwRPx11WLFTCArs+q2RXVagod9rz6hySsKYwdNq X-Received: by 2002:a17:906:4e48:: with SMTP id g8mr1963887ejw.67.1573835372927; Fri, 15 Nov 2019 08:29:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573835372; cv=none; d=google.com; s=arc-20160816; b=YS9ejObbB5SKQq4FtsV0iqVjWHdZlyhsSp+5mitTBj5hIo+gr/eBZ//DJp5YDOT86F Jn+8bRcJeB3GPQ643JjXZrFRAA2ZbyI2WLZ0IMwAMMRUSDF2+VtN8vA3sucM5Z+89aiv 8VgjTjUlv4l5jMVY30GSaP6Oq/AKcCnLT8bCKTtaZC+HyMi+CwD464eUfThSlYj5F5hp 5AkVU/np2xYItQt7rI+UOdxOzdLFYBZaTATywT5riUtvs2JfcPSPiQJuobRoG73ErAW0 KK1ZYPSKw5h3I+uZUSNd6Ko8QBY6DVyO4RMNjrhEldrbX8DMgyxUEQvqzlRXiVUktU0/ aFwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Zgqr5BSa48TxbTYLKMugnan1gSsGxic61qyv50u9LdE=; b=f3P6w9N420huuhVHuEW1Ms/X71MNgI9lXeT4b1sD7Ylp2rexfEoVqMvo3Syov/lhEE lipakmxmpTBemMPt1HSO5djzGNhLHSP/RPO5h1eXAigMFUzKyqnFlZ8UPJWE74sK6Dz0 SVZea4OXseZNW886lXM89Of9QXdjTSY994rtWdICwFeLTiu/Jvi+9PV1M4gEKrLDs3+a YyR3CJ16t0N4nwUXLPM7vdZV0TPRgQCAhBijV9LTSW3T+pfXa0gSKWZScBlbC8brAIdz kWPHk3CC0EeKn6NPxbXAsScHsdx6qnhaylUAZbB4zAU3Zu+yaWWeibSBIb+brGB72TrQ H10Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bDwt676Z; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g24si6530304edv.239.2019.11.15.08.29.32; Fri, 15 Nov 2019 08:29:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bDwt676Z; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727667AbfKOQ3c (ORCPT + 8 others); Fri, 15 Nov 2019 11:29:32 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:45523 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727531AbfKOQ3b (ORCPT ); Fri, 15 Nov 2019 11:29:31 -0500 Received: by mail-pg1-f195.google.com with SMTP id k1so4925886pgg.12 for ; Fri, 15 Nov 2019 08:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zgqr5BSa48TxbTYLKMugnan1gSsGxic61qyv50u9LdE=; b=bDwt676ZHNZP4/OhuT46sME9F112AckEbHsVx2sEy47mcfLzQmbjlhL11cuUcDdaeM OiEVSvny1sL90sQ5WiTEfn2etLoNfRPQNv1Y2EB98oPolXEc9Z0/lo1M/Du5SZBFrzSg 6DefqqjTcwNku8DNOMJAoz/zgNAgj5C/U/XuvSRUEF8au2NcCv1SpQ2fuWCSbNLFNTx5 xAsoZSzAIV+HqrUGehN96r1kBlNsffXqGaD5fOs6JgTM2ZAfrlc+3nHLyX0aEd7NOiyL pxN2/U0DzY/jFCgrILutKYiJJky3xQi4Z5jKc990EwebB/EGdzxJSILWp9P5/ZFv5YXN r1rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Zgqr5BSa48TxbTYLKMugnan1gSsGxic61qyv50u9LdE=; b=I5oIkpI8So28KAd/UL0zYhTJuCfPdb/3qG4TCFm1mqPel93+1/yQtuwr4/NEnTfsVX pEBjNTgjvnlqpDKF8Z6sAuYQvcBeogHfhs91QduPmBOXS2e3jGlcyKg1XRBxZHyj92id dDpphLvmqE23M4UKiNYL/uyuHGjmmOn3Zi1oFbqxIHP4zdbSWE/b4Q0/XNw3S3bz4Tw8 I9aotJEODYleLNn8J7oFq3n+kHEW311UNx6PwmJRiewQRvZ6hAA/FveKaEKY3bv2LLNu TobgAo401DNxjy3B66SMHbxs6q9++Zt3auvwy7/pKDRtWSyjlVAf6KCBbK8jOfm9NYyF uPGQ== X-Gm-Message-State: APjAAAVd3Pt+U5XyzPs0Y/sCNdCgtgRTuOaK8n0KT8xLUpc5z0XCYPWI 0qFJcWpMuy5VmRKAJS5DtWdy X-Received: by 2002:a63:715d:: with SMTP id b29mr17081495pgn.369.1573835370908; Fri, 15 Nov 2019 08:29:30 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6183:6d55:8418:2bbc:e6d8:2b4]) by smtp.gmail.com with ESMTPSA id y24sm12295288pfr.116.2019.11.15.08.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 08:29:30 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, fisher.cheng@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH v7 3/7] dt-bindings: clock: Add devicetree binding for BM1880 SoC Date: Fri, 15 Nov 2019 21:58:57 +0530 Message-Id: <20191115162901.17456-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191115162901.17456-1-manivannan.sadhasivam@linaro.org> References: <20191115162901.17456-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add YAML devicetree binding for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../bindings/clock/bitmain,bm1880-clk.yaml | 76 +++++++++++++++++ include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml create mode 100644 include/dt-bindings/clock/bm1880-clock.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml new file mode 100644 index 000000000000..e63827399c1a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 Clock Controller + +maintainers: + - Manivannan Sadhasivam + +description: | + The Bitmain BM1880 clock controller generates and supplies clock to + various peripherals within the SoC. + + This binding uses common clock bindings + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + const: bitmain,bm1880-clk + + reg: + items: + - description: pll registers + - description: system registers + + reg-names: + items: + - const: pll + - const: sys + + clocks: + maxItems: 1 + + clock-names: + const: osc + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + + # Example UART controller node that consumes clock generated by the clock controller: + - | + uart0: serial@58018000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk 45>, <&clk 46>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <0 9 4>; + reg-shift = <2>; + reg-io-width = <4>; + }; + +... diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h new file mode 100644 index 000000000000..b46732361b25 --- /dev/null +++ b/include/dt-bindings/clock/bm1880-clock.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Device Tree binding constants for Bitmain BM1880 SoC + * + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_BM1880_H +#define __DT_BINDINGS_CLOCK_BM1880_H + +#define BM1880_CLK_OSC 0 +#define BM1880_CLK_MPLL 1 +#define BM1880_CLK_SPLL 2 +#define BM1880_CLK_FPLL 3 +#define BM1880_CLK_DDRPLL 4 +#define BM1880_CLK_A53 5 +#define BM1880_CLK_50M_A53 6 +#define BM1880_CLK_AHB_ROM 7 +#define BM1880_CLK_AXI_SRAM 8 +#define BM1880_CLK_DDR_AXI 9 +#define BM1880_CLK_EFUSE 10 +#define BM1880_CLK_APB_EFUSE 11 +#define BM1880_CLK_AXI5_EMMC 12 +#define BM1880_CLK_EMMC 13 +#define BM1880_CLK_100K_EMMC 14 +#define BM1880_CLK_AXI5_SD 15 +#define BM1880_CLK_SD 16 +#define BM1880_CLK_100K_SD 17 +#define BM1880_CLK_500M_ETH0 18 +#define BM1880_CLK_AXI4_ETH0 19 +#define BM1880_CLK_500M_ETH1 20 +#define BM1880_CLK_AXI4_ETH1 21 +#define BM1880_CLK_AXI1_GDMA 22 +#define BM1880_CLK_APB_GPIO 23 +#define BM1880_CLK_APB_GPIO_INTR 24 +#define BM1880_CLK_GPIO_DB 25 +#define BM1880_CLK_AXI1_MINER 26 +#define BM1880_CLK_AHB_SF 27 +#define BM1880_CLK_SDMA_AXI 28 +#define BM1880_CLK_SDMA_AUD 29 +#define BM1880_CLK_APB_I2C 30 +#define BM1880_CLK_APB_WDT 31 +#define BM1880_CLK_APB_JPEG 32 +#define BM1880_CLK_JPEG_AXI 33 +#define BM1880_CLK_AXI5_NF 34 +#define BM1880_CLK_APB_NF 35 +#define BM1880_CLK_NF 36 +#define BM1880_CLK_APB_PWM 37 +#define BM1880_CLK_DIV_0_RV 38 +#define BM1880_CLK_DIV_1_RV 39 +#define BM1880_CLK_MUX_RV 40 +#define BM1880_CLK_RV 41 +#define BM1880_CLK_APB_SPI 42 +#define BM1880_CLK_TPU_AXI 43 +#define BM1880_CLK_DIV_UART_500M 44 +#define BM1880_CLK_UART_500M 45 +#define BM1880_CLK_APB_UART 46 +#define BM1880_CLK_APB_I2S 47 +#define BM1880_CLK_AXI4_USB 48 +#define BM1880_CLK_APB_USB 49 +#define BM1880_CLK_125M_USB 50 +#define BM1880_CLK_33K_USB 51 +#define BM1880_CLK_DIV_12M_USB 52 +#define BM1880_CLK_12M_USB 53 +#define BM1880_CLK_APB_VIDEO 54 +#define BM1880_CLK_VIDEO_AXI 55 +#define BM1880_CLK_VPP_AXI 56 +#define BM1880_CLK_APB_VPP 57 +#define BM1880_CLK_DIV_0_AXI1 58 +#define BM1880_CLK_DIV_1_AXI1 59 +#define BM1880_CLK_AXI1 60 +#define BM1880_CLK_AXI2 61 +#define BM1880_CLK_AXI3 62 +#define BM1880_CLK_AXI4 63 +#define BM1880_CLK_AXI5 64 +#define BM1880_CLK_DIV_0_AXI6 65 +#define BM1880_CLK_DIV_1_AXI6 66 +#define BM1880_CLK_MUX_AXI6 67 +#define BM1880_CLK_AXI6 68 +#define BM1880_NR_CLKS 69 + +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ From patchwork Fri Nov 15 16:28:58 2019 Content-Type: text/plain; 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Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index d65453f99a99..8471662413da 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -4,6 +4,7 @@ * Author: Manivannan Sadhasivam */ +#include #include #include @@ -66,6 +67,12 @@ ; }; + osc: osc { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -94,6 +101,15 @@ reg = <0x400 0x120>; }; + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + rst: reset-controller@c00 { compatible = "bitmain,bm1880-reset"; reg = <0xc00 0x8>; From patchwork Fri Nov 15 16:28:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 179507 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp12680072ilf; Fri, 15 Nov 2019 08:29:47 -0800 (PST) X-Google-Smtp-Source: APXvYqwCkNJSlIPP47lFsx9ZTBbP3EABDjWO5l9OPB2gfEcRRtqgMnPT44I6jTG8VFLiQb6vS18B X-Received: by 2002:a17:906:5502:: with SMTP id r2mr2095142ejp.3.1573835387265; Fri, 15 Nov 2019 08:29:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573835387; cv=none; d=google.com; s=arc-20160816; b=xG4vo5rcYP1EeH7JDzWyqLfRTRCg++5Il+Q2CWpVGY7LR4qiKcji4UIp3Etz9PQZqz oS9vlsVhMiB8v7xmJIJFoDRDILbBaPL4T03B0L4UghFdQIxRAzQeRomNG+A8kpkSeCJ+ xUXmNDa13tf4XdXX7lCQHGkrjS+yHHyMly/7aX+TRYI48nIk8l59M2dHGhHgVGbuuChE Io/FwBu6mKFwcK3fr7PXLJfJQbKGp5rVQeP94DofvNYDq1AEeyvE1glBrXEIaoqiIshy FRNW2KKYrcN3xVk+W1jLgGW1oykf7OAxrSiRsCD2OpfPchIwW8EnvUXmnjmcmwtlLui4 qhTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kgB5pCuOS2QWyyNQUlCeMbbF7mRF+VE6sHHJ2GG7b1c=; b=AZPi65W9XU5vE+VC6DZXt5Pq5LXqVNQP4PgKAQoJcLicBm1PSFbE9HfRd8GwISVilh N4PNnjS3K5/8dliIFYsESwkcXmHv34ECGM5A/gYy/YXmph3/53QQeKDnnRuuA3M8fJ7C jShxlt718Yxd+beol42rxYqJalpItCUxhgA2vk6iEthMLlyzQjaEyH0CtWmt0Hzu1a1W RtNs28jC/6s/QmqRpmjC6J7WAfrq+HhdxI+9aAnKVgPo1NYntpYB6vZSAfvcJ+nz0UBT 4mFIZjz+7Cbmv3n1gCEnu28/l0RwAeUOaU04SB5h6m1vzBg6+1lJQgmTE7vULgizbNA/ 7Vyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DPCw4Yfm; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts | 9 --------- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts index 3e8c70778e24..7a2c7f9c2660 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts +++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts @@ -49,12 +49,6 @@ reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB }; - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <500000000>; - #clock-cells = <0>; - }; - soc { gpio0: gpio@50027000 { porta: gpio-controller@0 { @@ -173,21 +167,18 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &uart2 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_default>; }; diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index 8471662413da..fa6e6905f588 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -174,6 +174,9 @@ uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -184,6 +187,9 @@ uart1: serial@5801A000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801a000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -194,6 +200,9 @@ uart2: serial@5801C000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801c000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -204,6 +213,9 @@ uart3: serial@5801E000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801e000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>;