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a=openpgp-sha256; l=1917; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=4jg/7UcRjOk5Aa8PYPjFu4S06h+6mU5cJuLQp0/H3QE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBm3J/xHjCopDQPiYASMPf01hRA68yz6IxH2T4eL eC6cfgV0lyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZtyf8QAKCRCLPIo+Aiko 1Q9uB/0ag1ZGlUF+StHNMO5RSRr8jbA8TML029hF2MBiqykw2lDs8s8+suyKE9WYe4KswcqvVgN 4bLu2KGe0WcbuoHG/wD/0SUKHISGgj5Anq4r23QlfVb2bxp4eyH5lJGlFpX19EANfZl3+VaMWyY 9heRsRGZ3eCyB+Lbo0qZGCWzU7Stf3ugs2tVW/KpgpE+RU64fzV2B+hAZRoqrH/SSzcvZ0qR1tL NzKtpFdruw/1UcKNwMKoQJV9xo58sMiOz6W2+uJB9Md+VVFGfmCFmjQ1uK0VdwVnpwVVxQgT9Jo vCdHx4iMWcz8ZKPEMLUY7mTi4Uw0ad36gbt2aAtXUl6jX6xT X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The Qualcomm SDM630 / SDM660 platform requires the same kind of workaround as MSM8998: some IOMMUs have context banks reserved by firmware / TZ, touching those banks resets the board. Apply the num_context_bank workaround to those two SMMU devices in order to allow them to be used by Linux. Fixes: b812834b5329 ("iommu: arm-smmu-qcom: Add sdm630/msm8998 compatibles for qcom quirks") Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 087fb4f6f4d3..13a3e3585c89 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -288,6 +288,12 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) */ if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && smmu->num_context_banks == 13) smmu->num_context_banks = 12; + else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) { + if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */ + smmu->num_context_banks = 7; + else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */ + smmu->num_context_banks = 13; + } /* * Some platforms support more than the Arm SMMU architected maximum of @@ -350,6 +356,11 @@ static int qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device *smmu) /* Support for 16K pages is advertised on some SoCs, but it doesn't seem to work */ smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K; + /* TZ protects several last context banks, hide them from Linux */ + if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") && + smmu->num_context_banks == 5) + smmu->num_context_banks = 2; + return 0; } From patchwork Sat Sep 7 18:48:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 826309 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE4CE16191B for ; Sat, 7 Sep 2024 18:48:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 07 Sep 2024 11:48:20 -0700 (PDT) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2f75c0b1af3sm2271861fa.129.2024.09.07.11.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Sep 2024 11:48:20 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 07 Sep 2024 21:48:13 +0300 Subject: [PATCH 2/7] arm64: dts: qcom: sdm630: enable GPU SMMU and GPUCC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240907-sdm660-wifi-v1-2-e316055142f8@linaro.org> References: <20240907-sdm660-wifi-v1-0-e316055142f8@linaro.org> In-Reply-To: <20240907-sdm660-wifi-v1-0-e316055142f8@linaro.org> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , AngeloGioacchino Del Regno , Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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Enable GPU SMMU and GPU clock controller. GPU should be enabled for target devices that have ZAP shader blob. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index c8da5cb8d04e..40ad99d75738 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1186,8 +1186,6 @@ kgsl_smmu: iommu@5040000 { , , ; - - status = "disabled"; }; gpucc: clock-controller@5065000 { @@ -1203,7 +1201,6 @@ gpucc: clock-controller@5065000 { clock-names = "xo", "gcc_gpu_gpll0_clk", "gcc_gpu_gpll0_div_clk"; - status = "disabled"; }; lpass_smmu: iommu@5100000 { From patchwork Sat Sep 7 18:48:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 826491 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF20B165F13 for ; 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It requires the Zap shader binary that was provided by the vendor. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 60412281ab27..ac0197624c09 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -110,6 +110,14 @@ vreg_l10a_1p8: vreg-l10a-regulator { }; }; +&adreno_gpu { + status = "okay"; +}; + +&adreno_gpu_zap { + firmware-name = "qcom/sda660/a512_zap.mbn"; +}; + &adsp_pil { firmware-name = "qcom/sda660/adsp.mbn"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 40ad99d75738..92695375a63b 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1150,6 +1150,10 @@ opp-160000000 { opp-supported-hw = <0xff>; }; }; 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Sat, 07 Sep 2024 11:48:21 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 07 Sep 2024 21:48:15 +0300 Subject: [PATCH 4/7] arm64: dts: qcom: sda660-ifc6560: fix l10a voltage ranges Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240907-sdm660-wifi-v1-4-e316055142f8@linaro.org> References: <20240907-sdm660-wifi-v1-0-e316055142f8@linaro.org> In-Reply-To: <20240907-sdm660-wifi-v1-0-e316055142f8@linaro.org> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , AngeloGioacchino Del Regno , Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1040; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=6TCDPpBkY5pK/ecMFCBKg6KyrCqiL2Nwxp1MC/3FL0Y=; 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Fix the max_voltage range to be equal to minimum. Fixes: 4edbcf264fe2 ("arm64: dts: qcom: sda660-ifc6560: document missing USB PHY supplies") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index ac0197624c09..09bc010ce56a 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -104,7 +104,7 @@ vreg_l10a_1p8: vreg-l10a-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_l10a_1p8"; regulator-min-microvolt = <1804000>; - regulator-max-microvolt = <1896000>; + regulator-max-microvolt = <1804000>; regulator-always-on; regulator-boot-on; }; From patchwork Sat Sep 7 18:48:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 826490 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3938C166F0F for ; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 92695375a63b..dc8bc63bdc70 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -665,8 +665,6 @@ anoc2_smmu: iommu@16c0000 { , , ; - - status = "disabled"; }; a2noc: interconnect@1704000 { @@ -1234,8 +1232,6 @@ lpass_smmu: iommu@5100000 { , , ; - - status = "disabled"; }; sram@290000 { From patchwork Sat Sep 7 18:48:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 826306 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3832166F39 for ; Sat, 7 Sep 2024 18:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index dc8bc63bdc70..4536fa45869a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2412,6 +2412,33 @@ intc: interrupt-controller@17a00000 { redistributor-stride = <0x0 0x20000>; interrupts = ; }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x18800000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>; + clock-names = "cxo_ref_clk_pin"; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&anoc2_smmu 0x1a00>, + <&anoc2_smmu 0x1a01>; + qcom,snoc-host-cap-8bit-quirk; + qcom,no-msa-ready-indicator; + status = "disabled"; + }; }; sound: sound { From patchwork Sat Sep 7 18:48:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 826489 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBC111684BB for ; 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Sat, 07 Sep 2024 11:48:24 -0700 (PDT) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2f75c0b1af3sm2271861fa.129.2024.09.07.11.48.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Sep 2024 11:48:24 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 07 Sep 2024 21:48:18 +0300 Subject: [PATCH 7/7] arm64: dts: qcom: sda660-ifc6560: enable mDSP and WiFi devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240907-sdm660-wifi-v1-7-e316055142f8@linaro.org> References: <20240907-sdm660-wifi-v1-0-e316055142f8@linaro.org> In-Reply-To: <20240907-sdm660-wifi-v1-0-e316055142f8@linaro.org> To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , AngeloGioacchino Del Regno , Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ath11k@lists.infradead.org, Kalle Valo X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2512; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=XTnySTBdd5sawEDE4jiRSfy1oa5Ctl+YWAAqUv4joIg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBm3J/yWVPTASuqwGf6KgTFf9lHvriPxuej/lwbV aZEbLvM9JWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZtyf8gAKCRCLPIo+Aiko 1ZEqB/4/aeZwm+BdnM4GZPBXDOBNORRCXxR7ErRiln3e5RdBCf4xXCE6iQvmGFXEXS/LrebtK/X FNMW65S93BZFnkwxHn6UQ+EHAFGW27njCs/KvrkXnGPtjv50v4+JiV2Kp1cUWTb3w21MJAnJSU5 5TP4gUddxWWFBAqPeK0Khdh4ojgcQcxkbJZg49A+fkAl1eQ2+Muneg+woHbjtFa51jJYnvX0SWE /Xu+uP5bMQ3+J+0Y+lS2f+HdM6ZAKIvLcVs4cEzVqh4+fljZ6NUrrfM4P/TAlLZ3Q6M0gheBeJV 4PQ81KBAp7c2Opqwvn3clTZnknpVaurmdvLR2aBlgRtUjDU5 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Enable the onboard WiFi device present on the Inforce IFC6560 SBC. Pretty much like MSM8998 this device also doesn't generate the MSA_READY_IND indication. For the reference: ath10k_snoc 18800000.wifi: qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40050000 ath10k_snoc 18800000.wifi: qmi fw_version 0x101d01da fw_build_timestamp 2018-07-26 21:42 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.1.0.1.c2-00474-QCAHLSWMTPLZ-1 ath10k_snoc 18800000.wifi: qmi not waiting for msa_ready indicator ath10k_snoc 18800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc 18800000.wifi: kconfig debug 1 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc 18800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc 18800000.wifi: htt-ver 3.54 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 ath10k_snoc 18800000.wifi: invalid MAC address; choosing random Signed-off-by: Dmitry Baryshkov --- Cc: ath11k@lists.infradead.org Cc: Kalle Valo --- .../arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 09bc010ce56a..7948c8f6ab64 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -252,6 +252,11 @@ &qusb2phy1 { vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; }; +&remoteproc_mss { + firmware-name = "qcom/sda660/mba.mbn", "qcom/sda660/modem.mbn"; + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm660-regulators"; @@ -291,6 +296,11 @@ vreg_l1a_1p225: l1 { regulator-allow-set-load; }; + vreg_l5a_0p8: l5 { + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <848000>; + }; + vreg_l6a_1p3: l6 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1368000>; @@ -489,3 +499,15 @@ &usb3_qmpphy { vdda-pll-supply = <&vreg_l10a_1p8>; status = "okay"; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l9a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l6a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l19a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l8b_3p3>; + + qcom,ath10k-calibration-variant = "Inforce_IFC6560"; +};