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Wed, 11 Sep 2024 00:11:30 -0700 (PDT) From: Linus Walleij Date: Wed, 11 Sep 2024 09:11:12 +0200 Subject: [PATCH 1/7] mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller MIME-Version: 1.0 Message-Id: <20240911-brcmnand-fixes-v1-1-be112a20aaf1@linaro.org> References: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> In-Reply-To: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> To: u-boot@lists.denx.de, Dario Binacchi , Michael Trimarchi , Anand Gore , William Zhang , Kursad Oney , Philippe Reynes Cc: Linus Walleij , Florian Fainelli , Miquel Raynal X-Mailer: b4 0.14.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: William Zhang Backport from the Linux kernel commit 2ec2839a9062db8a592525a3fdabd42dcd9a3a9b "mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller" v7.2 controller has different ECC level field size and shift in the acc control register than its predecessor and successor controller. It needs to be set specifically. Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-2-william.zhang@broadcom.com Signed-off-by: Linus Walleij --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 74 ++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index b1af3f717d43..700d1122639f 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -218,6 +218,7 @@ struct brcmnand_controller { const unsigned int *page_sizes; unsigned int page_size_shift; unsigned int max_oob; + u32 ecc_level_shift; u32 features; /* for low-power standby/resume only */ @@ -544,6 +545,34 @@ enum { INTFC_CTLR_READY = BIT(31), }; +/*********************************************************************** + * NAND ACC CONTROL bitfield + * + * Some bits have remained constant throughout hardware revision, while + * others have shifted around. + ***********************************************************************/ + +/* Constant for all versions (where supported) */ +enum { + /* See BRCMNAND_HAS_CACHE_MODE */ + ACC_CONTROL_CACHE_MODE = BIT(22), + + /* See BRCMNAND_HAS_PREFETCH */ + ACC_CONTROL_PREFETCH = BIT(23), + + ACC_CONTROL_PAGE_HIT = BIT(24), + ACC_CONTROL_WR_PREEMPT = BIT(25), + ACC_CONTROL_PARTIAL_PAGE = BIT(26), + ACC_CONTROL_RD_ERASED = BIT(27), + ACC_CONTROL_FAST_PGM_RDIN = BIT(28), + ACC_CONTROL_WR_ECC = BIT(30), + ACC_CONTROL_RD_ECC = BIT(31), +}; + +#define ACC_CONTROL_ECC_SHIFT 16 +/* Only for v7.2 */ +#define ACC_CONTROL_ECC_EXT_SHIFT 13 + static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) { return brcmnand_readl(ctrl->nand_base + offs); @@ -675,6 +704,12 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) #endif /* __UBOOT__ */ ctrl->features |= BRCMNAND_HAS_WP; + /* v7.2 has different ecc level shift in the acc register */ + if (ctrl->nand_version == 0x0702) + ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; + else + ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; + return 0; } @@ -844,30 +879,6 @@ static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) return 0; } -/*********************************************************************** - * NAND ACC CONTROL bitfield - * - * Some bits have remained constant throughout hardware revision, while - * others have shifted around. - ***********************************************************************/ - -/* Constant for all versions (where supported) */ -enum { - /* See BRCMNAND_HAS_CACHE_MODE */ - ACC_CONTROL_CACHE_MODE = BIT(22), - - /* See BRCMNAND_HAS_PREFETCH */ - ACC_CONTROL_PREFETCH = BIT(23), - - ACC_CONTROL_PAGE_HIT = BIT(24), - ACC_CONTROL_WR_PREEMPT = BIT(25), - ACC_CONTROL_PARTIAL_PAGE = BIT(26), - ACC_CONTROL_RD_ERASED = BIT(27), - ACC_CONTROL_FAST_PGM_RDIN = BIT(28), - ACC_CONTROL_WR_ECC = BIT(30), - ACC_CONTROL_RD_ECC = BIT(31), -}; - static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) { if (ctrl->nand_version == 0x0702) @@ -880,18 +891,15 @@ static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) return GENMASK(4, 0); } -#define NAND_ACC_CONTROL_ECC_SHIFT 16 -#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 - static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) { u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; - mask <<= NAND_ACC_CONTROL_ECC_SHIFT; + mask <<= ACC_CONTROL_ECC_SHIFT; /* v7.2 includes additional ECC levels */ - if (ctrl->nand_version >= 0x0702) - mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; + if (ctrl->nand_version == 0x0702) + mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; return mask; } @@ -905,8 +913,8 @@ static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) if (en) { acc_control |= ecc_flags; /* enable RD/WR ECC */ - acc_control |= host->hwcfg.ecc_level - << NAND_ACC_CONTROL_ECC_SHIFT; + acc_control &= ~brcmnand_ecc_level_mask(ctrl); + acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; } else { acc_control &= ~ecc_flags; /* disable RD/WR ECC */ acc_control &= ~brcmnand_ecc_level_mask(ctrl); @@ -2225,7 +2233,7 @@ static int brcmnand_set_cfg(struct brcmnand_host *host, tmp &= ~brcmnand_ecc_level_mask(ctrl); tmp &= ~brcmnand_spare_area_mask(ctrl); if (ctrl->nand_version >= 0x0302) { - tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; + tmp |= cfg->ecc_level << ctrl->ecc_level_shift; tmp |= cfg->spare_area_size; } nand_writereg(ctrl, acc_control_offs, tmp); From patchwork Wed Sep 11 07:11:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 827366 Delivered-To: patch@linaro.org Received: by 2002:adf:ab1c:0:b0:367:895a:4699 with SMTP id q28csp663780wrc; Wed, 11 Sep 2024 00:11:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWpUd2iHfL8l2slZWUuluUjmKPENlA8KKOVHwgzmVaC0uYzJr8ld0t2iRzrIlRsYgG0avFdOg==@linaro.org X-Google-Smtp-Source: AGHT+IEqoWjoIhKnpyog32D+8OubJt7+B6VK/NTVYsVNNl+nbhlkVQTK9ekff4L2E97b0wiY4vFY X-Received: by 2002:a5d:5f50:0:b0:371:a60e:a821 with SMTP id ffacd0b85a97d-378b07f37fdmr1306808f8f.38.1726038714313; Wed, 11 Sep 2024 00:11:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1726038714; cv=none; d=google.com; s=arc-20240605; b=VnU+RXsGB3KlhaurRpmlh6RijPZjORiRpcc1t1ZlUOLdoBqC0+Zws8ujeCCMkxUEK1 sM3aJbj1SZPwU7aOHVtOfrQNnm1+K+j98IEZcr397Hx/deSWnaKkh8lcmd/KufXdzYKb xDaWf5XcVzs9cBUJjINidPCTLuEGpApnCU/TUqja1X6HfzdzKdJHz7QV79Ns8+joaomW IN2Uel2z3fjN9EH2Mnpw9TnyOdCoOXjGWWoPJdbK5goUyGKurol3yjddokHrnMR83Asb hcBNy8ZkbWktcjJO2IYsKmkTXk+hXViYwMO1qQuSWYMoehGrVO2IMGS8P24AHvUXJ5Wq Ny5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=cy0AelE8X6/ImwZyMOvnLyspFv+MmXcjl2xKIRLZjow=; fh=bbSjVJcsz6ma3Arirz+KWNos93PEC62yDVUDN8y6koA=; b=c4gET86wX6BMEptJm192yWeFhJY9xiSgIzsEBD1RwZxaGYxKPnNVUPRYrJbljxPdyZ F+LeKU9hPr083nnjYZI9cnSTmGzBWUItQMvT5i+IWZ3RT1j1gZ0PHY+XSdCzhtYhQjcC QJhwvsB2j8XK0GFq5VDHo2wsOMqkemUxf3KTNgitA2HLfPm1m1vEeqcEjnaDd1ARG9tj SXfqg9+8DJ+H4Dyt97GHTY6KuqZ1pr/0FmaKJHIz/UhKg1FYie2ywaS4k1dTW5Bp+Qq1 MrhKFlaGxavN+FxZyW8WelIcijIKwDdu/05sPQz0/5ijoF7hxC9jJH0tnJ8M4LIoBzqM ynjQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=or6zx83L; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Do a final check after time out happens to ensure reading the correct status. Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-3-william.zhang@broadcom.com Signed-off-by: Linus Walleij --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 700d1122639f..46a4107a83a9 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1011,6 +1011,14 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, } while (get_timer(base) < limit); #endif /* __UBOOT__ */ + /* + * do a final check after time out in case the CPU was busy and the driver + * did not get enough time to perform the polling to avoid false alarms + */ + val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); + if ((val & mask) == expected_val) + return 0; + dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", expected_val, val & mask); From patchwork Wed Sep 11 07:11:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 827367 Delivered-To: patch@linaro.org Received: by 2002:adf:ab1c:0:b0:367:895a:4699 with SMTP id q28csp663828wrc; Wed, 11 Sep 2024 00:12:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX+ris/OizfO63fd7mpLW9LL3UXU2RvyaEEFIU6ukn6UiEmAtR7MgxVxo5BeNKDNshaXJgYog==@linaro.org X-Google-Smtp-Source: AGHT+IHPUUzOneW/GGWals8Vvd3vwWPBFcuXT7iDt3oecFn0ekG7csWjxjnCWs94Uc2EiUYHbNK1 X-Received: by 2002:a5d:658f:0:b0:374:bd01:707c with SMTP id ffacd0b85a97d-3789243fd50mr10996516f8f.48.1726038725306; Wed, 11 Sep 2024 00:12:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1726038725; cv=none; d=google.com; s=arc-20240605; b=OVFgPyG6v1qmZC+NNqOU1s7K9+UCaHFU/4JuBS+Pi1Dnlg10rAjZaKO0D+JhLqWtHQ 7DLA1q9K+32v63jpDlxLbGawDWShqUsYyXvWANulXiMnp7dNFv9fTo8DOBxKlhFVhGHt Xf5znkfkoQYqtexhDDZ1LGSZQIgNSRw1FAGeDMBI5GpQ7u8eHLjaK5J8tmwmSRbYRY7i 39vTb0CKgT3zxoRi+Rn7LUisawre0uB1Bj3GbBB44n0n2vKYwhyfg/ZI1hJn7ZdNrVtF K0sf1ZZ7gpZvma3iCcxhxFntY2NtI8hIisDHxjdZv0DQQuEal7oI2l0xPM+BIVRmlW67 Fojw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=EvEkZF2r2AqggnLWTgwzPhL/JoYelLUDEL1aq/7CH+o=; fh=bbSjVJcsz6ma3Arirz+KWNos93PEC62yDVUDN8y6koA=; b=PmeJMJ0YiCRBj8E/4rBBxlMMJxECv6H7R7DMBf91ezHV/GltJIFYUMjOImchiE8VJp WiNRk7UUzwCpVXzvdLHRpudyLByD30I60cf73v5Lgk4E/Y/yd8X9l05tI0SQFxqNb2Oq mx+F6ps6uVb366bD8fh7U790yWFpJQVA9RWHyF1pOy/kQODYDkpEHlwOwu6RfCUZ4ozI Xi9vT3DpbZDp3er+WE8nsLFbf99/6VPbsVw7RjkM41vpmWmOdqRNpSbiXK4Ae2lJCd4x xd7YlrtrKNqoVKquuT9+NSvAB1gwkPHocQhARY0gxMDg0RQ82SwHT8qJg7ZVB/lqIGz2 f8dw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GGucw/+E"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 11 Sep 2024 00:11:32 -0700 (PDT) From: Linus Walleij Date: Wed, 11 Sep 2024 09:11:14 +0200 Subject: [PATCH 3/7] mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write MIME-Version: 1.0 Message-Id: <20240911-brcmnand-fixes-v1-3-be112a20aaf1@linaro.org> References: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> In-Reply-To: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> To: u-boot@lists.denx.de, Dario Binacchi , Michael Trimarchi , Anand Gore , William Zhang , Kursad Oney , Philippe Reynes Cc: Linus Walleij , Florian Fainelli , Miquel Raynal X-Mailer: b4 0.14.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: William Zhang Backport of upstream Linux commit 5d53244186c9ac58cb88d76a0958ca55b83a15cd "mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write" When the oob buffer length is not in multiple of words, the oob write function does out-of-bounds read on the oob source buffer at the last iteration. Fix that by always checking length limit on the oob buffer read and fill with 0xff when reaching the end of the buffer to the oob registers. Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-5-william.zhang@broadcom.com Signed-off-by: Linus Walleij --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 46a4107a83a9..60d34bd21f53 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1334,19 +1334,33 @@ static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, const u8 *oob, int sas, int sector_1k) { int tbytes = sas << sector_1k; - int j; + int j, k = 0; + u32 last = 0xffffffff; + u8 *plast = (u8 *)&last; /* Adjust OOB values for 1K sector size */ if (sector_1k && (i & 0x01)) tbytes = max(0, tbytes - (int)ctrl->max_oob); tbytes = min_t(int, tbytes, ctrl->max_oob); - for (j = 0; j < tbytes; j += 4) + /* + * tbytes may not be multiple of words. Make sure we don't read out of + * the boundary and stop at last word. + */ + for (j = 0; (j + 3) < tbytes; j += 4) oob_reg_write(ctrl, j, (oob[j + 0] << 24) | (oob[j + 1] << 16) | (oob[j + 2] << 8) | (oob[j + 3] << 0)); + + /* handle the remaing bytes */ + while (j < tbytes) + plast[k++] = oob[j++]; + + if (tbytes & 0x3) + oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); + return tbytes; } From patchwork Wed Sep 11 07:11:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 827368 Delivered-To: patch@linaro.org Received: by 2002:adf:ab1c:0:b0:367:895a:4699 with SMTP id q28csp663884wrc; Wed, 11 Sep 2024 00:12:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX3nXt2CLhf6vAE8EAfjdBWBRTpBbnXMnzTsjdyGxW6g9GqcaB0gn103zxI0oQA9Z5OpxYOOg==@linaro.org X-Google-Smtp-Source: AGHT+IH0juNMCOAxgfBNTjwvMcLCJtpoRpgmVj6Yuv+WzCgzXuAJZBP0Y0W+KkXjXqos/SYTGz3f X-Received: by 2002:a05:6000:781:b0:374:c56c:fbc7 with SMTP id ffacd0b85a97d-378895ca924mr11454652f8f.15.1726038737048; Wed, 11 Sep 2024 00:12:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1726038737; cv=none; d=google.com; s=arc-20240605; b=b41T28ddBCyMTac8Fc34AL6OCRdWdVHyAspMG4RhiIovARV9dCTHgFRjKfLWb5fBUI h3VqDRfw/mp3b8pgBJy+G6MjV+AEJlrkgE4BL4C5CPktZh+i58c5/tRf8x0Mmskh038j IGDyJE8CS4hgh742cliBGpqb0PjMXZlzPcunWZEJDCDB9yUuY7F13g4LB29gYWE3Q4Q2 N7uyt/EDh1aQtp/Z28IMuR0DEtXfqro97W9QkdyOf3N/CIaadcJgVkBswnm5SOp+WCm9 aPDeR+XYV+a0L1nIBJgVazrR3rOretFKQv5op4nmpQQqsq7LKS+dUb6lc+afQSzf0IIM e9rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=yKuLdsLuyes8mnBA3MrU0R/rfIaNO+BeT5q0k2EEnh0=; fh=h9O78uwswjRVdW8Id1esrMzZoEr+njK1me6t0mcjnS0=; b=bADc/+QQUXpEh9nKcURQcm/Nhcjx+UsSb5b74uqLGZoY6gIdMAYXcbwuqCjOb1zgYX G8mlfrgcj/31Bcnx2oKND42v0nprVKE5D4Ju/buRx3Hv+P3+RJFl98LHN3lEiPNaTZtC 8TrKWq4ESHWIci0/wpnorcV2ze9cWRxLb1+URi8jbulr/rhZRHGC9XmOlZq2R4IgGMq/ sSeKjfRTNm3/c4gYWjt+oeZKJJL2ef2nt8ZVoIP6U2yta+Lky1RHGrqSmuGFc0z+wmD3 9vt2tBXCXwwhXW93naJr38ttS78kfUAHN5johM0Uc6GQ5mq+/hDHjABZOKTvZ5PrqDdh qaKQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ILQTihuw; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 11 Sep 2024 00:11:34 -0700 (PDT) From: Linus Walleij Date: Wed, 11 Sep 2024 09:11:15 +0200 Subject: [PATCH 4/7] mtd: rawnand: brcmnand: Fix mtd oobsize MIME-Version: 1.0 Message-Id: <20240911-brcmnand-fixes-v1-4-be112a20aaf1@linaro.org> References: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> In-Reply-To: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> To: u-boot@lists.denx.de, Dario Binacchi , Michael Trimarchi , Anand Gore , William Zhang , Kursad Oney , Philippe Reynes Cc: Linus Walleij , Miquel Raynal X-Mailer: b4 0.14.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: William Zhang Backport from upstream Linux commit 60177390fa061c62d156f4a546e3efd90df3c183 "mtd: rawnand: brcmnand: Fix mtd oobsize" brcmnand controller can only access the flash spare area up to certain bytes based on the ECC level. It can be less than the actual flash spare area size. For example, for many NAND chip supporting ECC BCH-8, it has 226 bytes spare area. But controller can only uses 218 bytes. So brcmand driver overrides the mtd oobsize with the controller's accessible spare area size. When the nand base driver utilizes the nand_device object, it resets the oobsize back to the actual flash spare aprea size from nand_memory_organization structure and controller may not able to access all the oob area as mtd advises. This change fixes the issue by overriding the oobsize in the nand_memory_organization structure to the controller's accessible spare area size. Fixes: a7ab085d7c16 ("mtd: rawnand: Initialize the nand_device object") Signed-off-by: William Zhang Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-6-william.zhang@broadcom.com Signed-off-by: Linus Walleij --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 60d34bd21f53..552b239b95ae 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -2304,6 +2305,8 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) { struct mtd_info *mtd = nand_to_mtd(&host->chip); struct nand_chip *chip = &host->chip; + struct nand_device *nanddev = mtd_to_nanddev(mtd); + struct nand_memory_organization *memorg = nanddev_get_memorg(nanddev); struct brcmnand_controller *ctrl = host->ctrl; struct brcmnand_cfg *cfg = &host->hwcfg; char msg[128]; @@ -2331,10 +2334,11 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) if (cfg->spare_area_size > ctrl->max_oob) cfg->spare_area_size = ctrl->max_oob; /* - * Set oobsize to be consistent with controller's spare_area_size, as - * the rest is inaccessible. + * Set mtd and memorg oobsize to be consistent with controller's + * spare_area_size, as the rest is inaccessible. */ mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); + memorg->oobsize = mtd->oobsize; cfg->device_size = mtd->size; cfg->block_size = mtd->erasesize; From patchwork Wed Sep 11 07:11:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 827369 Delivered-To: patch@linaro.org Received: by 2002:adf:ab1c:0:b0:367:895a:4699 with SMTP id q28csp663924wrc; Wed, 11 Sep 2024 00:12:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXaBE0V78He6QJMyys6KPTJAmzeU9aHCd+CwRBYOp6uF4F7ciEruhL8FC1YyGPSWX2qDg4mLA==@linaro.org X-Google-Smtp-Source: AGHT+IE/v/Y/RsObALZ/FKNT+EvGvpS3uu5xtDfB+RNV/eBO5F224BEExnYKSC0QpKeNJszKBeFw X-Received: by 2002:a5d:65cd:0:b0:368:6f64:3072 with SMTP id ffacd0b85a97d-378b0791f46mr1200308f8f.7.1726038746723; Wed, 11 Sep 2024 00:12:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1726038746; cv=none; d=google.com; s=arc-20240605; b=Rr8TlDfi9CDvBKVbxpYF4OFEjpJWRXuKWYlr/tQNt4YQMxLVDqvWvyK7B4tRJH1e+F EzsYW3fIItHMeXqZnwR374Koi8gYXuD+4IRKy7uvRH0/PXBAZCADvoVsP73jkimy0MMb 1PzwwxeHNKfY1eYgs4cpWzMeHOSchKvZqhUGN+HrQQxbcyadcZxfpnNdxqIm558nVgZB N9qhAHRdW4MdqDXA6xaQDmV/EnScyMggk045ecNF1D+HUSxyxgq7dCbzNUDVHvkKQKJ6 XC45wlBNQqVPzA9Rf4RNxtHwRY06SB8l10WNvY5nUV2+rgeW/Wy1+HFns4ov3oWljYup 7r4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Vqy6PVBHxWJx4+pP+WOa/qhGDCdQPicD1vpW1c3GTF4=; fh=ftQntzGq59ruF58t30aRXV87AbbvorkS2P8ZbONQbrM=; b=hj3V/njFaHtOE+Ja2epNEKrFuahnU88bxgBg9kLH6QpFm0zzeJcYMDamfac/biIwQm 9A9dbjpbG8lljW7vNG3jPXBkAjcEdaKxs1sEIA8px3pck1KtDpdQYnH7CVZEfn5f3xtw ZLsvs52tc40O+lcHoFjmu62BI3pCzGF+RffjE10bpXQC9SQqk6zurcMmvcjPtXxH0e1u o5rv/Oj/b1AFJtmyrq2xnrPN2oUPEZkCEXDer0JTKJMOxDoNRk3Gm77r6NmhxFzzzd5F 54b9ihHfGTLboh/tGNyhzxRFlyF+4dtQjIxhmULEkxNluG95kZJ/HRki3ziH9xjJa9ml vSUw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZdfFDHUu; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: William Zhang Signed-off-by: Linus Walleij --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 20 +++++++++++++++++--- drivers/mtd/nand/raw/brcmnand/brcmnand.h | 2 ++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 552b239b95ae..2f786584a1ae 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -769,6 +769,20 @@ static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, __raw_writel(val, ctrl->nand_fc + word * 4); } +static inline void brcmnand_read_data_bus(struct brcmnand_controller *ctrl, + void __iomem *flash_cache, u32 *buffer, int fc_words) +{ + struct brcmnand_soc *soc = ctrl->soc; + int i; + + if (soc && soc->read_data_bus) { + soc->read_data_bus(soc, flash_cache, buffer, fc_words); + } else { + for (i = 0; i < fc_words; i++) + buffer[i] = brcmnand_read_fc(ctrl, i); + } +} + static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) { @@ -1812,7 +1826,7 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, { struct brcmnand_host *host = nand_get_controller_data(chip); struct brcmnand_controller *ctrl = host->ctrl; - int i, j, ret = 0; + int i, ret = 0; brcmnand_clear_ecc_addr(ctrl); @@ -1825,8 +1839,8 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, if (likely(buf)) { brcmnand_soc_data_bus_prepare(ctrl->soc, false); - for (j = 0; j < FC_WORDS; j++, buf++) - *buf = brcmnand_read_fc(ctrl, j); + brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf, FC_WORDS); + buf += FC_WORDS; brcmnand_soc_data_bus_unprepare(ctrl->soc, false); } diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.h b/drivers/mtd/nand/raw/brcmnand/brcmnand.h index 6946a62b0679..3a1d60471361 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.h +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.h @@ -11,6 +11,8 @@ struct brcmnand_soc { void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en); void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare, bool is_param); + void (*read_data_bus)(struct brcmnand_soc *soc, void __iomem *flash_cache, + u32 *buffer, int fc_words); void *ctrl; }; From patchwork Wed Sep 11 07:11:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 827370 Delivered-To: patch@linaro.org Received: by 2002:adf:ab1c:0:b0:367:895a:4699 with SMTP id q28csp663968wrc; Wed, 11 Sep 2024 00:12:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXlB36Py6wkmwnkl5H20I32G0pj5Zeutedw4DYzV2lsSeQSO86P0joOr2hNQwDQRtVdPshwhw==@linaro.org X-Google-Smtp-Source: AGHT+IFm+pdyFh5QypQcy13ZJSJjtNpxe7ypIUWCemI1s0QiYnyasQ7BgEoDzq3xciiHOjTVfyVm X-Received: by 2002:a05:600c:1d0f:b0:42c:b4f1:f281 with SMTP id 5b1f17b1804b1-42cb4f1f41amr78170885e9.34.1726038756767; Wed, 11 Sep 2024 00:12:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1726038756; cv=none; d=google.com; s=arc-20240605; b=F35o5fFvaSUj0JbDqlFuo3kgbq3+AFLfSEmE7MyLZIYVGT4iUenPIrQ17DFW5S+qxW OP+ZZ205BTWnbSWIqX8aZnPQh6eco/KMdJH+i+gTrYd9aXdOUpYdzqcB0xKEIn0Rkd5C 8vAdim8iB/N54JAxXKuUjI2PCLR5sDnXFWVntDroi16gJDY0hd9toTTk0wwi5n7iG41P 9VgkpZv3uYafaedq/swjfGXGWg1zcJBL/qAGUUz3Bwhvokyf+i7rNQW2kWu2ociEsW3v ZjHUUmuLZLYD5vGs73dW9zFL3AYQ4cuiggmx7UvDNPoTeFXAflI574+8paeQNZBtE5MK ZyVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=0thuF0I1ZnDB7MFUd0vK4BvdCnk5Fzf2pv7fmJ53tVo=; fh=LjJWeawkcuYIe1gemXcY1RbqD239cYwgFjJpsG2gko4=; b=BLuzqlPTp949JFydGVtCvKPrA0jiCz97oY3YfpUoVlvJOVcPOU0sZfc6o0Jq3Hh7LJ tuwuHwqK/d8P5NAkUppRagY5QsGWXbcxI50A/d9MJkI9mV0uqE7XFzdZXjnqfBPrdGcW /TuYiMkvwOjUOQ7MsnpZVp/QFqDEshXZ6LW8xFxkb5z1J4IBEypJx4u3rg00Uw9QQg21 NjftFMEGUUR5LMhCHMRNbBGWUKCOE3Zsl8Xk66qgGmbyHepsqxSiJ+tvqtEhgbIgpM6z QcCIiAkWYj1i0/NpX4hrP3vfmKyS909wo0zjlb3exq93h6cD+UhXTuPG0uqEPWdDIPPB EgRw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OntOG8p3; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 11 Sep 2024 00:11:38 -0700 (PDT) From: Linus Walleij Date: Wed, 11 Sep 2024 09:11:17 +0200 Subject: [PATCH 6/7] mtd: rawnand: brcmnand: Support write protection setting from dts MIME-Version: 1.0 Message-Id: <20240911-brcmnand-fixes-v1-6-be112a20aaf1@linaro.org> References: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> In-Reply-To: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> To: u-boot@lists.denx.de, Dario Binacchi , Michael Trimarchi , Anand Gore , William Zhang , Kursad Oney , Philippe Reynes Cc: Linus Walleij , Florian Fainelli , Kamal Dasu , David Regan , Miquel Raynal X-Mailer: b4 0.14.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: William Zhang Backport of upstream Linux commit 8e7daa85641c9559c113f6b217bdc923397de77c "mtd: rawnand: brcmnand: Support write protection setting from dts" The write protection feature is controlled by the module parameter wp_on with default set to enabled. But not all the board use this feature especially in BCMBCA broadband board. And module parameter is not sufficient as different board can have different option. Add a device tree property and allow this feature to be configured through the board dts on per board basis. Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Reviewed-by: Kamal Dasu Reviewed-by: David Regan Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-14-william.zhang@broadcom.com Signed-off-by: Linus Walleij --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 2f786584a1ae..55d5d27438a8 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -2847,6 +2847,14 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc) /* Read the write-protect configuration in the device tree */ wp_on = dev_read_u32_default(dev, "write-protect", wp_on); + /* Check if the board connects the WP pin */ +#ifndef __UBOOT__ + if (of_property_read_bool(dn, "brcm,wp-not-connected")) +#else + if (dev_read_bool(ctrl->dev, "brcm,wp-not-connected")) +#endif /* __UBOOT__ */ + wp_on = 0; + if (ctrl->features & BRCMNAND_HAS_WP) { /* Permanently disable write protection */ if (wp_on == 2) From patchwork Wed Sep 11 07:11:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 827371 Delivered-To: patch@linaro.org Received: by 2002:adf:ab1c:0:b0:367:895a:4699 with SMTP id q28csp664017wrc; Wed, 11 Sep 2024 00:12:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUAnMjWwfqDcuSOkOA2s8u9mD13e3Th+Qd7fO2drGwJ+BfbxNATLx8haZnpnLR/TOyuPNepEA==@linaro.org X-Google-Smtp-Source: AGHT+IElo2dfswswlTwKm4enSjwBqxpo2KmB0/u6QyGjKIbyqaTeynwfs7H+qpJGhnJ8bJzqcjZ5 X-Received: by 2002:a5d:4f8c:0:b0:367:8a00:fac3 with SMTP id ffacd0b85a97d-378895d5318mr11316424f8f.30.1726038767654; Wed, 11 Sep 2024 00:12:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1726038767; cv=none; d=google.com; s=arc-20240605; b=J7Kd4mCRjTnIh2+XKP7SgPQxWEjGaI+2BQjrqAgh/4iYRHKeNUDKLtmzlBsqzi3IJe isTv7RyAqRxgojFOCPTyAkrrfqH1RSjr4JPA5xQDBckOdNZ4jhGFFnOQj1l46oH4xOlI bnQXFikxtb15kK5DgtFFJuCzFTxYlx4lG7XnxXR1MrRcCrci5RMRrN2YVlH7MlVBFWoj NzwavOXgyMcd2nHdH1ZMpflIQ7GTRntqF73lHLOs+02tClTsH2Pmv+aZ35RZjSMD/7lg 87Aed2+IH6o/bu3vg0CCn4eubfeu+YzlslU5KvZ1MIIj4DrEzb4gnOkG4/xykBm1NDTu n1Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=gngvSZSXDYIJVQBbZCkdBAj365BqDHKg2e7auavSkXs=; fh=YTnrfRIYLE/pT3cqoHvYay4qEd2auqJxcPFxhd6I1v4=; b=HSJE87drLNWSyRV/IWxVT2kqNBUGNv5h5RvD15ACL99PQXATsE480DR4IEb9Goo8c1 Pa53WdN2y4g3VEQWqg2cNgmXdSvm/jAsQllaMGZ5WOVs7w4KqbjXNWRtUmda9+85jRHy Lkxy4pQ70oazTf7Ee2IsKFfMLmr0EcGcecl5VQNkGOiUiciF/ovU9UylagvjYeOZQUdv 7u0wIupLcjsxbe8MvYTd6L6gNA3Q5nUbgAEPR122Qxp15HJejc3tUOtnhBrhXj4xNqyQ wIWej2a8KMEYJiCBKbOVGbLq/XHAX0crQv5fQxz5BMHCFuLA+z5o+BqtY3/9UQs/ApDD TTsw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qu0SVrjN; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 11 Sep 2024 00:11:39 -0700 (PDT) From: Linus Walleij Date: Wed, 11 Sep 2024 09:11:18 +0200 Subject: [PATCH 7/7] mtd: rawnand: brcmnand: Add support for getting ecc setting from strap MIME-Version: 1.0 Message-Id: <20240911-brcmnand-fixes-v1-7-be112a20aaf1@linaro.org> References: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> In-Reply-To: <20240911-brcmnand-fixes-v1-0-be112a20aaf1@linaro.org> To: u-boot@lists.denx.de, Dario Binacchi , Michael Trimarchi , Anand Gore , William Zhang , Kursad Oney , Philippe Reynes Cc: Linus Walleij , David Regan , Miquel Raynal X-Mailer: b4 0.14.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: William Zhang Backport from the upstream Linux kernel commit c2cf7e25eb2a3c915a420fb8ceed8912add7f36c "mtd: rawnand: brcmnand: Add support for getting ecc setting from strap" Note: the upstream kernel introduces a new bool brcmnand_get_sector_size_1k() function because the int version in U-Boot has been removed in Linux. I kept the old int-returning version that is already in U-Boot as we depend on that in other code. BCMBCA broadband SoC based board design does not specify ecc setting in dts but rather use the SoC NAND strap info to obtain the ecc strength and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for this purpose and update driver to support this option. However these two options can not be used at the same time. Signed-off-by: William Zhang Reviewed-by: David Regan Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20240301173308.226004-1-william.zhang@broadcom.com Signed-off-by: Linus Walleij --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 70 ++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 55d5d27438a8..1ffd6cfff98f 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -980,6 +980,43 @@ static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) nand_writereg(ctrl, acc_control_offs, tmp); } +static int brcmnand_get_spare_size(struct brcmnand_host *host) +{ + struct brcmnand_controller *ctrl = host->ctrl; + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, + BRCMNAND_CS_ACC_CONTROL); + u32 acc = nand_readreg(ctrl, acc_control_offs); + + return (acc & brcmnand_spare_area_mask(ctrl)); +} + +static void brcmnand_get_ecc_settings(struct brcmnand_host *host, struct nand_chip *chip) +{ + struct brcmnand_controller *ctrl = host->ctrl; + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, + BRCMNAND_CS_ACC_CONTROL); + bool sector_size_1k = brcmnand_get_sector_size_1k(host); + int spare_area_size, ecc_level; + u32 acc; + + spare_area_size = brcmnand_get_spare_size(host); + acc = nand_readreg(ctrl, acc_control_offs); + ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_shift; + if (sector_size_1k) + chip->ecc.strength = ecc_level * 2; + else if (spare_area_size == 16 && ecc_level == 15) + chip->ecc.strength = 1; /* hamming */ + else + chip->ecc.strength = ecc_level; + + if (chip->ecc.size == 0) { + if (sector_size_1k) + chip->ecc.size = 1024; + else + chip->ecc.size = 512; + } +} + /*********************************************************************** * CS_NAND_SELECT ***********************************************************************/ @@ -2323,12 +2360,33 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) struct nand_memory_organization *memorg = nanddev_get_memorg(nanddev); struct brcmnand_controller *ctrl = host->ctrl; struct brcmnand_cfg *cfg = &host->hwcfg; - char msg[128]; u32 offs, tmp, oob_sector; + bool use_strap = false; + char msg[128]; int ret; memset(cfg, 0, sizeof(*cfg)); +#ifndef __UBOOT__ + use_strap = of_property_read_bool(nand_get_flash_node(chip), + "brcm,nand-ecc-use-strap"): +#else + ret = ofnode_read_bool(nand_get_flash_node(chip), + "brcm,nand-ecc-use-strap"); +#endif /* __UBOOT__ */ + /* + * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error out + * if both exist. + */ + if (chip->ecc.strength && use_strap) { + dev_err(ctrl->dev, + "ECC strap and DT ECC configuration properties are mutually exclusive\n"); + return -EINVAL; + } + + if (use_strap) + brcmnand_get_ecc_settings(host, chip); + #ifndef __UBOOT__ ret = of_property_read_u32(nand_get_flash_node(chip), "brcm,nand-oob-sector-size", @@ -2338,10 +2396,14 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) "brcm,nand-oob-sector-size", &oob_sector); #endif /* __UBOOT__ */ + if (ret) { - /* Use detected size */ - cfg->spare_area_size = mtd->oobsize / - (mtd->writesize >> FC_SHIFT); + if (use_strap) + cfg->spare_area_size = brcmnand_get_spare_size(host); + else + /* Use detected size */ + cfg->spare_area_size = mtd->oobsize / + (mtd->writesize >> FC_SHIFT); } else { cfg->spare_area_size = oob_sector; }