From patchwork Tue Nov 19 02:19:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179624 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2684ilf; Mon, 18 Nov 2019 18:19:35 -0800 (PST) X-Google-Smtp-Source: APXvYqwV60UHTAvtLihd5FjNmQHKDf24jr5RTxALxO7AyWj02muPg0p2lwfSLUdqm7HE40E+NCqr X-Received: by 2002:a17:906:5f81:: with SMTP id a1mr31111549eju.54.1574129975315; Mon, 18 Nov 2019 18:19:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574129975; cv=none; d=google.com; s=arc-20160816; b=e11+AU62EYeUx2RkDduOAAb9zXuotUy0xkk1wVlOFw6TdwkQGLktDxQmiKFJh0WYrX 78EO6URadOF/TMRsRsTaoXPEvbzTnkD2MHQUbSfLLg/qutMqtGpFPGsnhPXDgOczF904 Y5PiEWb30pGZmi1jJdailV4hle+tzUqS2vdRKHm0wBElhdli7t7r8xLGGFwsp99OfUSq hLD9WLa2RucXpGaWscAdXBhQudNC3RdyQyiukNhqOk1YdgH03lPcJBhrxtvosQ47d+jZ QIPHVnHfbj7+hVhIIz+yGh0lFpreC9OfgFICAd/vu+4Z2bzZTUOY49p/CAj0Wt1o5W2A 95QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=v7VsnMMeRZ3+/NCqfwTAkRtWkVKXM4b4xH09IstrQh8=; b=E3s2CKXWaqB9h2zEcJe9MXBbkuAgk46KB4zwtC6/dAttcaHbF1cc+Yod9YuENQQBdD radHcw+dimvwMec5jZVomAKhF8sLXpIfr82fJi84qnEB5kFQBh7ZcMQHpGj7XqmOpK9j axMA6qAlX6dWefHVEqg3uOEOeOwNXri6sILUdr+oGA1t9y4ZU7Xr0R8H4T7nuXoD1vdK hbsV53Y3Pvg74OJ6yz09l+VcTaPl2rMMJjzM/rrCiQDBBq3W8nLe/cbjRwmo+52GBkry 0J8jXpkdihjSq8Dm+lYLVtwDmivRqgZ9yyU9g1UYdKmpxcsOkRrGh4EcNU8ebgaU253G mkbQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z10si13018867ejr.262.2019.11.18.18.19.35; Mon, 18 Nov 2019 18:19:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727399AbfKSCTa (ORCPT + 26 others); Mon, 18 Nov 2019 21:19:30 -0500 Received: from mx2.suse.de ([195.135.220.15]:57996 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726983AbfKSCTZ (ORCPT ); Mon, 18 Nov 2019 21:19:25 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id EBDB6AE12; Tue, 19 Nov 2019 02:19:22 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Aleix Roca Nonell , James Tai , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v4 2/8] irqchip: Add Realtek RTD1295 mux driver Date: Tue, 19 Nov 2019 03:19:11 +0100 Message-Id: <20191119021917.15917-3-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This irq mux driver implements the RTD1295 SoC's non-linear mapping between status and enable bits. Based in part on QNAP's arch/arm/mach-rtk119x/rtk_irq_mux.c and Synology's drivers/irqchip/irq-rtk.c code. Signed-off-by: Andreas Färber Cc: Aleix Roca Nonell Signed-off-by: James Tai Signed-off-by: Andreas Färber --- v3 -> v4: * Drop no-op .irq_set_affinity callback (Thomas) * Clear all interrupts (James) * Updated SPDX-License-identifier * Use tabular formatting (Thomas) * Adopt different braces style (Thomas) * Use raw_spinlock_t (Thomas) * Shortened callback from isr_to_scpu_int_en_mask to isr_to_int_en_mask (Thomas) * Fixed of_iomap() error handling to not use IS_ERR() * Don't mask unmapped NMIs by checking for a non-zero mask * Cache SCPU_INT_EN to avoid superfluous reads (Thomas) * Renamed functions and variables from rtd119x to rtd1195 v2 -> v3: * Adopted spin_lock_irq{save,restore}() (Marc) * Adopted single-write masking (Marc) * Adopted misc compatible string * Introduced explicit bit mapping * Adopted looped processing of pending interrupts (Marc) * Replaced unmask implementation with UMSK_ISR write * Introduced enable/disable ops and dropped no longer needed UART0 quirk v1 -> v2: * Renamed struct fields to avoid ambiguity (Marc) * Refactored offset lookup to avoid per-compatible init functions * Inserted white lines to clarify balanced locking (Marc) * Dropped forwarding of set_affinity to GIC (Marc) * Added spinlocks for consistency (Marc) * Limited initialization quirk to iso mux * Fixed spinlock initialization (Andrew) drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rtd1195-mux.c | 283 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 284 insertions(+) create mode 100644 drivers/irqchip/irq-rtd1195-mux.c -- 2.16.4 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e806dda690ea..d678881eebc8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -104,3 +104,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_ARCH_REALTEK) += irq-rtd1195-mux.o diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c new file mode 100644 index 000000000000..e6b08438b23c --- /dev/null +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek RTD1295 IRQ mux + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include +#include +#include +#include +#include +#include +#include + +struct rtd1195_irq_mux_info { + unsigned int isr_offset; + unsigned int umsk_isr_offset; + unsigned int scpu_int_en_offset; + const u32 *isr_to_int_en_mask; +}; + +struct rtd1195_irq_mux_data { + void __iomem *reg_isr; + void __iomem *reg_umsk_isr; + void __iomem *reg_scpu_int_en; + const struct rtd1195_irq_mux_info *info; + int irq; + u32 scpu_int_en; + struct irq_domain *domain; + raw_spinlock_t lock; +}; + +static void rtd1195_mux_irq_handle(struct irq_desc *desc) +{ + struct rtd1195_irq_mux_data *data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 isr, mask; + int i; + + chained_irq_enter(chip, desc); + + isr = readl_relaxed(data->reg_isr); + + while (isr) { + i = __ffs(isr); + isr &= ~BIT(i); + + mask = data->info->isr_to_int_en_mask[i]; + if (mask && !(data->scpu_int_en & mask)) + continue; + + if (!generic_handle_irq(irq_find_mapping(data->domain, i))) + writel_relaxed(BIT(i), data->reg_isr); + } + + chained_irq_exit(chip, desc); +} + +static void rtd1195_mux_mask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + + writel_relaxed(BIT(data->hwirq), mux_data->reg_isr); +} + +static void rtd1195_mux_unmask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + + writel_relaxed(BIT(data->hwirq), mux_data->reg_umsk_isr); +} + +static void rtd1195_mux_enable_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 mask; + + mask = mux_data->info->isr_to_int_en_mask[data->hwirq]; + if (!mask) + return; + + raw_spin_lock_irqsave(&mux_data->lock, flags); + + mux_data->scpu_int_en |= mask; + writel_relaxed(mux_data->scpu_int_en, mux_data->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux_data->lock, flags); +} + +static void rtd1195_mux_disable_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 mask; + + mask = mux_data->info->isr_to_int_en_mask[data->hwirq]; + if (!mask) + return; + + raw_spin_lock_irqsave(&mux_data->lock, flags); + + mux_data->scpu_int_en &= ~mask; + writel_relaxed(mux_data->scpu_int_en, mux_data->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux_data->lock, flags); +} + +static struct irq_chip rtd1195_mux_irq_chip = { + .name = "rtd1195-mux", + .irq_mask = rtd1195_mux_mask_irq, + .irq_unmask = rtd1195_mux_unmask_irq, + .irq_enable = rtd1195_mux_enable_irq, + .irq_disable = rtd1195_mux_disable_irq, +}; + +static int rtd1195_mux_irq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hw) +{ + struct rtd1195_irq_mux_data *data = d->host_data; + + irq_set_chip_and_handler(irq, &rtd1195_mux_irq_chip, handle_level_irq); + irq_set_chip_data(irq, data); + irq_set_probe(irq); + + return 0; +} + +static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = rtd1195_mux_irq_domain_map, +}; + +enum rtd1295_iso_isr_bits { + RTD1295_ISO_ISR_UR0_SHIFT = 2, + RTD1295_ISO_ISR_IRDA_SHIFT = 5, + RTD1295_ISO_ISR_I2C0_SHIFT = 8, + RTD1295_ISO_ISR_I2C1_SHIFT = 11, + RTD1295_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1295_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1295_ISO_ISR_GPIOA_SHIFT = 19, + RTD1295_ISO_ISR_GPIODA_SHIFT = 20, + RTD1295_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1295_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1295_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1295_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1295_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1295_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1295_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1295_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1295_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1295_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1295_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1295_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1295_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1295_misc_isr_bits { + RTD1295_ISR_UR1_SHIFT = 3, + RTD1295_ISR_UR1_TO_SHIFT = 5, + RTD1295_ISR_UR2_SHIFT = 8, + RTD1295_ISR_RTC_MIN_SHIFT = 10, + RTD1295_ISR_RTC_HOUR_SHIFT = 11, + RTD1295_ISR_RTC_DATA_SHIFT = 12, + RTD1295_ISR_UR2_TO_SHIFT = 13, + RTD1295_ISR_I2C5_SHIFT = 14, + RTD1295_ISR_I2C4_SHIFT = 15, + RTD1295_ISR_GPIOA_SHIFT = 19, + RTD1295_ISR_GPIODA_SHIFT = 20, + RTD1295_ISR_LSADC0_SHIFT = 21, + RTD1295_ISR_LSADC1_SHIFT = 22, + RTD1295_ISR_I2C3_SHIFT = 23, + RTD1295_ISR_SC0_SHIFT = 24, + RTD1295_ISR_I2C2_SHIFT = 26, + RTD1295_ISR_GSPI_SHIFT = 27, + RTD1295_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1295_ISR_UR1_SHIFT] = BIT(3), + [RTD1295_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1295_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1295_ISR_UR2_SHIFT] = BIT(7), + [RTD1295_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1295_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1295_ISR_RTC_DATA_SHIFT] = BIT(12), + [RTD1295_ISR_I2C5_SHIFT] = BIT(14), + [RTD1295_ISR_I2C4_SHIFT] = BIT(15), + [RTD1295_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_ISR_LSADC0_SHIFT] = BIT(21), + [RTD1295_ISR_LSADC1_SHIFT] = BIT(22), + [RTD1295_ISR_SC0_SHIFT] = BIT(24), + [RTD1295_ISR_I2C2_SHIFT] = BIT(26), + [RTD1295_ISR_GSPI_SHIFT] = BIT(27), + [RTD1295_ISR_I2C3_SHIFT] = BIT(28), + [RTD1295_ISR_FAN_SHIFT] = BIT(29), +}; + +static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, +}; + +static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, +}; + +static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1295-iso-irq-mux", + .data = &rtd1295_iso_irq_mux_info, + }, + { + .compatible = "realtek,rtd1295-misc-irq-mux", + .data = &rtd1295_misc_irq_mux_info, + }, + { + } +}; + +static int __init rtd1195_irq_mux_init(struct device_node *node, + struct device_node *parent) +{ + struct rtd1195_irq_mux_data *data; + const struct of_device_id *match; + const struct rtd1195_irq_mux_info *info; + void __iomem *base; + + match = of_match_node(rtd1295_irq_mux_dt_matches, node); + if (!match) + return -EINVAL; + + info = match->data; + if (!info) + return -EINVAL; + + base = of_iomap(node, 0); + if (!base) + return -EIO; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->info = info; + data->reg_isr = base + info->isr_offset; + data->reg_umsk_isr = base + info->umsk_isr_offset; + data->reg_scpu_int_en = base + info->scpu_int_en_offset; + + data->irq = irq_of_parse_and_map(node, 0); + if (data->irq <= 0) { + kfree(data); + return -EINVAL; + } + + raw_spin_lock_init(&data->lock); + + writel_relaxed(data->scpu_int_en, data->reg_scpu_int_en); + + data->domain = irq_domain_add_linear(node, 32, + &rtd1195_mux_irq_domain_ops, data); + if (!data->domain) { + kfree(data); + return -ENOMEM; + } + + irq_set_chained_handler_and_data(data->irq, rtd1195_mux_irq_handle, data); + + return 0; +} +IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); From patchwork Tue Nov 19 02:19:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179629 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2995ilf; Mon, 18 Nov 2019 18:19:55 -0800 (PST) X-Google-Smtp-Source: APXvYqz+bp9VQ57y/WbYy1p/st01UlkXv2M7DqdrWJH5ke5XUuRn0SwkoRA6+3dZ/OhMnfDtpnPY X-Received: by 2002:a17:906:e110:: with SMTP id gj16mr29283550ejb.124.1574129995476; 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[209.132.180.67]) by mx.google.com with ESMTP id bi17si15170019edb.430.2019.11.18.18.19.55; Mon, 18 Nov 2019 18:19:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727512AbfKSCTw (ORCPT + 26 others); Mon, 18 Nov 2019 21:19:52 -0500 Received: from mx2.suse.de ([195.135.220.15]:58010 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727059AbfKSCTZ (ORCPT ); Mon, 18 Nov 2019 21:19:25 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 5C6F1B328; Tue, 19 Nov 2019 02:19:23 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v4 3/8] arm64: dts: realtek: rtd129x: Add irq muxes and UART interrupts Date: Tue, 19 Nov 2019 03:19:12 +0100 Message-Id: <20191119021917.15917-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add iso and misc IRQ mux DT nodes to RTD129x SoC family. Update the UART DT nodes with interrupts from these muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v3 -> v4: * Rebased onto chip-info and r-bus * Dropped schema-violating second interrupts for UART1 and UART2 v2 -> v3: * Added nodes to rtd129x.dtsi instead of rtd1295.dtsi * Adopted misc compatible string * Renamed node label from irq_mux to misc_irq_mux for clarity v1 -> v2: * Rebased arch/arm64/boot/dts/realtek/rtd129x.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 7d56c9f5d48a..188b4f256917 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -86,6 +86,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1295-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -105,6 +113,8 @@ reg-io-width = <4>; clock-frequency = <27000000>; resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -115,6 +125,14 @@ <0x171d8 0x4>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1295-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -122,6 +140,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR1>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; @@ -132,6 +152,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR2>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <8>; status = "disabled"; }; }; From patchwork Tue Nov 19 02:19:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179623 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2619ilf; Mon, 18 Nov 2019 18:19:30 -0800 (PST) X-Google-Smtp-Source: APXvYqwf/DQ1ZoHyStLYbkOmWijxPCJyoxclhlrsPBHfWAfPYa3tEwLcVm8k0pZyhATS77iFF5WW X-Received: by 2002:a17:906:37cd:: with SMTP id o13mr15648898ejc.148.1574129970763; Mon, 18 Nov 2019 18:19:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574129970; cv=none; d=google.com; s=arc-20160816; b=LPVVaE6kRm5aU7cvruOKCTny9YgUJCD7/vflUJ85SVdGaDMLhcaaXBtw8nfjUTchga niNvBtdLE9vLAaSYT26berLZRI0FyQ33EpvsyzsA39FMJXhp1DIvDhqX+6Aq90Fmy8a2 +tf8JiGYIFobaLFU/NNlS1atpxVkLWCAbmz5DcFq45CGD5cqzGyX3dNlu1MaWEbp+cCN nnePP+Cw45ZPM+VxrACR7+5tDZp41F2Oj757R3KKJrEgUOlJKTUZiMnfeRNIZLoDdwz9 lLQ1+1S4gy3J4MWViSz1z718rYrO4VPGeMaFfWfwUs1QbdlZkOsc41WD+XFCEe49N+u4 C0og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=AvB19tcNs6m+R5Ab/ixZFAmS/0woSBjBjE3vy/YAk3Q=; b=LgYRB/ksuUzBPwJqkUCeIsSv4C/I5zTZ3ttIxsKzfJe/k4Vmg+xMXn2pbPv88yeqiX apdyB5/gS3kG5XvYEjF2abj7Di2FQC79wUszbaKsBv9kMBiiBYQfMu+g3ETZdhoABG9G 5X11HG2YEsY9vH06mkZYuiL80iX2BMjzGA0E53bBHlFdWto8WzPR5AySEW1CqELOhbQM Vh0mJKx7e8IVLUJ1E8Bo1+6nKZFZXxEVTCODGFb9IIOYExw6IkoD7shB87SQJgf4p1sb JQx+9uVnk9ewDGVESYvLVb7ntm5jAxpBCJtcpUPpDwkKGJIVaGWl131VQ4gYB68R2FQc oKzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o19si12630863ejc.315.2019.11.18.18.19.30; Mon, 18 Nov 2019 18:19:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727372AbfKSCT2 (ORCPT + 26 others); Mon, 18 Nov 2019 21:19:28 -0500 Received: from mx2.suse.de ([195.135.220.15]:58028 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727099AbfKSCTZ (ORCPT ); Mon, 18 Nov 2019 21:19:25 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id C52C2B32F; Tue, 19 Nov 2019 02:19:23 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v4 4/8] irqchip: rtd1195-mux: Add RTD1195 definitions Date: Tue, 19 Nov 2019 03:19:13 +0100 Message-Id: <20191119021917.15917-5-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible strings and bit mappings for Realtek RTD1195 SoC. Signed-off-by: Andreas Färber --- v3 -> v4: * Use tabular formatting (Thomas) * Adopt different braces style (Thomas) * Updated with shortened isr_to_int_en_mask callback name (Thomas) * Renamed functions and variables from rtd119x_ to rtd1195_ * Renamed enum values from RTD119X_ to RTD1195_ v3: New drivers/irqchip/irq-rtd1195-mux.c | 101 +++++++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) -- 2.16.4 diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index e6b08438b23c..765d72653383 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1295 IRQ mux + * Realtek RTD1195/RTD1295 IRQ mux * * Copyright (c) 2017-2019 Andreas Färber */ @@ -132,6 +132,81 @@ static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { .map = rtd1195_mux_irq_domain_map, }; +enum rtd1195_iso_isr_bits { + RTD1195_ISO_ISR_TC3_SHIFT = 1, + RTD1195_ISO_ISR_UR0_SHIFT = 2, + RTD1195_ISO_ISR_IRDA_SHIFT = 5, + RTD1195_ISO_ISR_WDOG_NMI_SHIFT = 7, + RTD1195_ISO_ISR_I2C0_SHIFT = 8, + RTD1195_ISO_ISR_TC4_SHIFT = 9, + RTD1195_ISO_ISR_I2C6_SHIFT = 10, + RTD1195_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1195_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1195_ISO_ISR_VFD_WDONE_SHIFT = 14, + RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT = 15, + RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT = 16, + RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT = 17, + RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT = 18, + RTD1195_ISO_ISR_GPIOA_SHIFT = 19, + RTD1195_ISO_ISR_GPIODA_SHIFT = 20, + RTD1195_ISO_ISR_CEC_SHIFT = 22, +}; + +static const u32 rtd1195_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1195_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1195_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1195_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1195_ISO_ISR_I2C6_SHIFT] = BIT(10), + [RTD1195_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1195_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1195_ISO_ISR_VFD_WDONE_SHIFT] = BIT(14), + [RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT] = BIT(15), + [RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT] = BIT(16), + [RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT] = BIT(17), + [RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT] = BIT(18), + [RTD1195_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_ISO_ISR_CEC_SHIFT] = BIT(22), +}; + +enum rtd1195_misc_isr_bits { + RTD1195_MIS_ISR_WDOG_NMI_SHIFT = 2, + RTD1195_MIS_ISR_UR1_SHIFT = 3, + RTD1195_MIS_ISR_I2C1_SHIFT = 4, + RTD1195_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1195_MIS_ISR_TC0_SHIFT = 6, + RTD1195_MIS_ISR_TC1_SHIFT = 7, + RTD1195_MIS_ISR_RTC_HSEC_SHIFT = 9, + RTD1195_MIS_ISR_RTC_MIN_SHIFT = 10, + RTD1195_MIS_ISR_RTC_HOUR_SHIFT = 11, + RTD1195_MIS_ISR_RTC_DATE_SHIFT = 12, + RTD1195_MIS_ISR_I2C5_SHIFT = 14, + RTD1195_MIS_ISR_I2C4_SHIFT = 15, + RTD1195_MIS_ISR_GPIOA_SHIFT = 19, + RTD1195_MIS_ISR_GPIODA_SHIFT = 20, + RTD1195_MIS_ISR_LSADC_SHIFT = 21, + RTD1195_MIS_ISR_I2C3_SHIFT = 23, + RTD1195_MIS_ISR_I2C2_SHIFT = 26, + RTD1195_MIS_ISR_GSPI_SHIFT = 27, +}; + +static const u32 rtd1195_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1195_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1195_MIS_ISR_I2C1_SHIFT] = BIT(4), + [RTD1195_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1195_MIS_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1195_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1195_MIS_ISR_RTC_DATE_SHIFT] = BIT(12), + [RTD1195_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1195_MIS_ISR_I2C4_SHIFT] = BIT(15), + [RTD1195_MIS_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_MIS_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_MIS_ISR_LSADC_SHIFT] = BIT(21), + [RTD1195_MIS_ISR_I2C2_SHIFT] = BIT(26), + [RTD1195_MIS_ISR_GSPI_SHIFT] = BIT(27), + [RTD1195_MIS_ISR_I2C3_SHIFT] = BIT(28), +}; + enum rtd1295_iso_isr_bits { RTD1295_ISO_ISR_UR0_SHIFT = 2, RTD1295_ISO_ISR_IRDA_SHIFT = 5, @@ -202,6 +277,13 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_ISR_FAN_SHIFT] = BIT(29), }; +static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1195_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_offset = 0x0, .umsk_isr_offset = 0x4, @@ -209,6 +291,13 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1195_misc_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .umsk_isr_offset = 0x8, .isr_offset = 0xc, @@ -217,10 +306,18 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { }; static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1195-iso-irq-mux", + .data = &rtd1195_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1195-misc-irq-mux", + .data = &rtd1195_misc_irq_mux_info, + }, { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, @@ -279,5 +376,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, return 0; } +IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); From patchwork Tue Nov 19 02:19:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179627 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2847ilf; Mon, 18 Nov 2019 18:19:45 -0800 (PST) X-Google-Smtp-Source: APXvYqy3wbis5d9gHjxOE6PRTTeU0Krko4zAYLyZBWQ4oHmdxEYX0lB6DW3ztYgyu6zfv7mAZDa7 X-Received: by 2002:a17:906:3710:: with SMTP id d16mr11832683ejc.132.1574129984921; Mon, 18 Nov 2019 18:19:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574129984; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id k4si12783435eji.269.2019.11.18.18.19.44; Mon, 18 Nov 2019 18:19:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727470AbfKSCTi (ORCPT + 26 others); Mon, 18 Nov 2019 21:19:38 -0500 Received: from mx2.suse.de ([195.135.220.15]:58036 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726761AbfKSCT0 (ORCPT ); Mon, 18 Nov 2019 21:19:26 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 359A4B330; Tue, 19 Nov 2019 02:19:24 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v4 5/8] ARM: dts: rtd1195: Add irq muxes and UART interrupts Date: Tue, 19 Nov 2019 03:19:14 +0100 Message-Id: <20191119021917.15917-6-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add iso and misc IRQ mux DT nodes for the Realtek RTD1195 SoC. Update the UART DT nodes with interrupts from those muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v4: New arch/arm/boot/dts/rtd1195.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.16.4 diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index db1171c5adfa..ee7761ae4ee0 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -118,6 +118,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1195-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -137,6 +145,8 @@ reg-io-width = <4>; resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; clock-frequency = <27000000>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -145,6 +155,14 @@ reg = <0x1a200 0x8>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1195-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -152,6 +170,8 @@ reg-io-width = <4>; resets = <&reset2 RTD1195_RSTN_UR1>; clock-frequency = <27000000>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; }; From patchwork Tue Nov 19 02:19:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179628 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2902ilf; Mon, 18 Nov 2019 18:19:48 -0800 (PST) X-Google-Smtp-Source: APXvYqz3PkPZ7KtSpTapBHJPtPj80N9qJYo2eahKzHkOmWmaBhahME4KvyRZjM5Ppxbp6cSBv1WA X-Received: by 2002:a17:906:240c:: with SMTP id z12mr31412340eja.35.1574129988709; Mon, 18 Nov 2019 18:19:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574129988; cv=none; d=google.com; s=arc-20160816; b=dQyqojK3MIm+ahd0FbIpJuQb1wCNXWK2OuawE0hkk4cx4gwY1uZNfB8aiN8Gaicwyh BNkELYaYmicZIFcOb3nw3JZEenpPcmrFNiqehHcPviL8Ul4/8bLH9KY2QRgeh7GVQp10 aEFfw7vdrTFt/CCb421fBrLTQxMcQl6ilEResYhq5qF3Yl1jL1UibLNEWa7iNKzhfzF5 E3EnNfnGr8+iDV1CMWAO4tcqj234qZ6NaCzxSlG46W5miKwZLBTFoKGHNoDhvpgqQ8IS /JfHkY8eF18p4J6fCS5nNpX3iabQtKfCN4X97EL1acSg/oZhh1SkPQzy9QRA0NV7F77e eXnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ZT+D5CUuvHiw5aH14mN+YC4FJkMmDk20dyKfXLu0nDI=; b=ek8d1sUjC5SZCUwAP/fDW4RFMREVe2JPsaxpBtTYP5PeLHun6u1u+qgNsLbMSClPLw +KWnS6TxNHCmIudUIYSEOhb6sSWFccGrFFKseUkz5OB603bo9+5+0lnQGiG2fuprJNu5 +GQBefA5U0F7fp7myHfge0hDbY3PqbArYXzH+oTfe5jEKxF0BpkjBRjc6+00wVnwNCzr acQ/7Qp/x225RY2if5ycQNmwdc1dRjh+F12XdSg5OHAr49lFA05db0lxhGuErHur3RgH 8fLED4DJuhxXnXOKdrzVMQDr4RP2NHmE87ZgGwkHY2p2Uj3LQz9NyBNeJQ2KsS4oc5bA SvLw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e4si12912082ejx.214.2019.11.18.18.19.48; Mon, 18 Nov 2019 18:19:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727445AbfKSCTh (ORCPT + 26 others); Mon, 18 Nov 2019 21:19:37 -0500 Received: from mx2.suse.de ([195.135.220.15]:58050 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727298AbfKSCT0 (ORCPT ); Mon, 18 Nov 2019 21:19:26 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id A7D12B331; Tue, 19 Nov 2019 02:19:24 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v4 6/8] dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395 Date: Tue, 19 Nov 2019 03:19:15 +0100 Message-Id: <20191119021917.15917-7-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible strings for Realtek RTD1395 SoC. Signed-off-by: Andreas Färber --- v4: New .../devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml | 2 ++ 1 file changed, 2 insertions(+) -- 2.16.4 diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml index 5cf3a28cedba..7c2a31548d46 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml @@ -19,6 +19,8 @@ properties: - realtek,rtd1195-iso-irq-mux - realtek,rtd1295-misc-irq-mux - realtek,rtd1295-iso-irq-mux + - realtek,rtd1395-misc-irq-mux + - realtek,rtd1395-iso-irq-mux reg: maxItems: 1 From patchwork Tue Nov 19 02:19:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 179626 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2832ilf; Mon, 18 Nov 2019 18:19:43 -0800 (PST) X-Google-Smtp-Source: APXvYqzs1jOzdkDCslxrIhzJHkCSW4K2AW33+ZNvClXBo2hIRyOUtbw5tu5EuJ1G6/SkdB6ybT8c X-Received: by 2002:a17:906:938d:: with SMTP id l13mr31569971ejx.74.1574129983777; Mon, 18 Nov 2019 18:19:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574129983; cv=none; d=google.com; s=arc-20160816; b=NQE3q8bOrAvWdXVK5NQ96Y3xJTcRHCIBUnvPqfi1ilYxZGnEvcbW8tCS8U5Mux2qho h4i/Mr5A2iVRxRpwFKjAefhD/Dn17L2BVM64csQb1MIhi8cCQ87D5McSikAw40c+O/KY vfOVVMDRu357c8USOYmW2wb2aQJuHZhDJtaDcA0SWvtP0UrrUyhpy7z2tacoRiHl5PZH v82qwKNElrStTMRX0+RDfc2BCH8i7WNCJgX7WaTFPswfwcVsrl3D8sV9yfr+xPBZsUPV 8CeAqS7uM+WkjGQG2YqKDIdxxtVvMxAoNqCy9m8qwGn6SmRhnIA6WuYnfE3WPIqIsfGM 7vjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=paWAMCPM/xZtp239FM7hnFKQDYOJyD0w/j61+sNBvfs=; b=elRXkGn1bdDm0bX3p8+GNcizuXfq07kLSt5fJzNoDKaqZ4wKyxq77vwiOmZlYuCCqD bSAzBB/PlvUAE8P9b5kDHh6n21HKW4A9NL+gVO1B7bbHxVxntoR85CVgg4tVlrXLVNSh oV2Y7/AvhFEKcjcKYKl1RIPeeOk2UuCethIcshlVErGwpiBs8uGEpmMlZGXh8bIcT6xg dBi4HMz9PblCNsUOMI1iSHKvjsazYVkiQs6/y8e+UQL+SWenBwsGLXx3xErzvHwrIQrm XQHSoWd3ZEw24OCOnX0rOwK4BOWFJPkTK8k+LIa+kb17nJPslPOIVDBuk3aV16A4n+gv xhow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k4si12783435eji.269.2019.11.18.18.19.43; Mon, 18 Nov 2019 18:19:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727491AbfKSCTj (ORCPT + 26 others); Mon, 18 Nov 2019 21:19:39 -0500 Received: from mx2.suse.de ([195.135.220.15]:58058 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726952AbfKSCT0 (ORCPT ); Mon, 18 Nov 2019 21:19:26 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 1869FB335; Tue, 19 Nov 2019 02:19:25 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v4 7/8] irqchip: rtd1195-mux: Add RTD1395 definitions Date: Tue, 19 Nov 2019 03:19:16 +0100 Message-Id: <20191119021917.15917-8-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible strings and bit mappings for Realtek RTD1395 SoC. Based on BPI-M4-bsp linux-rtk/drivers/irqchip/irq-rtd139x.h. Signed-off-by: Andreas Färber --- v4: New drivers/irqchip/irq-rtd1195-mux.c | 83 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) -- 2.16.4 diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index 765d72653383..ad4b0ef3071b 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1195/RTD1295 IRQ mux + * Realtek RTD1195/RTD1295/RTD1395 IRQ mux * + * Copyright (C) 2017 Realtek Semiconductor Corporation * Copyright (c) 2017-2019 Andreas Färber */ @@ -277,6 +278,62 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_ISR_FAN_SHIFT] = BIT(29), }; +enum rtd1395_iso_isr_bits { + RTD1395_ISO_ISR_UR0_SHIFT = 2, + RTD1395_ISO_ISR_IRDA_SHIFT = 5, + RTD1395_ISO_ISR_I2C0_SHIFT = 8, + RTD1395_ISO_ISR_I2C1_SHIFT = 11, + RTD1395_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1395_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1395_ISO_ISR_LSADC0_SHIFT = 16, + RTD1395_ISO_ISR_LSADC1_SHIFT = 17, + RTD1395_ISO_ISR_GPIOA_SHIFT = 19, + RTD1395_ISO_ISR_GPIODA_SHIFT = 20, + RTD1395_ISO_ISR_GPHY_HV_SHIFT = 28, + RTD1395_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1395_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1395_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1395_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1395_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1395_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1395_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1395_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1395_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1395_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1395_ISO_ISR_LSADC0_SHIFT] = BIT(16), + [RTD1395_ISO_ISR_LSADC1_SHIFT] = BIT(17), + [RTD1395_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1395_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1395_ISO_ISR_GPHY_HV_SHIFT] = BIT(28), + [RTD1395_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1395_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1395_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1395_misc_isr_bits { + RTD1395_MISC_ISR_UR1_SHIFT = 3, + RTD1395_MISC_ISR_UR1_TO_SHIFT = 5, + RTD1395_MISC_ISR_UR2_SHIFT = 8, + RTD1395_MISC_ISR_UR2_TO_SHIFT = 13, + RTD1395_MISC_ISR_I2C5_SHIFT = 14, + RTD1395_MISC_ISR_SC0_SHIFT = 24, + RTD1395_MISC_ISR_SPI_SHIFT = 27, + RTD1395_MISC_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1395_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1395_MISC_ISR_UR1_SHIFT] = BIT(3), + [RTD1395_MISC_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1395_MISC_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1395_MISC_ISR_UR2_SHIFT] = BIT(7), + [RTD1395_MISC_ISR_I2C5_SHIFT] = BIT(14), + [RTD1395_MISC_ISR_SC0_SHIFT] = BIT(24), + [RTD1395_MISC_ISR_SPI_SHIFT] = BIT(27), + [RTD1395_MISC_ISR_FAN_SHIFT] = BIT(29), +}; + static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { .isr_offset = 0x0, .umsk_isr_offset = 0x4, @@ -291,6 +348,13 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_iso_irq_mux_info = { + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1395_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { .umsk_isr_offset = 0x8, .isr_offset = 0xc, @@ -305,6 +369,13 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_misc_irq_mux_info = { + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1395_misc_isr_to_scpu_int_en_mask, +}; + static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { { .compatible = "realtek,rtd1195-iso-irq-mux", @@ -314,6 +385,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-iso-irq-mux", + .data = &rtd1395_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1195-misc-irq-mux", .data = &rtd1195_misc_irq_mux_info, @@ -322,6 +397,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-misc-irq-mux", + .data = &rtd1395_misc_irq_mux_info, + }, { } }; @@ -378,5 +457,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, } IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_iso_mux, "realtek,rtd1395-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_misc_mux, "realtek,rtd1395-misc-irq-mux", rtd1195_irq_mux_init);