From patchwork Mon Sep 16 06:42:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang <18771902331@163.com> X-Patchwork-Id: 829052 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D32CB4120B; Mon, 16 Sep 2024 06:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469145; cv=none; b=gOztd+T559jPv6UkNacN1mdLsvl3dd4bUNSaJIX6gytSj7gMwJn4zUhUyXOFQpOmP5OnOLlmt25+zMmg7pfLgsqhSP/YZbQhRtWMfuXVzCPE79cYj8dJYM1arSu0FIBnF0f+1zQMMnTbIhuOzSAy7ZrJ73r8fS5jsrvYEg1pvb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469145; c=relaxed/simple; bh=jAwSw4LEIfXT39XmNvQkkX3/1clNMqBMeMdEHqSLLuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XwLrVYJQO9ckb7UN33sI/4EAf9kCDL2BvWHsQmSYAMhqoo3C5e+OHO+1QMkhzkSaZD+av2OprpNsCOMtRu51rRiRYN9gkdg41XDvGUvFWRd0XvPin02pALDwGxXDH/Wj4hQdzLruQstSriXr0vff798gafxwGGqPJ5ZJWl27lis= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=ELcD2D9i; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ELcD2D9i" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-ID:MIME-Version; bh=H5SO/ a1hfbyVpeTzy2AAy5aKvwSqfgsGs2lOMb5bsec=; b=ELcD2D9iTL4cSN5SxjBh6 BXgHtcjXd3q1Snt6RNk4YaZOuu2naSd+v2aGVrwlnyZTvk4kirg61qdU9m2/J6bd WHwF+zo+k9Z/u6AEiRrnVJRe/mY9XlCJVCu5W9h85pwJhnwxN7fme/EkWBGbZUcX 4hclGhEXcFJ5oq7C1CoeVY= Received: from jean.localdomain (unknown [27.18.168.209]) by gzga-smtp-mta-g3-3 (Coremail) with SMTP id _____wDXX36b0+dmVfTnDg--.31141S2; Mon, 16 Sep 2024 14:43:39 +0800 (CST) From: Ze Huang <18771902331@163.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Ze Huang <18771902331@163.com>, Yangyu Chen Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RESEND PATCH 1/3] dt-bindings: pinctrl: Add support for canaan, k230 SoC Date: Mon, 16 Sep 2024 14:42:23 +0800 Message-ID: <20240916064225.316863-1-18771902331@163.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240916063021.311721-1-18771902331@163.com> References: <20240916063021.311721-1-18771902331@163.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDXX36b0+dmVfTnDg--.31141S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxuF17Cr1xuw1rZr4rAryfXrb_yoWrJFyxpF ZxKa98KF1rWF47K3yfta18uF13Xa1kArsagw1Utry7tw45WF18Kr1akr4IvF4DWFn7J3Wa qFWIgry7KF47Ar7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piL0ePUUUUU= X-CM-SenderInfo: zpryllqrzqjjitr6il2tof0z/1tbiJwBcomXAn1YeJAAAsP Add device tree binding details for Canaan K230 pinctrl device. Signed-off-by: Ze Huang <18771902331@163.com> --- .../bindings/pinctrl/canaan,k230-pinctrl.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml new file mode 100644 index 000000000000..979c5bd71e3d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Pin Controller + +maintainers: + - Ze Huang <18771902331@163.com> + +description: + The Canaan Kendryte K230 platform includes 64 IO pins, each capable of + multiplexing up to 5 different functions. Pin function configuration is + performed on a per-pin basis. + +properties: + compatible: + const: canaan,k230-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-cfg$': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias, input + enable/disable, input schmitt trigger, slew-rate enable/disable, + slew-rate, drive strength. + + properties: + pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + The list of GPIOs and their mux settings that properties in + the node apply to. This should be set with the macro + 'K230_PINMUX(pin, mode)' + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + minimum: 0 + maximum: 15 + + input-enable: true + + output-enable: true + + input-schmitt-enable: true + + slew-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + slew rate control enable + 0: disable + 1: enable + + enum: [0, 1] + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specifies the power source voltage for the IO bank that the + pin belongs to. Each bank of IO pins operate at a specific, + fixed voltage levels. Incorrect voltage configuration can + damage the chip. The defined constants represent the + possible voltage configurations: + + - K230_MSC_3V3 (value 0): 3.3V power supply + - K230_MSC_1V8 (value 1): 1.8V power supply + + The following banks have the corresponding voltage + configurations: + + - bank IO0 to IO1: Fixed at 1.8V + - bank IO2 to IO13: Fixed at 1.8V + - bank IO14 to IO25: Fixed at 1.8V + - bank IO26 to IO37: Fixed at 1.8V + - bank IO38 to IO49: Fixed at 1.8V + - bank IO50 to IO61: Fixed at 3.3V + - bank IO62 to IO63: Fixed at 1.8V + + enum: [0, 1] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl: pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x91105000 0x100>; + + uart2_pins: uart2-pins { + uart2-pins-cfg { + pinmux = <0x503>, /* uart2 txd */ + <0x603>; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = <1>; + input-enable; + output-enable; + bias-disable; + }; + }; + }; From patchwork Mon Sep 16 06:47:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang <18771902331@163.com> X-Patchwork-Id: 829051 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 61EC377F01; Mon, 16 Sep 2024 06:49:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469355; cv=none; b=PoJmcEf1VxelKj6Y+VaOU3a2k5pZGavO6WJ/fAejb/bwNdosQEKXdqDQ9fInmebnQLgX3pJ12qynkrzkNiTmD9FPXuepoBwZAhcEfVkF/BpAvNgXHmnKKuGo1yUT4VoaS1fOv2sERm9992Hf80wZDlZcmOJCM5TJIfYp2FALF6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469355; c=relaxed/simple; bh=OuCf5XtUpLEJAaXpvuO13tnAB9M9h8/21ajr7rCfodA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N8W9QrgS3PYQGxuXNjIrKF6qYjJjiwK9oW9bMPOaJUDmTQFKNue1VVcUrT52xr57WqrQZbC4grtXOmCCKuwfrWkKjVqNbpO6GaYXN7rD8y/elEQMBlw5O4X6zegvb67vdiF7keGFc0zcjUTBRjK7gsgLEZggltaPYLLuVL9lmPA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=B8Xgwcoo; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="B8Xgwcoo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-ID:MIME-Version; bh=JOP8q SR7Z3yhaJZZrM54f9DxjIHXIEkaJJZCRMA+NSQ=; b=B8XgwcooT3tZy456I8T6E 2Xa/rMuLaQE1GqK7drij3MRffnHdtA3yQBUeqRugXjkv5CIzMYBdN4hPCEiTjBzx 0FcWEd3b497RwjwFpHvlNKSCpKDcivbSWOFyzvAVn+AdCTGoKUgm6HJxYCtLJCtO IuwbeTzlmd5hkYPQJs7fyk= Received: from jean.localdomain (unknown [27.18.168.209]) by gzga-smtp-mta-g2-4 (Coremail) with SMTP id _____wDHD2du1OdmyQfeBg--.30056S3; Mon, 16 Sep 2024 14:47:13 +0800 (CST) From: Ze Huang <18771902331@163.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Ze Huang <18771902331@163.com>, Yangyu Chen Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RESEND PATCH 3/3] riscv: dts: canaan: Add k230's pinctrl node Date: Mon, 16 Sep 2024 14:47:05 +0800 Message-ID: <20240916064706.318793-2-18771902331@163.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240916063021.311721-1-18771902331@163.com> References: <20240916063021.311721-1-18771902331@163.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDHD2du1OdmyQfeBg--.30056S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxtw15Ww1DXr4Dtr4fKF1UAwb_yoW3ZF1xpF WS9rn3K34j9rWrK3y0vr1jgF1UWF4q9r1rK3srKry7tw10gFs5K3s5Cr1YqFn8ur1Yk34j g395Zw4Ivrs7JwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRvPfLUUUUU= X-CM-SenderInfo: zpryllqrzqjjitr6il2tof0z/1tbiNwBcomXAnRlTLAADsU Add pinctrl device, containing default config for uart, pwm, iis, iic and mmc. Signed-off-by: Ze Huang <18771902331@163.com> --- arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi | 316 +++++++++++++++++++ arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ arch/riscv/boot/dts/canaan/k230.dtsi | 2 + 3 files changed, 336 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi new file mode 100644 index 000000000000..0737f50d2868 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ +#include "k230-pinctrl.h" + +/ { + soc { + pinctrl: pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x0 0x91105000 0x0 0x100>; + + jtag_pins: jtag-pins { + jtag-tck-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-pull-down; + input-schmitt-enable; + }; + + jtag-tdi-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-disable; + }; + + jtag-tdo-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + jtag-tms-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + uart2-pins-cfg { + pinmux = , /* uart2 txd */ + ; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + output-enable; + bias-disable; + }; + }; + + pwm2_pins: pwm2-pins { + pwm2-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm3_pins: pwm3-pins { + pwm3-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm4_pins: pwm4-pins { + pwm4-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iis_pins: iis-pins { + iis-clk-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + iis-ws-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + iis-din0-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-disable; + }; + + iis-dout0-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + }; + + uart4_pins: uart4-pins { + uart4-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart4-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart0-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iic1_pins: iic1-pins { + iic1-pins-cfg { + pinmux = , /* iic1 scl */ + ; /* iic1 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic3_pins: iic3-pins { + iic3-pins-cfg { + pinmux = , /* iic3 scl */ + ; /* iic3 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic4_pins: iic4-pins { + iic4-pins-cfg { + pinmux = , /* iic4 scl */ + ; /* iic4 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic0_pins: iic0-pins { + iic0-pins-cfg { + pinmux = , /* iic0 scl */ + ; /* iic0 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart3_pins: uart3-pins { + uart3-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart3-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + key_pins: key-pins { + key-pins-cfg { + pinmux = , /* key0 */ + ; /* key1 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + mmc1_pins: mmc1-pins { + mmc1-cmd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + + mmc1-clk-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + mmc1-data-cfg { + pinmux = , /* mmc1 data0 */ + , /* mmc1 data1 */ + , /* mmc1 data2 */ + ; /* mmc1 data3 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.h b/arch/riscv/boot/dts/canaan/k230-pinctrl.h new file mode 100644 index 000000000000..f240a980f37a --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.h @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright (C) 2024 Canaan Bright Sight Co. Ltd + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ + +#ifndef _K230_PINCTRL_H +#define _K230_PINCTRL_H + +#define K230_MSC_3V3 0 +#define K230_MSC_1V8 1 + +#define BANK_VOLTAGE_DEFAULT K230_MSC_1V8 +#define BANK_VOLTAGE_IO50_IO61 K230_MSC_3V3 + +#define K230_PINMUX(pin, mode) (((pin) << 8) | (mode)) + +#endif /* _K230_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 95c1a3d8fb11..a9354e538642 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -140,3 +140,5 @@ uart4: serial@91404000 { }; }; }; + +#include "k230-pinctrl.dtsi"