From patchwork Mon Sep 16 13:49:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 829211 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6FE819307D for ; Mon, 16 Sep 2024 13:57:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495053; cv=none; b=BYFiM914MiGYTEz4eDf0B2z0OXd9OYWhG+HRbIDpL3tAVkTwb8rCw3cTajEX/G6jOM+hwXq15hBFtTelYe4E57tUXmNi9rZTE1E5080duNhW+fe7c7bw/luYFjq6lI3+YfWnLzcPlaA2QHpQkXkudmXkSdwBv6ejGJmmdGIYolY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495053; c=relaxed/simple; bh=oP9fekxxhgLh5eDAfrpQ0Wb4R1ndMDvhopfdC546kPM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kUtlZmFuu2LNfE/eTWTkxBa3oc+J1mWKZmMHsZTR0X5OeLPjxv5M10ElxdRJryd+oMJqcKPGNPq5K8rw4Aaq14jRwmgI7PtcMZynFaOaU5Je8QioqbY6QyDh1TbOU0c1mncgjPxERycF7gyiavvde0x8PMykkxhBT6rXCoZQLD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KSm4cmP8; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KSm4cmP8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726495052; x=1758031052; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oP9fekxxhgLh5eDAfrpQ0Wb4R1ndMDvhopfdC546kPM=; b=KSm4cmP8yIS/qeQWyJ8aaKbX/aHnNEQeHkyXGOiWcKneNSFdtyoRhd7j qFMNJEWieGc/hyhevNc+SEIZJZ/2fDs6tsDDNi8+cC9mEAuq3lOWWGgTU gJBdZKsjdc5W2NcEwFGol+Td6X9Ota3y55rIBt2JzMBLHeRORbyPFPTxu 0Lpp9Hlwm2ch12ZGn77GGTus1mr0u0YB+9qzuN/Ir7cfAlBGESM0+5usC AzriK76KHey3EfuwLwwFdYTv1wTwZMOh91mUrFz1Sq/wYgnRc/9klFEIy tPHA0oOmiWQPR9ggtprl97EWtpVR1lHxNAa7eqnxnmz3U5izc9Z6nmmg5 g==; X-CSE-ConnectionGUID: 4CouyvkEQJyrnrftGm2qKQ== X-CSE-MsgGUID: Xtj5RedpRa+Yus1rUec44g== X-IronPort-AV: E=McAfee;i="6700,10204,11197"; a="36666776" X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="36666776" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:31 -0700 X-CSE-ConnectionGUID: c8Q9oLFVQaaVBMZZAxpaTQ== X-CSE-MsgGUID: DVCQM+5+RD6VUi/JG/MB4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="68837281" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:27 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 01/12] spi: add driver for intel graphics on-die spi device Date: Mon, 16 Sep 2024 16:49:17 +0300 Message-Id: <20240916134928.3654054-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add auxiliary driver for intel discrete graphics on-die spi device. CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- MAINTAINERS | 7 ++ drivers/spi/Kconfig | 11 +++ drivers/spi/Makefile | 1 + drivers/spi/spi-intel-dg.c | 142 +++++++++++++++++++++++++++++++ include/linux/intel_dg_spi_aux.h | 27 ++++++ 5 files changed, 188 insertions(+) create mode 100644 drivers/spi/spi-intel-dg.c create mode 100644 include/linux/intel_dg_spi_aux.h diff --git a/MAINTAINERS b/MAINTAINERS index 333ed0718175..b2c1aa743bc6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11214,6 +11214,13 @@ L: linux-kernel@vger.kernel.org S: Supported F: arch/x86/include/asm/intel-family.h +INTEL DISCRETE GRAPHIC SPI FLASH DRIVER +M: Alexander Usyskin +L: linux-spi@vger.kernel.org +S: Supported +F: drivers/spi/spi-intel-dg.c +F: include/linux/intel_dg_spi_aux.h + INTEL DRM DISPLAY FOR XE AND I915 DRIVERS M: Jani Nikula M: Rodrigo Vivi diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ec1550c698d5..95d6667dc127 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -524,6 +524,17 @@ config SPI_INTEL_PLATFORM To compile this driver as a module, choose M here: the module will be called spi-intel-platform. +config SPI_INTEL_DG + tristate "Intel Discrete Graphic SPI flash driver" + depends on AUXILIARY_BUS + depends on MTD + help + This enables support for Intel Discrete Graphic SPI + auxiliary device. + + To compile this driver as a module, choose M here: the module + will be called spi-intel-dg. + config SPI_JCORE tristate "J-Core SPI Master" depends on OF && (SUPERH || COMPILE_TEST) diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index a9b1bc259b68..ae8398930f3b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_INGENIC) += spi-ingenic.o obj-$(CONFIG_SPI_INTEL) += spi-intel.o obj-$(CONFIG_SPI_INTEL_PCI) += spi-intel-pci.o obj-$(CONFIG_SPI_INTEL_PLATFORM) += spi-intel-platform.o +obj-$(CONFIG_SPI_INTEL_DG) += spi-intel-dg.o obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o obj-$(CONFIG_SPI_JCORE) += spi-jcore.o obj-$(CONFIG_SPI_LJCA) += spi-ljca.o diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c new file mode 100644 index 000000000000..4e302957f077 --- /dev/null +++ b/drivers/spi/spi-intel-dg.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct intel_dg_spi { + struct kref refcnt; + void __iomem *base; + size_t size; + unsigned int nregions; + struct { + const char *name; + u8 id; + u64 offset; + u64 size; + } regions[]; +}; + +static void intel_dg_spi_release(struct kref *kref) +{ + struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt); + int i; + + pr_debug("freeing spi memory\n"); + for (i = 0; i < spi->nregions; i++) + kfree(spi->regions[i].name); + kfree(spi); +} + +static int intel_dg_spi_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *aux_dev_id) +{ + struct intel_dg_spi_dev *ispi = auxiliary_dev_to_intel_dg_spi_dev(aux_dev); + struct device *device; + struct intel_dg_spi *spi; + unsigned int nregions; + unsigned int i, n; + size_t size; + char *name; + size_t name_size; + int ret; + + device = &aux_dev->dev; + + /* count available regions */ + for (nregions = 0, i = 0; i < INTEL_DG_SPI_REGIONS; i++) { + if (ispi->regions[i].name) + nregions++; + } + + if (!nregions) { + dev_err(device, "no regions defined\n"); + return -ENODEV; + } + + size = sizeof(*spi) + sizeof(spi->regions[0]) * nregions; + spi = kzalloc(size, GFP_KERNEL); + if (!spi) + return -ENOMEM; + + kref_init(&spi->refcnt); + + spi->nregions = nregions; + for (n = 0, i = 0; i < INTEL_DG_SPI_REGIONS; i++) { + if (ispi->regions[i].name) { + name_size = strlen(dev_name(&aux_dev->dev)) + + strlen(ispi->regions[i].name) + 2; /* for point */ + name = kzalloc(name_size, GFP_KERNEL); + if (!name) + continue; + snprintf(name, name_size, "%s.%s", + dev_name(&aux_dev->dev), ispi->regions[i].name); + spi->regions[n].name = name; + spi->regions[n].id = i; + n++; + } + } + + spi->base = devm_ioremap_resource(device, &ispi->bar); + if (IS_ERR(spi->base)) { + dev_err(device, "mmio not mapped\n"); + ret = PTR_ERR(spi->base); + goto err; + } + + dev_set_drvdata(&aux_dev->dev, spi); + + return 0; + +err: + kref_put(&spi->refcnt, intel_dg_spi_release); + return ret; +} + +static void intel_dg_spi_remove(struct auxiliary_device *aux_dev) +{ + struct intel_dg_spi *spi = dev_get_drvdata(&aux_dev->dev); + + if (!spi) + return; + + dev_set_drvdata(&aux_dev->dev, NULL); + + kref_put(&spi->refcnt, intel_dg_spi_release); +} + +static const struct auxiliary_device_id intel_dg_spi_id_table[] = { + { + .name = "i915.spi", + }, + { + .name = "xe.spi", + }, + { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(auxiliary, intel_dg_spi_id_table); + +static struct auxiliary_driver intel_dg_spi_driver = { + .probe = intel_dg_spi_probe, + .remove = intel_dg_spi_remove, + .driver = { + /* auxiliary_driver_register() sets .name to be the modname */ + }, + .id_table = intel_dg_spi_id_table +}; + +module_auxiliary_driver(intel_dg_spi_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_DESCRIPTION("Intel DGFX SPI driver"); diff --git a/include/linux/intel_dg_spi_aux.h b/include/linux/intel_dg_spi_aux.h new file mode 100644 index 000000000000..d4c3830d56d6 --- /dev/null +++ b/include/linux/intel_dg_spi_aux.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_DG_SPI_AUX_H__ +#define __INTEL_DG_SPI_AUX_H__ + +#include + +#define INTEL_DG_SPI_REGIONS 13 + +struct intel_dg_spi_region { + const char *name; +}; + +struct intel_dg_spi_dev { + struct auxiliary_device aux_dev; + bool writeable_override; + struct resource bar; + const struct intel_dg_spi_region *regions; +}; + +#define auxiliary_dev_to_intel_dg_spi_dev(auxiliary_dev) \ + container_of(auxiliary_dev, struct intel_dg_spi_dev, aux_dev) + +#endif /* __INTEL_DG_SPI_AUX_H__ */ From patchwork Mon Sep 16 13:49:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 829210 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C623158A3C for ; Mon, 16 Sep 2024 13:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495064; cv=none; b=op4w8LKyXTcYGJKeDO/sIEIM997cBxy2Jinp2GRtdvv9A1S2RcxOJnXeDBkB7kI65l3py1fY+dQnSNo7ibfm7P6hN5pMlL247bVi8Ta/IoDBTgysReszUtbVYOyj+I9gNvnRrgfaV1Jfh2gfltHYhcPvtplpWm5Y0WZi/4UXvL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495064; c=relaxed/simple; bh=t8/zR6wZpeIic8DqQVjxZX/IQw1gAwaQkNY4aBe1tn4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kZ9HCp8vG5y89EMMrMEzzbXlIG9jE+yi4Qw2ErIeIH3QP57xU1UTfk4jQvqmBSzSynn/OtqzoNMB+1IAj3bLGSzXxMAmDVkGBgmT2c4JNFfbMrvwjZiwtESvKv+wqjtL+y5TZpwnn3MdoYjsL8alPkgDgzMiU3eTT1/6eZsMuJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=P6Sf3R4t; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P6Sf3R4t" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726495062; x=1758031062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t8/zR6wZpeIic8DqQVjxZX/IQw1gAwaQkNY4aBe1tn4=; b=P6Sf3R4tVBrdJxkul31ofLWci+S4hNi+p/EjtylSt9AgiI/ulFeYyH/f MY9rODKRxLcon8UIDbU9Y8/JBGT7rwY2mexk9xu/KQKWecfretqYphvsG eDQIsKK2AVCDhhVKNLw+vIbrCR2ceU6MR9BJtlA9Jc74+OtreVAVODEby 5XFNjvWp8rku0CkmuwsTya4S+MqBDhJKE/LYlvnhVw62/Zq1uNmjLMAWE zx2Te7rXKtq/A9VowVAqJ3qKcxJz+YXnoRPbGvR9Dw26gj4NXs1+9eW30 aXhKP+P2xMCCGteetnj68+z9DuzdV6F22UGQ1xnJVkNtoBYQ2pYI7VslC A==; X-CSE-ConnectionGUID: igAEQDfZQtWSYsexKpj9rA== X-CSE-MsgGUID: leo54ivhTMS41QsCDhvxlA== X-IronPort-AV: E=McAfee;i="6700,10204,11197"; a="36666808" X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="36666808" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:42 -0700 X-CSE-ConnectionGUID: rnAjHPdkTBCsdbN/1M3ePA== X-CSE-MsgGUID: /pwYD2pPRSixgNrBuzboPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="68837313" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:37 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 03/12] spi: intel-dg: implement spi access functions Date: Mon, 16 Sep 2024 16:49:19 +0300 Message-Id: <20240916134928.3654054-4-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Tomas Winkler Implement spi_read(), spi_erase() and spi_write() functions. CC: Lucas De Marchi CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/spi/spi-intel-dg.c | 199 +++++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c index 661e5189fa58..863898c8739c 100644 --- a/drivers/spi/spi-intel-dg.c +++ b/drivers/spi/spi-intel-dg.c @@ -3,13 +3,16 @@ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. */ +#include #include #include #include +#include #include #include #include #include +#include #include struct intel_dg_spi { @@ -84,6 +87,33 @@ static inline u32 spi_read32(struct intel_dg_spi *spi, u32 address) return ioread32(base + SPI_TRIGGER_REG); } +static inline u64 spi_read64(struct intel_dg_spi *spi, u32 address) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + return readq(base + SPI_TRIGGER_REG); +} + +static void spi_write32(struct intel_dg_spi *spi, u32 address, u32 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + iowrite32(data, base + SPI_TRIGGER_REG); +} + +static void spi_write64(struct intel_dg_spi *spi, u32 address, u64 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + writeq(data, base + SPI_TRIGGER_REG); +} + static int spi_get_access_map(struct intel_dg_spi *spi) { u32 flmap1; @@ -140,6 +170,175 @@ static int intel_dg_spi_is_valid(struct intel_dg_spi *spi) return 0; } +__maybe_unused +static unsigned int spi_get_region(const struct intel_dg_spi *spi, loff_t from) +{ + unsigned int i; + + for (i = 0; i < spi->nregions; i++) { + if ((spi->regions[i].offset + spi->regions[i].size - 1) > from && + spi->regions[i].offset <= from && + spi->regions[i].size != 0) + break; + } + + return i; +} + +static ssize_t spi_rewrite_partial(struct intel_dg_spi *spi, loff_t to, + loff_t offset, size_t len, const u32 *newdata) +{ + u32 data = spi_read32(spi, to); + + if (spi_error(spi)) + return -EIO; + + memcpy((u8 *)&data + offset, newdata, len); + + spi_write32(spi, to, data); + if (spi_error(spi)) + return -EIO; + + return len; +} + +__maybe_unused +static ssize_t spi_write(struct intel_dg_spi *spi, u8 region, + loff_t to, size_t len, const unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + size_t to4; + size_t to_shift; + size_t len_s = len; + ssize_t ret; + + spi_set_region_id(spi, region); + + to4 = ALIGN_DOWN(to, sizeof(u32)); + to_shift = min(sizeof(u32) - ((size_t)to - to4), len); + if (to - to4) { + ret = spi_rewrite_partial(spi, to4, to - to4, to_shift, + (uint32_t *)&buf[0]); + if (ret < 0) + return ret; + + buf += to_shift; + to += to_shift; + len_s -= to_shift; + } + + len8 = ALIGN_DOWN(len_s, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data; + + memcpy(&data, &buf[i], sizeof(u64)); + spi_write64(spi, to + i, data); + if (spi_error(spi)) + return -EIO; + } + + len4 = len_s - len8; + if (len4 >= sizeof(u32)) { + u32 data; + + memcpy(&data, &buf[i], sizeof(u32)); + spi_write32(spi, to + i, data); + if (spi_error(spi)) + return -EIO; + i += sizeof(u32); + len4 -= sizeof(u32); + } + + if (len4 > 0) { + ret = spi_rewrite_partial(spi, to + i, 0, len4, + (uint32_t *)&buf[i]); + if (ret < 0) + return ret; + } + + return len; +} + +__maybe_unused +static ssize_t spi_read(struct intel_dg_spi *spi, u8 region, + loff_t from, size_t len, unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + size_t from4; + size_t from_shift; + size_t len_s = len; + + spi_set_region_id(spi, region); + + from4 = ALIGN_DOWN(from, sizeof(u32)); + from_shift = min(sizeof(u32) - ((size_t)from - from4), len); + + if (from - from4) { + u32 data = spi_read32(spi, from4); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift); + len_s -= from_shift; + buf += from_shift; + from += from_shift; + } + + len8 = ALIGN_DOWN(len_s, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data = spi_read64(spi, from + i); + + if (spi_error(spi)) + return -EIO; + + memcpy(&buf[i], &data, sizeof(data)); + } + + len4 = len_s - len8; + if (len4 >= sizeof(u32)) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, sizeof(data)); + i += sizeof(u32); + len4 -= sizeof(u32); + } + + if (len4 > 0) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, len4); + } + + return len; +} + +__maybe_unused +static ssize_t +spi_erase(struct intel_dg_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr) +{ + u64 i; + const u32 block = 0x10; + void __iomem *base = spi->base; + + for (i = 0; i < len; i += SZ_4K) { + iowrite32(from + i, base + SPI_ADDRESS_REG); + iowrite32(region << 24 | block, base + SPI_ERASE_REG); + /* Since the writes are via sguint + * we cannot do back to back erases. + */ + msleep(50); + } + return len; +} + static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device) { int ret; From patchwork Mon Sep 16 13:49:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 829209 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6641D158A18 for ; Mon, 16 Sep 2024 13:57:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; 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16 Sep 2024 06:57:52 -0700 X-CSE-ConnectionGUID: LQ/B926/QWy8habCH1B3Cw== X-CSE-MsgGUID: +Deif7QtRlqMdvsyKqjCCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="68837357" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:47 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 05/12] spi: intel-dg: implement mtd access handlers Date: Mon, 16 Sep 2024 16:49:21 +0300 Message-Id: <20240916134928.3654054-6-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Tomas Winkler Implement mtd read, erase, and write handlers. For erase operation address and size should be 4K aligned. For write operation address and size has to be 4bytes aligned. CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/spi/spi-intel-dg.c | 152 +++++++++++++++++++++++++++++++++++-- 1 file changed, 147 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c index a936014f1a76..dfb457c43a5d 100644 --- a/drivers/spi/spi-intel-dg.c +++ b/drivers/spi/spi-intel-dg.c @@ -174,7 +174,6 @@ static int intel_dg_spi_is_valid(struct intel_dg_spi *spi) return 0; } -__maybe_unused static unsigned int spi_get_region(const struct intel_dg_spi *spi, loff_t from) { unsigned int i; @@ -206,7 +205,6 @@ static ssize_t spi_rewrite_partial(struct intel_dg_spi *spi, loff_t to, return len; } -__maybe_unused static ssize_t spi_write(struct intel_dg_spi *spi, u8 region, loff_t to, size_t len, const unsigned char *buf) { @@ -265,7 +263,6 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region, return len; } -__maybe_unused static ssize_t spi_read(struct intel_dg_spi *spi, u8 region, loff_t from, size_t len, unsigned char *buf) { @@ -324,7 +321,6 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region, return len; } -__maybe_unused static ssize_t spi_erase(struct intel_dg_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr) { @@ -413,18 +409,164 @@ static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device) static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info) { - return 0; + struct intel_dg_spi *spi; + unsigned int idx; + u8 region; + u64 addr; + ssize_t bytes; + loff_t from; + size_t len; + size_t total_len; + int ret = 0; + + if (!mtd || !info) + return -EINVAL; + + spi = mtd->priv; + if (WARN_ON(!spi)) + return -EINVAL; + + if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) { + dev_err(&mtd->dev, "unaligned erase %llx %llx\n", + info->addr, info->len); + info->fail_addr = MTD_FAIL_ADDR_UNKNOWN; + return -EINVAL; + } + + total_len = info->len; + addr = info->addr; + + mutex_lock(&spi->lock); + + while (total_len > 0) { + if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) { + dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len); + info->fail_addr = addr; + ret = -ERANGE; + goto out; + } + + idx = spi_get_region(spi, addr); + if (idx >= spi->nregions) { + dev_err(&mtd->dev, "out of range"); + info->fail_addr = MTD_FAIL_ADDR_UNKNOWN; + ret = -ERANGE; + goto out; + } + + from = addr - spi->regions[idx].offset; + region = spi->regions[idx].id; + len = total_len; + if (len > spi->regions[idx].size - from) + len = spi->regions[idx].size - from; + + dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n", + region, spi->regions[idx].name, from, len); + + bytes = spi_erase(spi, region, from, len, &info->fail_addr); + if (bytes < 0) { + dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes); + info->fail_addr += spi->regions[idx].offset; + ret = bytes; + goto out; + } + + addr += len; + total_len -= len; + } + +out: + mutex_unlock(&spi->lock); + return ret; } static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { + struct intel_dg_spi *spi; + ssize_t ret; + unsigned int idx; + u8 region; + + if (!mtd) + return -EINVAL; + + spi = mtd->priv; + if (WARN_ON(!spi)) + return -EINVAL; + + idx = spi_get_region(spi, from); + + dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n", + spi->regions[idx].id, spi->regions[idx].name, from, len); + + if (idx >= spi->nregions) { + dev_err(&mtd->dev, "out of ragnge"); + return -ERANGE; + } + + from -= spi->regions[idx].offset; + region = spi->regions[idx].id; + if (len > spi->regions[idx].size - from) + len = spi->regions[idx].size - from; + + mutex_lock(&spi->lock); + + ret = spi_read(spi, region, from, len, buf); + if (ret < 0) { + dev_dbg(&mtd->dev, "read failed with %zd\n", ret); + mutex_unlock(&spi->lock); + return ret; + } + + *retlen = ret; + + mutex_unlock(&spi->lock); return 0; } static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) { + struct intel_dg_spi *spi; + ssize_t ret; + unsigned int idx; + u8 region; + + if (!mtd) + return -EINVAL; + + spi = mtd->priv; + if (WARN_ON(!spi)) + return -EINVAL; + + idx = spi_get_region(spi, to); + + dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n", + spi->regions[idx].id, spi->regions[idx].name, to, len); + + if (idx >= spi->nregions) { + dev_err(&mtd->dev, "out of range"); + return -ERANGE; + } + + to -= spi->regions[idx].offset; + region = spi->regions[idx].id; + if (len > spi->regions[idx].size - to) + len = spi->regions[idx].size - to; + + mutex_lock(&spi->lock); + + ret = spi_write(spi, region, to, len, buf); + if (ret < 0) { + dev_dbg(&mtd->dev, "write failed with %zd\n", ret); + mutex_unlock(&spi->lock); + return ret; + } + + *retlen = ret; + + mutex_unlock(&spi->lock); return 0; } From patchwork Mon Sep 16 13:49:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 829208 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CC21158DC0 for ; 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a="36666865" X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="36666865" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:58:02 -0700 X-CSE-ConnectionGUID: q7F9RPWMQp+GnsXAS4DLZQ== X-CSE-MsgGUID: WE17oruOQryIwiRDcEDN2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="68837396" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:57:57 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 07/12] spi: intel-dg: wake card on operations Date: Mon, 16 Sep 2024 16:49:23 +0300 Message-Id: <20240916134928.3654054-8-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable runtime PM in spi driver to notify graphics driver that whole card should be kept awake while spi operations are performed through this driver. CC: Lucas De Marchi Signed-off-by: Alexander Usyskin --- drivers/spi/spi-intel-dg.c | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c index c76b0a70f8d8..a14fc3190520 100644 --- a/drivers/spi/spi-intel-dg.c +++ b/drivers/spi/spi-intel-dg.c @@ -12,11 +12,14 @@ #include #include #include +#include #include #include #include #include +#define INTEL_DG_SPI_RPM_TIMEOUT 500 + struct intel_dg_spi { struct kref refcnt; struct mtd_info mtd; @@ -471,6 +474,12 @@ static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info) total_len = info->len; addr = info->addr; + ret = pm_runtime_resume_and_get(mtd->dev.parent); + if (ret < 0) { + dev_err(&mtd->dev, "rpm: get failed %d\n", ret); + return ret; + } + mutex_lock(&spi->lock); while (total_len > 0) { @@ -512,6 +521,8 @@ static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info) out: mutex_unlock(&spi->lock); + pm_runtime_mark_last_busy(mtd->dev.parent); + pm_runtime_put_autosuspend(mtd->dev.parent); return ret; } @@ -545,6 +556,12 @@ static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len, if (len > spi->regions[idx].size - from) len = spi->regions[idx].size - from; + ret = pm_runtime_resume_and_get(mtd->dev.parent); + if (ret < 0) { + dev_err(&mtd->dev, "rpm: get failed %zd\n", ret); + return ret; + } + mutex_lock(&spi->lock); ret = spi_read(spi, region, from, len, buf); @@ -557,6 +574,8 @@ static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len, *retlen = ret; mutex_unlock(&spi->lock); + pm_runtime_mark_last_busy(mtd->dev.parent); + pm_runtime_put_autosuspend(mtd->dev.parent); return 0; } @@ -590,6 +609,12 @@ static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len, if (len > spi->regions[idx].size - to) len = spi->regions[idx].size - to; + ret = pm_runtime_resume_and_get(mtd->dev.parent); + if (ret < 0) { + dev_err(&mtd->dev, "rpm: get failed %zd\n", ret); + return ret; + } + mutex_lock(&spi->lock); ret = spi_write(spi, region, to, len, buf); @@ -602,6 +627,8 @@ static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len, *retlen = ret; mutex_unlock(&spi->lock); + pm_runtime_mark_last_busy(mtd->dev.parent); + pm_runtime_put_autosuspend(mtd->dev.parent); return 0; } @@ -747,6 +774,17 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev, } } + pm_runtime_enable(device); + + pm_runtime_set_autosuspend_delay(device, INTEL_DG_SPI_RPM_TIMEOUT); + pm_runtime_use_autosuspend(device); + + ret = pm_runtime_resume_and_get(device); + if (ret < 0) { + dev_err(device, "rpm: get failed %d\n", ret); + goto err_norpm; + } + spi->base = devm_ioremap_resource(device, &ispi->bar); if (IS_ERR(spi->base)) { dev_err(device, "mmio not mapped\n"); @@ -769,9 +807,13 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev, dev_set_drvdata(&aux_dev->dev, spi); + pm_runtime_put(device); return 0; err: + pm_runtime_put(device); +err_norpm: + pm_runtime_disable(device); kref_put(&spi->refcnt, intel_dg_spi_release); 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CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/spi/intel_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c index 4b90e42b0f86..200139531d26 100644 --- a/drivers/gpu/drm/i915/spi/intel_spi.c +++ b/drivers/gpu/drm/i915/spi/intel_spi.c @@ -11,6 +11,13 @@ #define GEN12_GUNIT_SPI_SIZE 0x80 +static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = { + [0] = { .name = "DESCRIPTOR", }, + [2] = { .name = "GSC", }, + [11] = { .name = "OptionROM", }, + [12] = { .name = "DAM", }, +}; + static void i915_spi_release_dev(struct device *dev) { } @@ -31,6 +38,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv) spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1; spi->bar.flags = IORESOURCE_MEM; spi->bar.desc = IORES_DESC_NONE; + spi->regions = regions; aux_dev->name = "spi"; aux_dev->id = (pci_domain_nr(pdev->bus) << 16) | From patchwork Mon Sep 16 13:49:27 2024 Content-Type: text/plain; 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16 Sep 2024 06:58:18 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 11/12] drm/xe/spi: add on-die spi device Date: Mon, 16 Sep 2024 16:49:27 +0300 Message-Id: <20240916134928.3654054-12-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable access to internal spi on DGFX with GSC/CSC devices via a child device. The spi child device is exposed via auxiliary bus. Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 3 + drivers/gpu/drm/xe/xe_device_types.h | 8 +++ drivers/gpu/drm/xe/xe_pci.c | 5 ++ drivers/gpu/drm/xe/xe_spi.c | 82 ++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_spi.h | 15 +++++ 6 files changed, 114 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_spi.c create mode 100644 drivers/gpu/drm/xe/xe_spi.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index edfd812e0f41..90f995b04479 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -93,6 +93,7 @@ xe-y += xe_bb.o \ xe_ring_ops.o \ xe_sa.o \ xe_sched_job.o \ + xe_spi.o \ xe_step.o \ xe_sync.o \ xe_tile.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 4d3c794f134c..25ca0b53c5c1 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -48,6 +48,7 @@ #include "xe_pcode.h" #include "xe_pm.h" #include "xe_query.h" +#include "xe_spi.h" #include "xe_sriov.h" #include "xe_tile.h" #include "xe_ttm_stolen_mgr.h" @@ -734,6 +735,7 @@ int xe_device_probe(struct xe_device *xe) goto err_fini_gt; } + xe_spi_init(xe); xe_heci_gsc_init(xe); err = xe_oa_init(xe); @@ -802,6 +804,7 @@ void xe_device_remove(struct xe_device *xe) xe_oa_fini(xe); xe_heci_gsc_fini(xe); + xe_spi_fini(xe); for_each_gt(gt, xe, id) xe_gt_remove(gt); diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index c92df0a2423f..dfc0183cabe0 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -12,6 +12,8 @@ #include #include +#include + #include "xe_devcoredump_types.h" #include "xe_heci_gsc.h" #include "xe_lmtt_types.h" @@ -44,6 +46,7 @@ struct xe_pat_ops; #define IS_DGFX(xe) ((xe)->info.is_dgfx) #define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi) #define HAS_HECI_CSCFI(xe) ((xe)->info.has_heci_cscfi) +#define HAS_GSC_SPI(xe) ((xe)->info.has_gsc_spi) #define XE_VRAM_FLAGS_NEED64K BIT(0) @@ -331,6 +334,8 @@ struct xe_device { u8 has_heci_gscfi:1; /** @info.has_heci_cscfi: device has heci cscfi */ u8 has_heci_cscfi:1; + /** @info.has_gsc_spi: device has gsc spi */ + u8 has_gsc_spi:1; /** @info.skip_guc_pc: Skip GuC based PM feature init */ u8 skip_guc_pc:1; /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ @@ -499,6 +504,9 @@ struct xe_device { /** @heci_gsc: graphics security controller */ struct xe_heci_gsc heci_gsc; + /** @spi: discrete graphics spi */ + struct intel_dg_spi_dev spi; + /** @oa: oa observation subsystem */ struct xe_oa oa; diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index a1d08e20cd34..45be73ccf274 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -60,6 +60,7 @@ struct xe_device_desc { u8 has_display:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_gsc_spi:1; u8 has_llc:1; u8 has_mmio_ext:1; u8 has_sriov:1; @@ -282,6 +283,7 @@ static const struct xe_device_desc dg1_desc = { PLATFORM(DG1), .has_display = true, .has_heci_gscfi = 1, + .has_gsc_spi = 1, .require_force_probe = true, }; @@ -293,6 +295,7 @@ static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 }; DGFX_FEATURES, \ PLATFORM(DG2), \ .has_heci_gscfi = 1, \ + .has_gsc_spi = 1, \ .subplatforms = (const struct xe_subplatform_desc[]) { \ { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ @@ -324,6 +327,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = { PLATFORM(PVC), .has_display = false, .has_heci_gscfi = 1, + .has_gsc_spi = 1, .require_force_probe = true, }; @@ -613,6 +617,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.is_dgfx = desc->is_dgfx; xe->info.has_heci_gscfi = desc->has_heci_gscfi; xe->info.has_heci_cscfi = desc->has_heci_cscfi; + xe->info.has_gsc_spi = desc->has_gsc_spi; xe->info.has_llc = desc->has_llc; xe->info.has_mmio_ext = desc->has_mmio_ext; xe->info.has_sriov = desc->has_sriov; diff --git a/drivers/gpu/drm/xe/xe_spi.c b/drivers/gpu/drm/xe/xe_spi.c new file mode 100644 index 000000000000..37080b82e9ae --- /dev/null +++ b/drivers/gpu/drm/xe/xe_spi.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "xe_device_types.h" +#include "xe_spi.h" +#include "xe_sriov.h" + +#define GEN12_GUNIT_SPI_BASE 0x00102040 +#define GEN12_GUNIT_SPI_SIZE 0x80 +#define HECI_FW_STATUS_2_SPI_ACCESS_MODE BIT(3) + +static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = { + [0] = { .name = "DESCRIPTOR", }, + [2] = { .name = "GSC", }, + [11] = { .name = "OptionROM", }, + [12] = { .name = "DAM", }, +}; + +static void xe_spi_release_dev(struct device *dev) +{ +} + +void xe_spi_init(struct xe_device *xe) +{ + struct intel_dg_spi_dev *spi = &xe->spi; + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); + struct auxiliary_device *aux_dev = &spi->aux_dev; + int ret; + + if (!HAS_GSC_SPI(xe)) + return; + + /* No access to internal SPI from VFs */ + if (IS_SRIOV_VF(xe)) + return; + + spi->writeable_override = false; + spi->bar.parent = &pdev->resource[0]; + spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start; + spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1; + spi->bar.flags = IORESOURCE_MEM; + spi->bar.desc = IORES_DESC_NONE; + spi->regions = regions; + + aux_dev->name = "spi"; + aux_dev->id = (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent = &pdev->dev; + aux_dev->dev.release = xe_spi_release_dev; + + ret = auxiliary_device_init(aux_dev); + if (ret) { + dev_err(&pdev->dev, "xe-spi aux init failed %d\n", ret); + return; + } + + ret = auxiliary_device_add(aux_dev); + if (ret) { + dev_err(&pdev->dev, "xe-spi aux add failed %d\n", ret); + auxiliary_device_uninit(aux_dev); + return; + } +} + +void xe_spi_fini(struct xe_device *xe) +{ + struct intel_dg_spi_dev *spi = &xe->spi; + + if (!HAS_GSC_SPI(xe)) + return; + + /* No access to internal SPI from VFs */ + if (IS_SRIOV_VF(xe)) + return; + + auxiliary_device_delete(&spi->aux_dev); + auxiliary_device_uninit(&spi->aux_dev); +} diff --git a/drivers/gpu/drm/xe/xe_spi.h b/drivers/gpu/drm/xe/xe_spi.h new file mode 100644 index 000000000000..aef79893a864 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_spi.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2024 Intel Corporation. All rights reserved. + */ + +#ifndef __XE_SPI_H__ +#define __XE_SPI_H__ + +struct xe_device; + +void xe_spi_init(struct xe_device *xe); + +void xe_spi_fini(struct xe_device *xe); + +#endif /* __XE_SPI_H__ */