From patchwork Tue Sep 17 23:29:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 830053 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02F9717920E for ; Tue, 17 Sep 2024 23:29:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726615788; cv=none; b=MI0NFnUeHvMHpcOc+PH17WvrXkL7DjCZl/IPIAgmAfe497oJwA2DcSVmV1QCl/giq+WpCDJw7qEbphskW73ZkASFpW3El9RgvX16V+51WHCW3emvvHYK5B7/CbR5PKjqi1YStKHiZdjPyPzIUtxvieqYp5T0Jq1ueD2yZFkDDtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726615788; c=relaxed/simple; bh=PS96jAihdDtRMarEQelGNHWbItvYn10nrN4v+Fj67fY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UaXZpR0R7SB8KCv17ZEpvGUEvGHG/ivyNW4MmHgdP8GGX59Q67JbpUZLZGHGXxu5JoeLty8sBn82J5I57jzhaL0/78whkXZwsZfHDSz7upO+fw0Zmncs0XHUtCJK5XvGOBMhY6PFZqDFF1HQcUmbDK/K61ZEQegFqCS/D3qhSdg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=mzCm8bZd; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="mzCm8bZd" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id DE7A12C046D; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1726615776; bh=f9JeA8d+mZ1OVpc38H0KjkqDCAD8U+9ZGkj1oHxs4Ts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mzCm8bZd9ZDiB6LlUtGulzxj+j1RqDujVyj9ferde4kdK2VOkdOwadXYnQnCW6yeO aVSXDBX481HfaH1M/Cku61/F1xJeuqUvx9eIeSH0igYS6u8YvSx/ldZko2fVBBJyAt A25A8EGkOoe+FJNYnVSIbEQ30Oy3TOLM/gBgxyfHyoDcrfg+9gGaZUnYM0Z+wP6kl8 uHL8TtKeRfEAxrYYHhExBi5f6gXJxOvyzxNOa+V2mC6n7AlxVsqrR2vIpRDsf1eWXe 4CdIS5BRv2j35rAkkRFNYxPoiRRsjZgqvMpn205EvxFhcj+yOFayQu/wsOu1nymbeW yT3Mj+3N6Y10Q== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 18 Sep 2024 11:29:36 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 7B0AD13EE6D; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 76D27280347; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) From: Chris Packham To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH 1/5] dt-bindings: i2c: Add RTL9300 I2C controller Date: Wed, 18 Sep 2024 11:29:28 +1200 Message-ID: <20240917232932.3641992-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> References: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Id0kWnqa c=1 sm=1 tr=0 ts=66ea10e0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=EaEq8P2WXUwA:10 a=gEfo2CItAAAA:8 a=NEAV23lmAAAA:8 a=VwQbUJbxAAAA:8 a=UgJECxHJAAAA:8 a=lp7SEntL7-OLZ8pvscEA:9 a=3ZKOabzyN94A:10 a=sptkURWiP4Gy88Gu7hUp:22 a=-El7cUbtino8hM1DCn8D:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add dtschema for the I2C controller on the RTL9300 SoC. The I2C controllers on this SoC are part of the "switch" block which is represented here as a syscon node. The SCL pins are dependent on the I2C controller (GPIO8 for the first controller, GPIO 17 for the second). The SDA pins can be assigned to either one of the I2C controllers (but not both). Signed-off-by: Chris Packham --- Notes: This does hit generate the following dt_binding_check warning realtek,rtl9300-i2c.example.dts:22.19-30.13: Warning (unit_address_vs_reg): /example-0/switch@1b000000/i2c@36c: node has a unit name, but no reg or ranges property Which is totally correct. I haven't given this thing a reg property because I'm using an offset from the parent syscon node. I'm also not calling the first offset "offset" but I don't think that'd help. I looked at a couple of other examples of devices that are children of syscon nodes (e.g. armada-ap806-thermal, ap806-cpu-clock) these do have a reg property in the dts but as far as I can see from the code it's not actually used, instead the register offsets are in the code looked up from the driver data (in at least one-case the reg offset is for a legacy usage). So I'm a little unsure what to do here. I can add a reg property and update the driver to use that to get the offset for the first set of registers (or just not use it). Or I could drop the @36c from the node names but then I coudn't distinguish the two controllers without failing the $nodename: requirement from i2c-controller.yaml. .../bindings/i2c/realtek,rtl9300-i2c.yaml | 73 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c.yaml diff --git a/Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c.yaml b/Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c.yaml new file mode 100644 index 000000000000..5b74a1986720 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/realtek,rtl9300-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL I2C Controller + +maintainers: + - Chris Packham + +description: | + The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (which + if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be + assigned to either I2C controller. + +properties: + compatible: + const: realtek,rtl9300-i2c + + realtek,control-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset of the registers for this I2C controller + + realtek,global-control-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset of the I2C global control register (common between + controllers). + + clock-frequency: + enum: [ 100000, 400000 ] + + realtek,sda-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: + SDA pin associated with this I2C controller. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +unevaluatedProperties: false + +required: + - compatible + - realtek,control-offset + - realtek,global-control-offset + +examples: + - | + switch@1b000000 { + compatible = "realtek,rtl9302c-switch", "syscon", "simple-mfd"; + reg = <0x1b000000 0x10000>; + + i2c@36c { + compatible = "realtek,rtl9300-i2c"; + realtek,control-offset = <0x36c>; + realtek,global-control-offset = <0x384>; + clock-frequency = <100000>; + realtek,sda-pin = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@388 { + compatible = "realtek,rtl9300-i2c"; + realtek,control-offset = <0x388>; + realtek,global-control-offset = <0x384>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f328373463b0..ccb1125444f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19887,6 +19887,12 @@ S: Maintained T: git https://github.com/pkshih/rtw.git F: drivers/net/wireless/realtek/rtl8xxxu/ +RTL9300 I2C DRIVER (rtl9300-i2c) +M: Chris Packham +L: linux-i2c@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c.yaml + RTRS TRANSPORT DRIVERS M: Md. Haris Iqbal M: Jack Wang From patchwork Tue Sep 17 23:29:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 830052 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0520C18BC15 for ; Tue, 17 Sep 2024 23:29:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726615789; cv=none; b=cW1oX+57IKm1r4ZWeBf+6uc3OWjiviUxP0iAPhWh6LwBwljZsrPwEnoudxGnzgIhCnsbjhckzh921PRKw98BkYiVWxCzLxTo9ne9FpHaEfr+lq58StZreteCC6rDB2xm3BQdtmHHbGkpcGNk1ZWy5JmHB9aQhkFsAVVroz3skwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726615789; c=relaxed/simple; bh=PWXsu7hmdKyFryLbKF2H2hHNrjY4SabXvnkj3ZlXos0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VPf6ez8O/jueDCA05jlUL9Zg20PRFHjdpUjtX8ZZMX15XtTtZzveuKX7vM1+C2c+0F2toBnQwRK1IO89krqWVIs6Fq1pj29Y7bPoaeGtMVN2aBdBWkni1JegtX91Y56kiWhmtjHpoR8MRPmnheHSh6qZkzbBUp2Td/toyu2K6nY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=i2iHtJ/R; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="i2iHtJ/R" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 37F312C04C6; Wed, 18 Sep 2024 11:29:37 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1726615777; bh=sK0OBjCO0TUSOtd9gJAG5cm4pxzayS0oqY9Ctba8wX0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i2iHtJ/RUCePhTNHQrdP9ONcod08dRjbzksNzYh14ydqZyrmfbcu5i/4wazQgkgGT ynHs4rNvsZBpbvWIcIZprwoG9Rqp+jNy9qAXVWJYAsq5I727IH0ZuNfqTM1g0UWeqq jp6AdpU55ZLSiG9ptarqai0iaC9Yl91qbmkoqVIljHkUtAC6V7NhbAzKwLQDiuxf4N 71dZr/VzsVUlSLA5nb5yoyMZCe4ukr0s3U1quESecfx5QMMfxiG0JTpIgWB4BfrD/Y 3Xj/8U2YBKJ0dC4be02cuNrf7/uVl2WGfJ6aPuWCzLBNjFIXOUwIVoYI2Mrw9noee5 Jb+jabBHav+rg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 18 Sep 2024 11:29:36 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 7EA7913EE84; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 7BA6C280347; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) From: Chris Packham To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH 2/5] i2c: Add driver for the RTL9300 I2C controller Date: Wed, 18 Sep 2024 11:29:29 +1200 Message-ID: <20240917232932.3641992-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> References: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Id0kWnqa c=1 sm=1 tr=0 ts=66ea10e0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=EaEq8P2WXUwA:10 a=jdP34snFAAAA:8 a=VwQbUJbxAAAA:8 a=UgJECxHJAAAA:8 a=wkefLfiLUHRAPrDp2TIA:9 a=3ZKOabzyN94A:10 a=jlphF6vWLdwq7oh3TaWq:22 a=-El7cUbtino8hM1DCn8D:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add support for the I2C controller on the RTL9300 SoC. This is based on the openwrt implementation[1] but cleaned up to make use of the regmap APIs. [1] - https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/realtek/files-5.15/drivers/i2c/busses/i2c-rtl9300.c Signed-off-by: Chris Packham --- MAINTAINERS | 1 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-rtl9300.c | 377 +++++++++++++++++++++++++++++++ 4 files changed, 389 insertions(+) create mode 100644 drivers/i2c/busses/i2c-rtl9300.c diff --git a/MAINTAINERS b/MAINTAINERS index ccb1125444f4..9e123e9839a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19892,6 +19892,7 @@ M: Chris Packham L: linux-i2c@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c.yaml +F: drivers/i2c/busses/i2c-rtl9300.c RTRS TRANSPORT DRIVERS M: Md. Haris Iqbal diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index a22f9125322a..927b583002c7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1041,6 +1041,16 @@ config I2C_RK3X This driver can also be built as a module. If so, the module will be called i2c-rk3x. +config I2C_RTL9300 + tristate "Realtek RTL9300 I2C controller" + depends on MACH_REALTEK_RTL || COMPILE_TEST + help + Say Y here to include support for the I2C controller in Realtek + RTL9300 SoCs. + + This driver can also be built as a module. If so, the module will + be called i2c-rtl9300. + config I2C_RZV2M tristate "Renesas RZ/V2M adapter" depends on ARCH_RENESAS || COMPILE_TEST diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 78d0561339e5..ac2f9f22803c 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o obj-$(CONFIG_I2C_QUP) += i2c-qup.o obj-$(CONFIG_I2C_RIIC) += i2c-riic.o obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o +obj-$(CONFIG_I2C_RTL9300) += i2c-rtl9300.o obj-$(CONFIG_I2C_RZV2M) += i2c-rzv2m.o obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9300.c new file mode 100644 index 000000000000..f16e9b6343bf --- /dev/null +++ b/drivers/i2c/busses/i2c-rtl9300.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include + +struct rtl9300_i2c { + struct regmap *regmap; + struct device *dev; + struct i2c_adapter adap; + u32 i2c_mst_ofs; + u32 i2c_mst_glb_ofs; + u8 bus_freq; + u8 sda_pin; +}; + +#define I2C_MST_CTRL1 0x0 +#define MEM_ADDR_OFS 8 +#define MEM_ADDR_MASK 0xffffff +#define SDA_OUT_SEL_OFS 4 +#define SDA_OUT_SEL_MASK 0x7 +#define GPIO_SCL_SEL BIT(3) +#define RWOP BIT(2) +#define I2C_FAIL BIT(1) +#define I2C_TRIG BIT(0) +#define I2C_MST_CTRL2 0x4 +#define RD_MODE BIT(15) +#define DEV_ADDR_OFS 8 +#define DEV_ADDR_MASK 0x7f +#define DATA_WIDTH_OFS 4 +#define DATA_WIDTH_MASK 0xf +#define MEM_ADDR_WIDTH_OFS 2 +#define MEM_ADDR_WIDTH_MASK 0x3 +#define SCL_FREQ_OFS 0 +#define SCL_FREQ_MASK 0x3 +#define I2C_MST_DATA_WORD0 0x8 +#define I2C_MST_DATA_WORD1 0xc +#define I2C_MST_DATA_WORD2 0x10 +#define I2C_MST_DATA_WORD3 0x14 + +#define RTL9300_I2C_STD_FREQ 0 +#define RTL9300_I2C_FAST_FREQ 1 + +DEFINE_MUTEX(i2c_lock); + +static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) +{ + u32 val, mask; + int ret; + + val = len << MEM_ADDR_WIDTH_OFS; + mask = MEM_ADDR_WIDTH_MASK << MEM_ADDR_WIDTH_OFS; + + ret = regmap_update_bits(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_CTRL2, mask, val); + if (ret) + return ret; + + val = reg << MEM_ADDR_OFS; + mask = MEM_ADDR_MASK << MEM_ADDR_OFS; + + ret = regmap_update_bits(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_CTRL1, mask, val); + if (ret) + return ret; + + return 0; +} + +static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin) +{ + int ret; + + ret = regmap_update_bits(i2c->regmap, i2c->i2c_mst_glb_ofs, BIT(sda_pin), BIT(sda_pin)); + if (ret) + return ret; + + ret = regmap_update_bits(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_CTRL1, + (SDA_OUT_SEL_MASK << SDA_OUT_SEL_OFS) | GPIO_SCL_SEL, + (sda_pin << SDA_OUT_SEL_OFS) | GPIO_SCL_SEL); + if (ret) + return ret; + + return 0; +} + +static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len) +{ + u32 val, mask; + + val = i2c->bus_freq << SCL_FREQ_OFS; + mask = SCL_FREQ_MASK << SCL_FREQ_OFS; + + val |= addr << DEV_ADDR_OFS; + mask |= DEV_ADDR_MASK << DEV_ADDR_OFS; + + val |= ((len - 1) & 0xf) << DATA_WIDTH_OFS; + mask |= DATA_WIDTH_MASK << DATA_WIDTH_OFS; + + mask |= RD_MODE; + + return regmap_update_bits(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_CTRL2, mask, val); +} + +static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) +{ + u32 vals[4] = {}; + int i, ret; + + if (len > 16) + return -EIO; + + ret = regmap_bulk_read(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_DATA_WORD0, + vals, ARRAY_SIZE(vals)); + if (ret) + return ret; + + for (i = 0; i < len; i++) { + buf[i] = vals[i/4] & 0xff; + vals[i/4] >>= 8; + } + + return len; +} + +static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len) +{ + u32 vals[4] = {}; + int i, ret; + + if (len > 16) + return -EIO; + + for (i = 0; i < len; i++) { + if (i % 4 == 0) + vals[i/4] = 0; + vals[i/4] <<= 8; + vals[i/4] |= buf[i]; + } + + ret = regmap_bulk_write(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_DATA_WORD0, + vals, ARRAY_SIZE(vals)); + if (ret) + return ret; + + return len; +} + +static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data) +{ + int ret; + + ret = regmap_write(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_DATA_WORD0, data); + if (ret) + return ret; + + return 0; +} + +static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write, + int size, union i2c_smbus_data *data, int len) +{ + u32 val, mask; + int ret; + + if (read_write == I2C_SMBUS_READ) + val = 0; + else + val = RWOP; + mask = RWOP; + + val |= I2C_TRIG; + mask |= I2C_TRIG; + + ret = regmap_update_bits(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_CTRL1, mask, val); + if (ret) + return ret; + + ret = regmap_read_poll_timeout(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_CTRL1, + val, !(val & I2C_TRIG), 100, 2000); + if (ret) + return ret; + + if (val & I2C_FAIL) + return -EIO; + + if (read_write == I2C_SMBUS_READ) { + if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA) { + ret = regmap_read(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_DATA_WORD0, &val); + if (ret) + return ret; + data->byte = val & 0xff; + } else if (size == I2C_SMBUS_WORD_DATA) { + ret = regmap_read(i2c->regmap, i2c->i2c_mst_ofs + I2C_MST_DATA_WORD0, &val); + if (ret) + return ret; + data->word = val & 0xffff; + } else { + rtl9300_i2c_read(i2c, &data->block[0], len); + } + } + + return 0; +} + +static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, + unsigned short flags, char read_write, + u8 command, int size, union i2c_smbus_data *data) +{ + struct rtl9300_i2c *i2c = i2c_get_adapdata(adap); + int len = 0, ret; + + mutex_lock(&i2c_lock); + switch (size) { + case I2C_SMBUS_QUICK: + rtl9300_i2c_config_xfer(i2c, addr, 0); + rtl9300_i2c_reg_addr_set(i2c, 0, 0); + break; + + case I2C_SMBUS_BYTE: + if (read_write == I2C_SMBUS_WRITE) { + rtl9300_i2c_config_xfer(i2c, addr, 0); + rtl9300_i2c_reg_addr_set(i2c, command, 1); + } else { + rtl9300_i2c_config_xfer(i2c, addr, 1); + rtl9300_i2c_reg_addr_set(i2c, 0, 0); + } + break; + + case I2C_SMBUS_BYTE_DATA: + rtl9300_i2c_reg_addr_set(i2c, command, 1); + rtl9300_i2c_config_xfer(i2c, addr, 1); + if (read_write == I2C_SMBUS_WRITE) + rtl9300_i2c_writel(i2c, data->byte); + break; + + case I2C_SMBUS_WORD_DATA: + rtl9300_i2c_reg_addr_set(i2c, command, 1); + rtl9300_i2c_config_xfer(i2c, addr, 2); + if (read_write == I2C_SMBUS_WRITE) + rtl9300_i2c_writel(i2c, data->word); + break; + + case I2C_SMBUS_BLOCK_DATA: + rtl9300_i2c_reg_addr_set(i2c, command, 1); + rtl9300_i2c_config_xfer(i2c, addr, data->block[0]); + if (read_write == I2C_SMBUS_WRITE) + rtl9300_i2c_write(i2c, &data->block[1], data->block[0]); + len = data->block[0]; + break; + + default: + dev_warn(&adap->dev, "Unsupported transaction %d\n", size); + ret = -EOPNOTSUPP; + goto out_unlock; + } + + ret = rtl9300_i2c_execute_xfer(i2c, read_write, size, data, len); + +out_unlock: + mutex_unlock(&i2c_lock); + + return ret; +} + +static u32 rtl9300_i2c_func(struct i2c_adapter *a) +{ + return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_BLOCK_DATA; +} + +static const struct i2c_algorithm rtl9300_i2c_algo = { + .smbus_xfer = rtl9300_i2c_smbus_xfer, + .functionality = rtl9300_i2c_func, +}; + +struct i2c_adapter_quirks rtl9300_i2c_quirks = { + .flags = I2C_AQ_NO_CLK_STRETCH, + .max_read_len = 16, + .max_write_len = 16, +}; + +static int rtl9300_i2c_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtl9300_i2c *i2c; + struct i2c_adapter *adap; + u32 clock_freq, sda_pin; + int ret; + + i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + i2c->regmap = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(i2c->regmap)) + return PTR_ERR(i2c->regmap); + i2c->dev = dev; + + ret = device_property_read_u32(dev, "realtek,control-offset", &i2c->i2c_mst_ofs); + if (ret) + return ret; + + ret = device_property_read_u32(dev, "realtek,global-control-offset", &i2c->i2c_mst_glb_ofs); + if (ret) + return ret; + + ret = device_property_read_u32(dev, "clock-frequency", &clock_freq); + if (ret) + clock_freq = I2C_MAX_STANDARD_MODE_FREQ; + + switch (clock_freq) { + case I2C_MAX_STANDARD_MODE_FREQ: + i2c->bus_freq = RTL9300_I2C_STD_FREQ; + break; + + case I2C_MAX_FAST_MODE_FREQ: + i2c->bus_freq = RTL9300_I2C_FAST_FREQ; + break; + default: + dev_warn(i2c->dev, "clock-frequency %d not supported\n", clock_freq); + return -EINVAL; + } + + ret = device_property_read_u32(dev, "realtek,sda-pin", &sda_pin); + if (ret) + sda_pin = 0; + i2c->sda_pin = sda_pin; + + adap = &i2c->adap; + adap->owner = THIS_MODULE; + adap->algo = &rtl9300_i2c_algo; + adap->quirks = &rtl9300_i2c_quirks; + adap->retries = 3; + adap->dev.parent = dev; + i2c_set_adapdata(adap, i2c); + adap->dev.of_node = dev->of_node; + strscpy(adap->name, dev_name(dev), sizeof(adap->name)); + + platform_set_drvdata(pdev, i2c); + + ret = rtl9300_i2c_config_io(i2c, i2c->sda_pin); + if (ret) + return ret; + + return i2c_add_adapter(adap); +} + +static void rtl9300_i2c_remove(struct platform_device *pdev) +{ + struct rtl9300_i2c *i2c = platform_get_drvdata(pdev); + + i2c_del_adapter(&i2c->adap); +} + +static const struct of_device_id i2c_rtl9300_dt_ids[] = { + { .compatible = "realtek,rtl9300-i2c" }, + {} +}; +MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); + +static struct platform_driver rtl9300_i2c_driver = { + .probe = rtl9300_i2c_probe, + .remove = rtl9300_i2c_remove, + .driver = { + .name = "i2c-rtl9300", + .of_match_table = i2c_rtl9300_dt_ids, + }, +}; + +module_platform_driver(rtl9300_i2c_driver); + +MODULE_DESCRIPTION("RTL9300 I2C controller driver"); +MODULE_LICENSE("GPL"); + From patchwork Tue Sep 17 23:29:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 829295 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02ED3174EFA for ; Tue, 17 Sep 2024 23:29:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 18 Sep 2024 11:29:36 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 82FB313EE85; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 7FD37280347; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) From: Chris Packham To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH 3/5] mips: dts: realtek: Add I2C controllers Date: Wed, 18 Sep 2024 11:29:30 +1200 Message-ID: <20240917232932.3641992-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> References: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Id0kWnqa c=1 sm=1 tr=0 ts=66ea10e0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=EaEq8P2WXUwA:10 a=fhtXptwnTS7QFdIPH-sA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add the I2C controllers that are part of the RTL9300 SoC. Signed-off-by: Chris Packham --- arch/mips/boot/dts/realtek/rtl930x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index cf1b38b6c353..c579665df700 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -39,6 +39,24 @@ reboot { offset = <0x0c>; value = <0x01>; }; + + i2c0: i2c@36c { + compatible = "realtek,rtl9300-i2c"; + realtek,control-offset = <0x36c>; + realtek,global-control-offset = <0x384>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@388 { + compatible = "realtek,rtl9300-i2c"; + realtek,control-offset = <0x388>; + realtek,global-control-offset = <0x384>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; From patchwork Tue Sep 17 23:29:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 829296 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10D3B1925A3 for ; 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Wed, 18 Sep 2024 11:29:36 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 86F4513ED56; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 840AF280347; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) From: Chris Packham To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH 4/5] dt-bindings: i2c: Add RTL9300 I2C multiplexer Date: Wed, 18 Sep 2024 11:29:31 +1200 Message-ID: <20240917232932.3641992-5-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> References: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Id0kWnqa c=1 sm=1 tr=0 ts=66ea10e0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=EaEq8P2WXUwA:10 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=8lrFv0nGYZjcjRuYp20A:9 a=3ZKOabzyN94A:10 a=sptkURWiP4Gy88Gu7hUp:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat An extension of the RTL9300 SoC is to support multiplexing by selecting the SDA pins that are being used dynamically. Add a binding that allows us to describe hardware that makes use of this. Signed-off-by: Chris Packham --- .../bindings/i2c/realtek,rtl9300-i2c-mux.yaml | 82 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c-mux.yaml diff --git a/Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c-mux.yaml b/Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c-mux.yaml new file mode 100644 index 000000000000..a64879d0fda7 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c-mux.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/realtek,rtl9300-i2c-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL I2C Multiplexer + +maintainers: + - Chris Packham + +description: | + The I2C controllers on the RTL9300 support a level of multiplexing. In the + simple case the rtl9300-i2c binding can provide a single SDA pin per + controller. This binding allows a more than one SDA line to be used per + controller providing a level of multiplexing. + +properties: + compatible: + const: realtek,rtl9300-i2c-mux + + i2c-parent: + description: phandle of the I2C bus controller that this multiplexer + operates on. + $ref: /schemas/types.yaml#/definitions/phandle + +allOf: + - $ref: i2c-mux.yaml + +unevaluatedProperties: false + +required: + - compatible + - i2c-parent + +examples: + - | + switch@1b000000 { + compatible = "realtek,rtl9302c-switch", "syscon", "simple-mfd"; + reg = <0x1b000000 0x10000>; + + i2c0: i2c@36c { + compatible = "realtek,rtl9300-i2c"; + realtek,control-offset = <0x36c>; + realtek,global-control-offset = <0x384>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + base { + i2c-mux { + compatible = "realtek,rtl9300-i2c-mux"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 9e123e9839a5..178ac8a7e843 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19891,6 +19891,7 @@ RTL9300 I2C DRIVER (rtl9300-i2c) M: Chris Packham L: linux-i2c@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c-mux.yaml F: Documentation/devicetree/bindings/i2c/realtek,rtl9300-i2c.yaml F: drivers/i2c/busses/i2c-rtl9300.c From patchwork Tue Sep 17 23:29:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 829294 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00DC8191F95 for ; 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Wed, 18 Sep 2024 11:29:36 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 8B18613EE87; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 88203280347; Wed, 18 Sep 2024 11:29:36 +1200 (NZST) From: Chris Packham To: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH 5/5] i2c: rtl9300: Add multiplexing support Date: Wed, 18 Sep 2024 11:29:32 +1200 Message-ID: <20240917232932.3641992-6-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> References: <20240917232932.3641992-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Id0kWnqa c=1 sm=1 tr=0 ts=66ea10e0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=EaEq8P2WXUwA:10 a=v7xNKfeFtFACfAgD-bQA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat The RTL9300 I2C controller can support multiplexing by choosing the SDA pin to be used dynamically. Add mutliplexing support to the rtl9300 driver. Signed-off-by: Chris Packham --- drivers/i2c/busses/i2c-rtl9300.c | 168 ++++++++++++++++++++++++++++++- 1 file changed, 167 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9300.c index f16e9b6343bf..a934a2526c92 100644 --- a/drivers/i2c/busses/i2c-rtl9300.c +++ b/drivers/i2c/busses/i2c-rtl9300.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only #include +#include #include #include #include @@ -44,6 +45,14 @@ struct rtl9300_i2c { #define RTL9300_I2C_STD_FREQ 0 #define RTL9300_I2C_FAST_FREQ 1 +struct rtl9300_i2c_chan { + int parent; + const unsigned int *chans; + int n_chan; +}; + +#define RTL9300_I2C_MUX_NCHAN 8 + DEFINE_MUTEX(i2c_lock); static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) @@ -370,7 +379,164 @@ static struct platform_driver rtl9300_i2c_driver = { }, }; -module_platform_driver(rtl9300_i2c_driver); +static int rtl9300_i2c_select_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct i2c_adapter *adap = muxc->parent; + struct rtl9300_i2c *i2c = i2c_get_adapdata(adap); + int ret; + + ret = rtl9300_i2c_config_io(i2c, chan); + if (ret) + return ret; + + return 0; +} + +static int rtl9300_i2c_deselect_mux(struct i2c_mux_core *muxc, u32 chan) +{ + struct i2c_adapter *adap = muxc->parent; + struct rtl9300_i2c *i2c = i2c_get_adapdata(adap); + int ret; + + ret = rtl9300_i2c_config_io(i2c, i2c->sda_pin); + if (ret) + return ret; + + return 0; +} + +static int rtl9300_i2c_mux_probe_fw(struct rtl9300_i2c_chan *mux, struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct fwnode_handle *fwnode = dev_fwnode(dev); + struct device_node *np = dev->of_node; + struct device_node *adap_np; + struct i2c_adapter *adap = NULL; + struct fwnode_handle *child; + unsigned int *chans; + int i = 0; + + if (!is_of_node(fwnode)) + return -EOPNOTSUPP; + + if (!np) + return -ENODEV; + + adap_np = of_parse_phandle(np, "i2c-parent", 0); + if (!adap_np) { + dev_err(&pdev->dev, "Cannot parse i2c-parent\n"); + return -ENODEV; + } + adap = of_find_i2c_adapter_by_node(adap_np); + of_node_put(adap_np); + + if (!adap) + return -EPROBE_DEFER; + + mux->parent = i2c_adapter_id(adap); + put_device(&adap->dev); + + mux->n_chan = device_get_child_node_count(dev); + if (mux->n_chan >= RTL9300_I2C_MUX_NCHAN) + return -EINVAL; + + chans = devm_kcalloc(dev, mux->n_chan, sizeof(*mux->chans), GFP_KERNEL); + if (!chans) + return -ENOMEM; + + device_for_each_child_node(dev, child) { + fwnode_property_read_u32(child, "reg", chans + i); + i++; + } + mux->chans = chans; + + return 0; +} + +static int rtl9300_i2c_mux_probe(struct platform_device *pdev) +{ + struct i2c_mux_core *muxc; + struct i2c_adapter *adap; + struct rtl9300_i2c_chan *mux; + int ret, i; + + mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + ret = rtl9300_i2c_mux_probe_fw(mux, pdev); + if (ret) + return ret; + + adap = i2c_get_adapter(mux->parent); + if (!adap) + return -EPROBE_DEFER; + + muxc = i2c_mux_alloc(adap, &pdev->dev, mux->n_chan, 0, 0, + rtl9300_i2c_select_chan, rtl9300_i2c_deselect_mux); + if (!muxc) { + ret = -ENOMEM; + goto err_alloc; + } + muxc->priv = mux; + + platform_set_drvdata(pdev, muxc); + + for (i = 0; i < mux->n_chan; i++) { + ret = i2c_mux_add_adapter(muxc, 0, mux->chans[i]); + if (ret) + goto err_del_adapters; + } + + return 0; + +err_del_adapters: + i2c_mux_del_adapters(muxc); +err_alloc: + i2c_put_adapter(adap); + + return ret; +} + +static void rtl9300_i2c_mux_remove(struct platform_device *pdev) +{ + struct i2c_mux_core *muxc = platform_get_drvdata(pdev); + + i2c_mux_del_adapters(muxc); + i2c_put_adapter(muxc->parent); +} + +static const struct of_device_id i2c_rtl9300_mux_dt_ids[] = { + { .compatible = "realtek,rtl9300-i2c-mux" }, + {} +}; +MODULE_DEVICE_TABLE(of, i2c_rtl9300_mux_dt_ids); + +static struct platform_driver rtl9300_i2c_mux_driver = { + .probe = rtl9300_i2c_mux_probe, + .remove = rtl9300_i2c_mux_remove, + .driver = { + .name = "i2c-mux-rtl9300", + .of_match_table = i2c_rtl9300_mux_dt_ids, + }, +}; + +static struct platform_driver * const drivers[] = { + &rtl9300_i2c_driver, + &rtl9300_i2c_mux_driver, +}; + +static int __init rtl9300_i2c_init(void) +{ + return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); +} +module_init(rtl9300_i2c_init); + +static void __exit rtl9300_i2c_exit(void) +{ + platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); +} +module_exit(rtl9300_i2c_exit); MODULE_DESCRIPTION("RTL9300 I2C controller driver"); MODULE_LICENSE("GPL");