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Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju --- drivers/spi/spi-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 2245ad54b03a..c52066360dfe 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -7,12 +7,12 @@ // Author: Sanjay R Mehta #include +#include #include +#include #include #include -#include #include -#include #include #define AMD_SPI_CTRL0_REG 0x00 From patchwork Wed Sep 18 10:50:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raju Rangoju X-Patchwork-Id: 829533 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2076.outbound.protection.outlook.com [40.107.94.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B2CF381D5; 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Wed, 18 Sep 2024 05:53:47 -0500 From: Raju Rangoju To: , CC: , , , , Subject: [PATCH 3/9] spi: spi_amd: Replace ioread/iowrite calls Date: Wed, 18 Sep 2024 16:20:31 +0530 Message-ID: <20240918105037.406003-4-Raju.Rangoju@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918105037.406003-1-Raju.Rangoju@amd.com> References: <20240918105037.406003-1-Raju.Rangoju@amd.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000206:EE_|MN2PR12MB4405:EE_ X-MS-Office365-Filtering-Correlation-Id: 71e5ce9c-7531-4255-9c2a-08dcd7d0a9b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: DAvbVNru6bvKljLGeJlOTOtNcVYxHqaCH98p1eyG2HGXsrjtjfaikl7G8z6B4KymLjz/BGicVPb31iQIP4myGFg7/HiKtosK5c/AlQJhMy/TMPoEinMjjyRFe7kw+Hss0zEaPPM+PMONxgvFabBGD32/7SIqAFaVcr8Fsnyq3AzYBpTqGkIS5yAErudAZPz41DlbWnNatmj/gHwMMmz7eSBzQ+z9hNwgHxvC2BBmQAXyB0+LcO/BaiR++OigdblJ58oT935Aj7dxkYicsOTm6DLn6Ty0A+x8dKWyu1y+gJ0+HDDEcrRzWeH50KR3ibZo6kA8HVoe1+2qIg2Ko1lsNn3/iNKeXOQqjlKvHyyPi/9ec4UGsEQ+ftGDJWSS7cnqrGJD+YHqcrXUzlOOBt4ENZ5XPFbNeIsGJO/romb4ltldx6dAq93ykcZkLstJB4KFRSjHBJ19LoydcNSWZiWTqfIRhquDE3nOIk8X6wt7bIS5xXt5scpA7fDbAOtA5HZSR+Q7ZB/QQcfUX2bKWGlzvyQHvAErn4taIRnXlQnGuzHA5ozpkU6ghzO8+UqtB+qin/pDuC0Hjcs0WfsFbNaSbUYgkcS4iR1qbZS8cUYhEcg4eLWarhrK++8E9Ny7Faf/EfIPsgBPYywKTHD+M3HnkcAO8wbExZmSoq3/Nl5h2mON07j9foRzOYhNnlXPC1WcDzgGQ1srZFvIWJ4FQSGer9rIm1MVooz4h+p20W5Ztt9gvklVfjFv4SQlPUPKI6ystxuhUXJv92Yt/whhKJXPx+rltJh/UqvlzEGyO91g8RbPY4lWusSgyG5iHWAzqs59tzv5byF8Om5KyGpRqienBsuGaWOKERirgxeDUfiOn3YDgnx9woRtZbHgX79Qh0j/TJ7DXt10dmd2/aPuufC4zrnVtGX+27StU0ctHR4LVz+ELTe1jpG65gUUy22NlwLljZGk0NiWeU9zFFMmAGwUJE8beAfFY44+fvw+YnAJeE0ugjsATjrD58aCfo3Gxg7ACelsJKUZynG0U2kcqoQ5wq+tx1unw80aNUaJoEL+ld2xbulkRPTbZS3qHBZTcUJ5eEzFnOSc20GU5Hp/TbhlGcems2wX2yf6ItnlzZYC+XR639bU6UaosVDReasrtcSQ8Zfqq2uVZimOD+Bad3wF1y+3+eMJagFWO6rpTTG336AmDmWiQiL+67Xz47eAiDfhJE8R+nnLS7OPzZDO5sMasB6sHIbQCDyKu5wgzsM5q5txOLmlDFucrahjRm0RPbyYkhAriQ/c8MSuuUtCc1/PaMuscCfAh24ASIsGwzp11PV0EO+5kURDC1eK5tkrx7ae80GWM8WbUdSkrw+VeC/fKr9xnfjk3l2xsu9Ju09ycv7CCeCiF5wsLFh/e22HerQ2sTZWWNfPCbixirPJNCVq0mOv9bY2NsVn1jGyn/EoUvgCIMAp+6C3BIPzVUeqozzz X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 10:57:17.8979 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71e5ce9c-7531-4255-9c2a-08dcd7d0a9b8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4405 All `ioread*` and `iowrite*` functions are better suited for architecture independent code to ensure portability across different architectures. Since AMD SoCs support only the x86 architecture, replacing all `ioread*` and `iowrite*` calls with `read*` and `write*` calls can reduce the overhead of ensuring portability and increase the speed of I/O operations. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju --- drivers/spi/spi-amd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 54b5a4d18691..11ae910bb420 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -99,12 +99,12 @@ struct amd_spi { static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx) { - return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx); + return readb((u8 __iomem *)amd_spi->io_remap_addr + idx); } static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val) { - iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); + writeb(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); } static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear) @@ -117,12 +117,12 @@ static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 c static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx) { - return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx); + return readl((u8 __iomem *)amd_spi->io_remap_addr + idx); } static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val) { - iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); + writel(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); } static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear) From patchwork Wed Sep 18 10:50:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raju Rangoju X-Patchwork-Id: 829532 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2050.outbound.protection.outlook.com [40.107.220.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9947E176FA7; Wed, 18 Sep 2024 10:58:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.50 ARC-Seal: i=2; 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Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. And, use the version ID to differentiate the register offsets. Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju --- drivers/spi/spi-amd.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index c265e37cebc4..ccad969f501f 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -55,10 +55,12 @@ * enum amd_spi_versions - SPI controller versions * @AMD_SPI_V1: AMDI0061 hardware version * @AMD_SPI_V2: AMDI0062 hardware version + * @AMD_HID2_SPI: AMDI0063 hardware version */ enum amd_spi_versions { AMD_SPI_V1 = 1, AMD_SPI_V2, + AMD_HID2_SPI, }; enum amd_spi_speed { @@ -167,6 +169,7 @@ static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode) AMD_SPI_OPCODE_MASK); return 0; case AMD_SPI_V2: + case AMD_HID2_SPI: amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode); return 0; default: @@ -194,6 +197,7 @@ static int amd_spi_busy_wait(struct amd_spi *amd_spi) reg = AMD_SPI_CTRL0_REG; break; case AMD_SPI_V2: + case AMD_HID2_SPI: reg = AMD_SPI_STATUS_REG; break; default: @@ -219,6 +223,7 @@ static int amd_spi_execute_opcode(struct amd_spi *amd_spi) AMD_SPI_EXEC_CMD); return 0; case AMD_SPI_V2: + case AMD_HID2_SPI: /* Trigger the command execution */ amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG, AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD); @@ -360,6 +365,7 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, case AMD_SPI_V1: break; case AMD_SPI_V2: + case AMD_HID2_SPI: amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0)); break; default: @@ -541,7 +547,7 @@ static int amd_spi_probe(struct platform_device *pdev) amd_spi->version = (uintptr_t) device_get_match_data(dev); /* Initialize the spi_controller fields */ - host->bus_num = 0; + host->bus_num = (amd_spi->version == AMD_HID2_SPI) ? 2 : 0; host->num_chipselect = 4; host->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD; host->flags = SPI_CONTROLLER_HALF_DUPLEX; @@ -565,6 +571,7 @@ static int amd_spi_probe(struct platform_device *pdev) static const struct acpi_device_id spi_acpi_match[] = { { "AMDI0061", AMD_SPI_V1 }, { "AMDI0062", AMD_SPI_V2 }, + { "AMDI0063", AMD_HID2_SPI }, {}, }; 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And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support functions to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju --- drivers/spi/spi-amd.c | 84 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index ccad969f501f..f146366a67e7 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -38,6 +38,7 @@ #define AMD_SPI_FIFO_SIZE 70 #define AMD_SPI_MEM_SIZE 200 #define AMD_SPI_MAX_DATA 64 +#define AMD_SPI_HID2_DMA_SIZE 4096 #define AMD_SPI_ENA_REG 0x20 #define AMD_SPI_ALT_SPD_SHIFT 20 @@ -51,6 +52,21 @@ #define AMD_SPI_MAX_HZ 100000000 #define AMD_SPI_MIN_HZ 800000 +/* SPI read command opcodes */ +#define AMD_SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ +#define AMD_SPI_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ +#define AMD_SPI_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ +#define AMD_SPI_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ +#define AMD_SPI_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ +#define AMD_SPI_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ + +/* SPI read command opcodes - 4B address */ +#define AMD_SPI_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ +#define AMD_SPI_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ +#define AMD_SPI_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ +#define AMD_SPI_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ +#define AMD_SPI_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ + /** * enum amd_spi_versions - SPI controller versions * @AMD_SPI_V1: AMDI0061 hardware version @@ -377,20 +393,82 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, return message->status; } +static inline bool amd_is_spi_read_cmd_4b(const u16 op) +{ + switch (op) { + case AMD_SPI_OP_READ_FAST_4B: + case AMD_SPI_OP_READ_1_1_2_4B: + case AMD_SPI_OP_READ_1_2_2_4B: + case AMD_SPI_OP_READ_1_1_4_4B: + case AMD_SPI_OP_READ_1_4_4_4B: + return true; + default: + return false; + } +} + +static inline bool amd_is_spi_read_cmd(const u16 op) +{ + switch (op) { + case AMD_SPI_OP_READ: + case AMD_SPI_OP_READ_FAST: + case AMD_SPI_OP_READ_1_1_2: + case AMD_SPI_OP_READ_1_2_2: + case AMD_SPI_OP_READ_1_1_4: + case AMD_SPI_OP_READ_1_4_4: + return true; + default: + return amd_is_spi_read_cmd_4b(op); + } +} + static bool amd_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { + struct amd_spi *amd_spi = spi_controller_get_devdata(mem->spi->controller); + /* bus width is number of IO lines used to transmit */ - if (op->cmd.buswidth > 1 || op->addr.buswidth > 4 || - op->data.buswidth > 4 || op->data.nbytes > AMD_SPI_MAX_DATA) + if (op->cmd.buswidth > 1 || op->addr.buswidth > 4) + return false; + + /* AMD SPI controllers support quad mode only for read operations */ + if (amd_is_spi_read_cmd(op->cmd.opcode)) { + if (op->data.buswidth > 4) + return false; + + /* + * HID2 SPI controller supports DMA read up to 4K bytes and + * doesn't support 4-byte address commands. + */ + if (amd_spi->version == AMD_HID2_SPI) { + if (amd_is_spi_read_cmd_4b(op->cmd.opcode) || + op->data.nbytes > AMD_SPI_HID2_DMA_SIZE) + return false; + } else if (op->data.nbytes > AMD_SPI_MAX_DATA) { + return false; + } + } else if (op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA) { return false; + } return spi_mem_default_supports_op(mem, op); } static int amd_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { - op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_MAX_DATA); + struct amd_spi *amd_spi = spi_controller_get_devdata(mem->spi->controller); + + /* + * HID2 SPI controller DMA read mode supports reading up to 4k + * bytes in single transaction, where as SPI0 and HID2 SPI + * controller index mode supports maximum of 64 bytes in a single + * transaction. + */ + if (amd_spi->version == AMD_HID2_SPI && amd_is_spi_read_cmd(op->cmd.opcode)) + op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_HID2_DMA_SIZE); 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This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju --- drivers/spi/spi-amd.c | 176 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 156 insertions(+), 20 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 50dfdf2ab6ee..d30a21b0b05f 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -50,9 +51,21 @@ #define AMD_SPI_SPD7_SHIFT 8 #define AMD_SPI_SPD7_MASK GENMASK(13, AMD_SPI_SPD7_SHIFT) +#define AMD_SPI_HID2_INPUT_RING_BUF0 0X100 +#define AMD_SPI_HID2_CNTRL 0x150 +#define AMD_SPI_HID2_INT_STATUS 0x154 +#define AMD_SPI_HID2_CMD_START 0x156 +#define AMD_SPI_HID2_INT_MASK 0x158 +#define AMD_SPI_HID2_READ_CNTRL0 0x170 +#define AMD_SPI_HID2_READ_CNTRL1 0x174 +#define AMD_SPI_HID2_READ_CNTRL2 0x180 + #define AMD_SPI_MAX_HZ 100000000 #define AMD_SPI_MIN_HZ 800000 +#define AMD_SPI_IO_SLEEP_US 20 +#define AMD_SPI_IO_TIMEOUT_US 2000000 + /* SPI read command opcodes */ #define AMD_SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ #define AMD_SPI_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ @@ -108,11 +121,15 @@ struct amd_spi_freq { /** * struct amd_spi - SPI driver instance * @io_remap_addr: Start address of the SPI controller registers + * @phy_dma_buf: Physical address of DMA buffer + * @dma_virt_addr: Virtual address of DMA buffer * @version: SPI controller hardware version * @speed_hz: Device frequency */ struct amd_spi { void __iomem *io_remap_addr; + dma_addr_t phy_dma_buf; + void *dma_virt_addr; enum amd_spi_versions version; unsigned int speed_hz; }; @@ -135,6 +152,16 @@ static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 c amd_spi_writereg8(amd_spi, idx, tmp); } +static inline u16 amd_spi_readreg16(struct amd_spi *amd_spi, int idx) +{ + return readw((u8 __iomem *)amd_spi->io_remap_addr + idx); +} + +static inline void amd_spi_writereg16(struct amd_spi *amd_spi, int idx, u16 val) +{ + writew(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); +} + static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx) { return readl((u8 __iomem *)amd_spi->io_remap_addr + idx); @@ -517,6 +544,64 @@ static void amd_spi_mem_data_out(struct amd_spi *amd_spi, amd_spi_execute_opcode(amd_spi); } +static void amd_spi_hiddma_read(struct amd_spi *amd_spi, const struct spi_mem_op *op) +{ + u16 hid_cmd_start, val; + u32 hid_regval; + + /* Set the opcode in hid2_read_control0 register */ + hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL0); + hid_regval = (hid_regval & ~GENMASK(7, 0)) | op->cmd.opcode; + + /* + * Program the address in the hid2_read_control0 register [8:31]. The address should + * be written starting from the 8th bit of the register, requiring an 8-bit shift. + * Additionally, to convert a 2-byte spinand address to a 3-byte address, another + * 8-bit shift is needed. Therefore, a total shift of 16 bits is required. + */ + hid_regval = (hid_regval & ~GENMASK(31, 8)) | (op->addr.val << 16); + amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL0, hid_regval); + + /* Configure dummy clock cycles for fast read, dual, quad I/O commands */ + hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL2); + /* Fast read dummy cycle */ + hid_regval &= ~GENMASK(4, 0); + + /* Fast read Dual I/O dummy cycle */ + hid_regval &= ~GENMASK(12, 8); + + /* Fast read Quad I/O dummy cycle */ + hid_regval = (hid_regval & ~GENMASK(20, 16)) | BIT(17); + + /* Set no of preamble bytecount */ + hid_regval &= ~GENMASK(27, 24); + amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL2, hid_regval); + + /* + * Program the HID2 Input Ring Buffer0. 4k aligned buf_memory_addr[31:12], + * buf_size[4:0], end_input_ring[5]. + */ + hid_regval = amd_spi->phy_dma_buf | BIT(5) | BIT(0); + amd_spi_writereg32(amd_spi, AMD_SPI_HID2_INPUT_RING_BUF0, hid_regval); + + /* Program max read length(no of DWs) in hid2_read_control1 register */ + hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL1); + hid_regval = (hid_regval & ~GENMASK(15, 0)) | ((op->data.nbytes / 4) - 1); + amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL1, hid_regval); + + /* Set cmd start bit in hid2_cmd_start register to trigger HID basic read operation */ + hid_cmd_start = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_CMD_START); + amd_spi_writereg16(amd_spi, AMD_SPI_HID2_CMD_START, (hid_cmd_start | BIT(3))); + + /* Check interrupt status of HIDDMA basic read operation in hid2_int_status register */ + readw_poll_timeout(amd_spi->io_remap_addr + AMD_SPI_HID2_INT_STATUS, val, + (val & BIT(3)), AMD_SPI_IO_SLEEP_US, AMD_SPI_IO_TIMEOUT_US); + + /* Clear the interrupts by writing to hid2_int_status register */ + val = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_INT_STATUS); + amd_spi_writereg16(amd_spi, AMD_SPI_HID2_INT_STATUS, val); +} + static void amd_spi_mem_data_in(struct amd_spi *amd_spi, const struct spi_mem_op *op) { @@ -524,29 +609,52 @@ static void amd_spi_mem_data_in(struct amd_spi *amd_spi, u64 *buf_64 = (u64 *)op->data.buf.in; u32 nbytes = op->data.nbytes; u32 left_data = nbytes; + u32 data; u8 *buf; int i; - amd_spi_set_opcode(amd_spi, op->cmd.opcode); - amd_spi_set_addr(amd_spi, op); - amd_spi_set_tx_count(amd_spi, op->addr.nbytes + op->dummy.nbytes); - - for (i = 0; i < op->dummy.nbytes; i++) - amd_spi_writereg8(amd_spi, (base_addr + i), 0xff); - - amd_spi_set_rx_count(amd_spi, op->data.nbytes); - amd_spi_clear_fifo_ptr(amd_spi); - amd_spi_execute_opcode(amd_spi); - amd_spi_busy_wait(amd_spi); - - for (i = 0; left_data >= 8; i++, left_data -= 8) - *buf_64++ = amd_spi_readreg64(amd_spi, base_addr + op->dummy.nbytes + - (i * 8)); + /* + * Condition for using HID read mode. Only for reading complete page data, use HID read. + * Use index mode otherwise. + */ + if (amd_spi->version == AMD_HID2_SPI && amd_is_spi_read_cmd(op->cmd.opcode)) { + amd_spi_hiddma_read(amd_spi, op); + + for (i = 0; left_data >= 8; i++, left_data -= 8) + *buf_64++ = readq((u8 __iomem *)amd_spi->dma_virt_addr + (i * 8)); + + buf = (u8 *)buf_64; + for (i = 0; i < left_data; i++) + buf[i] = readb((u8 __iomem *)amd_spi->dma_virt_addr + + (nbytes - left_data + i)); + + /* Reset HID RX memory logic */ + data = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_CNTRL); + amd_spi_writereg32(amd_spi, AMD_SPI_HID2_CNTRL, data | BIT(5)); + } else { + /* Index mode */ + amd_spi_set_opcode(amd_spi, op->cmd.opcode); + amd_spi_set_addr(amd_spi, op); + amd_spi_set_tx_count(amd_spi, op->addr.nbytes + op->dummy.nbytes); + + for (i = 0; i < op->dummy.nbytes; i++) + amd_spi_writereg8(amd_spi, (base_addr + i), 0xff); + + amd_spi_set_rx_count(amd_spi, op->data.nbytes); + amd_spi_clear_fifo_ptr(amd_spi); + amd_spi_execute_opcode(amd_spi); + amd_spi_busy_wait(amd_spi); + + for (i = 0; left_data >= 8; i++, left_data -= 8) + *buf_64++ = amd_spi_readreg64(amd_spi, base_addr + op->dummy.nbytes + + (i * 8)); + + buf = (u8 *)buf_64; + for (i = 0; i < left_data; i++) + buf[i] = amd_spi_readreg8(amd_spi, base_addr + op->dummy.nbytes + + nbytes + i - left_data); + } - buf = (u8 *)buf_64; - for (i = 0; i < left_data; i++) - buf[i] = amd_spi_readreg8(amd_spi, base_addr + op->dummy.nbytes + - nbytes + i - left_data); } static void amd_set_spi_addr_mode(struct amd_spi *amd_spi, @@ -617,6 +725,31 @@ static size_t amd_spi_max_transfer_size(struct spi_device *spi) return AMD_SPI_FIFO_SIZE; } +static int amd_spi_setup_hiddma(struct amd_spi *amd_spi, struct device *dev) +{ + u32 hid_regval; + + /* Allocate DMA buffer to use for HID basic read operation */ + amd_spi->dma_virt_addr = dma_alloc_coherent(dev, AMD_SPI_HID2_DMA_SIZE, + &amd_spi->phy_dma_buf, GFP_KERNEL); + if (!amd_spi->dma_virt_addr) + return -ENOMEM; + + /* + * Enable interrupts and set mask bits in hid2_int_mask register to generate interrupt + * properly for HIDDMA basic read operations. + */ + hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_INT_MASK); + hid_regval = (hid_regval & GENMASK(31, 8)) | BIT(19); + amd_spi_writereg32(amd_spi, AMD_SPI_HID2_INT_MASK, hid_regval); + + /* Configure buffer unit(4k) in hid2_control register */ + hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_CNTRL); + amd_spi_writereg32(amd_spi, AMD_SPI_HID2_CNTRL, hid_regval & ~BIT(3)); + + return 0; +} + static int amd_spi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -657,7 +790,10 @@ static int amd_spi_probe(struct platform_device *pdev) if (err) return dev_err_probe(dev, err, "error registering SPI controller\n"); - return 0; + if (amd_spi->version == AMD_HID2_SPI) + err = amd_spi_setup_hiddma(amd_spi, dev); + + return err; } #ifdef CONFIG_ACPI