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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f57debe5csm94870215e9.24.2024.09.30.00.35.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:38 +0200 Message-ID: <20240930073450.33195-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce the ld/st_endian_p() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_p() methods. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- TODO: Update docstring regexp --- include/qemu/bswap.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index ad22910a5d..ec813a756d 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -433,4 +433,23 @@ DO_STN_LDN_P(be) #undef le_bswaps #undef be_bswaps +#define lduw_endian_p(big_endian, p) \ + (big_endian) ? lduw_be_p(p) : lduw_le_p(p) +#define ldsw_endian_p(big_endian, p) \ + (big_endian) ? ldsw_be_p(p) : ldsw_be_p(p) +#define ldl_endian_p(big_endian, p) \ + (big_endian) ? ldl_be_p(p) : ldl_le_p(p) +#define ldq_endian_p(big_endian, p) \ + (big_endian) ? ldq_be_p(p) : ldq_le_p(p) +#define stw_endian_p(big_endian, p, v) \ + (big_endian) ? stw_be_p(p, v) : stw_le_p(p, v) +#define stl_endian_p(big_endian, p, v) \ + (big_endian) ? stl_be_p(p, v) : stl_le_p(p, v) +#define stq_endian_p(big_endian, p, v) \ + (big_endian) ? stq_be_p(p, v) : stq_le_p(p, v) +#define ldn_endian_p(big_endian, p, sz) \ + (big_endian) ? ldn_be_p(p, sz) : ldn_le_p(p, sz) +#define stn_endian_p(big_endian, p, sz, v) \ + (big_endian) ? stn_be_p(p, sz, v) : stn_le_p(p, sz, v) + #endif /* BSWAP_H */ From patchwork Mon Sep 30 07:34:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831525 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1832272wrw; Mon, 30 Sep 2024 01:02:57 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUQNOI8HDpA0mvMRGUJ4JK7TVtRMH/bsvcLnf0QKLiKMDK0bQOIa3Jc+KvirqrJHKs4TEWj0A==@linaro.org X-Google-Smtp-Source: AGHT+IH15bh35MfLc6WyyfTlDagjwGEQJmpTZ3/D79QOhgpjvUV/aweW7Kqra7Qj/cieuLejaGwH X-Received: by 2002:a05:6214:310f:b0:6c5:540c:82b0 with SMTP id 6a1803df08f44-6cb3b5e6e29mr160404416d6.4.1727683377393; Mon, 30 Sep 2024 01:02:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727683377; cv=none; d=google.com; s=arc-20240605; b=P1ScDdSh3nYXk2htJ6HEncUwqcRUqmQmLoFjZ65C8Pd01AmNNuPLznwBjXDJ2rSkFE yIjKgR++NLuJLNLmbJyIc+OFbPXkAUPxON1UM8frE3BkNPfGSMmVTfH72adCTbfdREw2 ZyDaweGX5o6h7qnpl/PtfN8NPFA6ST/Ol8QkLkldXi/zmWcHAckZxRib0S9JDEiYmBeu Ylx+9ZIlqzc0lBVsT7AoSo73TNfrSAzLw/ngq6SCpcG3Nu7iZt1QTk/C1+hwCL16Hgzp NiWXwqAF+dMFy92OLJJli9VHvXVLX3wU3ZgG061EvIIeCV6qgyHuBike2FP5K1MmoCju sriA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yXipE1vCqUL/2GGIC/pfDOg0/7HE+1Efkqb3qV24aq0=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=TBMHNUCI0+bCgFFg1Y5V5rkNwR79IOpviRwo/lziYRa4ZLf+gqv/HhVb8PNEa/ZvPf 10aPtapFg12ShuedRmTgCdnUgPVjTesmMA84rP/2gcPtv9P8ZdGuOfiGddsSrCtxLF9n oWa0Mjv1A4v1NYvdZ4zGyu3HIxKxYcruHdyUoTlXeRL3YDoEx97eeX9gW3v2EWBPj0E+ F8qMUx8D6I9NfWhmccu1NsCw6VsJWDOjGc0efHOHn/R0ESf8aikG3PizDmALclZR4Nf3 aoD6r1Lj+vhLMJhQJnWA9tlduIs0zwTxG9wsHxW00z50idxsZl+e2gMjyyYgnzvmw0yU F35w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tx5YoGJW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 02/13] hw/virtio/virtio-access: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:39 +0200 Message-ID: <20240930073450.33195-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/virtio/virtio-access.h | 36 ++++++------------------------- 1 file changed, 6 insertions(+), 30 deletions(-) diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-access.h index 07aae69042..b920874be8 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -95,56 +95,32 @@ static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa, static inline void virtio_stw_p(VirtIODevice *vdev, void *ptr, uint16_t v) { - if (virtio_access_is_big_endian(vdev)) { - stw_be_p(ptr, v); - } else { - stw_le_p(ptr, v); - } + stw_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } static inline void virtio_stl_p(VirtIODevice *vdev, void *ptr, uint32_t v) { - if (virtio_access_is_big_endian(vdev)) { - stl_be_p(ptr, v); - } else { - stl_le_p(ptr, v); - } + stl_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } static inline void virtio_stq_p(VirtIODevice *vdev, void *ptr, uint64_t v) { - if (virtio_access_is_big_endian(vdev)) { - stq_be_p(ptr, v); - } else { - stq_le_p(ptr, v); - } + stq_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } static inline int virtio_lduw_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return lduw_be_p(ptr); - } else { - return lduw_le_p(ptr); - } + return lduw_endian_p(virtio_access_is_big_endian(vdev), ptr); } static inline int virtio_ldl_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return ldl_be_p(ptr); - } else { - return ldl_le_p(ptr); - } + return ldl_endian_p(virtio_access_is_big_endian(vdev), ptr); } static inline uint64_t virtio_ldq_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return ldq_be_p(ptr); - } else { - return ldq_le_p(ptr); - } + return ldq_endian_p(virtio_access_is_big_endian(vdev), ptr); } static inline uint16_t virtio_tswap16(VirtIODevice *vdev, uint16_t s) From patchwork Mon Sep 30 07:34:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831530 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1833749wrw; Mon, 30 Sep 2024 01:07:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXnhuEELbDPApUyZCAgLYDGPaP56wspcxWtWvMLA9kFtbzV5bH9G3Vg+aGpBL5DK8Ya3ti2Rw==@linaro.org X-Google-Smtp-Source: AGHT+IGvjVMz5i8bTaj9acZ196lO121SYKbve3hqqhcq4bRiz7EKIaef53/qjUy8Zhh+ZiY3qtnq X-Received: by 2002:a05:622a:15cf:b0:458:5161:e0ca with SMTP id d75a77b69052e-45c9f284d7emr183253401cf.41.1727683634747; Mon, 30 Sep 2024 01:07:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727683634; cv=none; d=google.com; s=arc-20240605; b=gLuY7W2cuq3H8Fyw1tA8kDJJN7CtgZCvY+PiAB9pU82quT5hY2AKvTq/oaDuT0UIcU IyScHwC5Yb4RYzyZha1Dk+TOG3N6Es5CaYFicwmoIx8ajiKZuMv6tR3+HedXaRDepNqN mTfdyzj0vhq0UW7x/hjIW0i5Ovex58XMnzjMk/0xFIZXZwBh8tpZ24mhE432qGJN5Bui jR3IRyiF5z/xjabmV4+TYZ+QtiRHo2b7jS2w6qNnu10wajitfmhKkBBnEj0Z7mWJST5G I9NxJSLJvCe+7f9wmtpA7He4t6irjL6G7QSmx3ZTU0WZ4JnekC2PKUsP/MzFyX1Bom3k nPvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PDKmxhtETyeu/iYuY2neXJ4cpuVufAHpcFENKpKvuEg=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=dOupyHk/OVTVBlSulQELHhK9rl5jUA6QDD9BfZNxE6G1dh0izJkhcWWEZJNcInep36 jwsYJ3zZJqbmJskzTz+Xu8IvivEoFBYXvPVatVkLIa50eqf78miBmrx/3ynY2PXM0+iU Mt/rVAQO32ZZpauH0k6sSqm/9ssKiAHIWuY92Oypd+e1YWTnCOBKZpwCEaLXUKyyuvgc 87XLwNF6wFfK4UBV0heTeZLM54PjYZKtADGpwMU/ptHz/vCc+OPI7AydcvW+iOGDggRk lQL1GUUbx4c7d91l8JSaqs90lA2Ox4CNVfZgdhnPf0lZhtPwF/zBqCrl8o//T8nEv7TQ VH8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xVF6KTM+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd5742a23sm8324073f8f.105.2024.09.30.00.35.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 03/13] target/arm/ptw: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:40 +0200 Message-ID: <20240930073450.33195-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/arm/ptw.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index defd6b84de..a1a6b1fec3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -699,11 +699,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, data = le64_to_cpu(data); } #else - if (ptw->out_be) { - data = ldq_be_p(host); - } else { - data = ldq_le_p(host); - } + data = ldq_endian_p(ptw->out_be, host); #endif } else { /* Page tables are in MMIO. */ @@ -860,16 +856,9 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, if (!locked) { bql_lock(); } - if (ptw->out_be) { - cur_val = ldq_be_p(host); - if (cur_val == old_val) { - stq_be_p(host, new_val); - } - } else { - cur_val = ldq_le_p(host); - if (cur_val == old_val) { - stq_le_p(host, new_val); - } + cur_val = ldq_endian_p(ptw->out_be, host); + if (cur_val == old_val) { + stq_endian_p(ptw->out_be, host, new_val); } if (!locked) { bql_unlock(); From patchwork Mon Sep 30 07:34:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831522 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1830892wrw; Mon, 30 Sep 2024 00:59:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV4b+6393ICp2jdxZwhfwRYTOgc+HYGN+GiTISsUVEu/gRvxxaqvfl11BLyJmiiRiRzZYaocA==@linaro.org X-Google-Smtp-Source: AGHT+IGDYOXtjegjKtgmQ8xREm7MPGOBaMyNH1IfSTC8AxZLSms8cuTa8Wk70l1uriwUYZOAxYOG X-Received: by 2002:a0c:f412:0:b0:6cb:54be:d57e with SMTP id 6a1803df08f44-6cb54bed58emr97005326d6.50.1727683175122; Mon, 30 Sep 2024 00:59:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727683175; cv=none; d=google.com; s=arc-20240605; b=Ok/0jqQR91WuIEDfJcKjFW1jOexpJoo25PNIhWogK6CLiOJeKoaVtgYft+Ep91cD8l gngHEhF+XJOI7c8msocgT4W87ALmPSPfQt26eRst2pXqC9C9/tgNowvmzvLl9xI1a8R1 a0G23TtIXJdHdayge3mpsC01VdljjDLHd+B8jpkbm2Y5TzNdvZWaMGJZBR1Pwkuo4LFU Js6EVvvCLnd7rzaxhFAk1AB97l1t7yKIjhCJY0RHz6NDRUYNp3VCt8djM/1OfqscxKp5 QTz0eNjuuSCbP1mLrsAK1LrQ6cOKPvvymnZkCh24xqpVT1vot1GCLsqItklFu12IHupB IepA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xlB7TER95AHLu1cUEZk4SLXmuphORdTbB9q557qt3nU=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=BqSIvrLGN+f97wD32fpK5/fPHsKV87gGqP/1b4omxmEs6NlcJzawI95/aayLFm+2+O NbL+9iZygWVHekf4txuaOmPWvRF97Aa9gMaWvjnmDf4obQZVAclXH0iXJoEeiNUmHMWE rMLj1TXcr2y2DNpc1C4bAK16Ze5hCywsWQnUYuFxmFR1GuQHAl3rm7ujgAWSyiwT0z7D F1xxAK7Km0oPcrK9547QCj5G2MILPVi1BkXDTVM9uB3TI1GkOdiw4pHZJ+MkbAqdORdg GAAOyjsAjt+8xubrfJoccWrvRH98hLMrTlFSisNzTyxJPJY+n+63GoHrK4dfM7nSrwq7 t/1g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PWmyRjTl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd575dfd2sm8301463f8f.117.2024.09.30.00.35.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 04/13] hw/mips: Pass BlCpuCfg argument to bootloader API Date: Mon, 30 Sep 2024 09:34:41 +0200 Message-ID: <20240930073450.33195-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation to pass endianness and target word size to the bootloader API, introduce an empty BlCpuCfg structure and propagate it to the MIPS bootloader methods. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/mips/bootloader.h | 17 +++-- hw/mips/bootloader.c | 142 +++++++++++++++++++---------------- hw/mips/boston.c | 9 ++- hw/mips/fuloong2e.c | 3 +- hw/mips/malta.c | 21 +++--- 5 files changed, 109 insertions(+), 83 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index c32f6c2835..744eb11d0e 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -10,17 +10,24 @@ #define HW_MIPS_BOOTLOADER_H #include "exec/cpu-defs.h" +#include "exec/target_long.h" -void bl_gen_jump_to(void **ptr, target_ulong jump_addr); -void bl_gen_jump_kernel(void **ptr, +typedef struct bl_cpu_cfg { +} BlCpuCfg; + +void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr); +void bl_gen_jump_kernel(const BlCpuCfg *cfg, void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, bool set_a2, target_ulong a2, bool set_a3, target_ulong a3, target_ulong kernel_addr); -void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); -void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); -void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); +void bl_gen_write_ulong(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, target_ulong val); +void bl_gen_write_u32(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, uint32_t val); +void bl_gen_write_u64(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef2096..ee1a1c4f20 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -54,7 +54,7 @@ static bool bootcpu_supports_isa(uint64_t isa_mask) return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); } -static void st_nm32_p(void **ptr, uint32_t insn) +static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, uint32_t insn) { uint16_t *p = *ptr; @@ -67,10 +67,10 @@ static void st_nm32_p(void **ptr, uint32_t insn) } /* Base types */ -static void bl_gen_nop(void **ptr) +static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - st_nm32_p(ptr, 0x8000c000); + st_nm32_p(cfg, ptr, 0x8000c000); } else { uint32_t *p = *ptr; @@ -80,7 +80,8 @@ static void bl_gen_nop(void **ptr) } } -static void bl_gen_r_type(void **ptr, uint8_t opcode, +static void bl_gen_r_type(const BlCpuCfg *cfg, + void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, bl_reg rd, uint8_t shift, uint8_t funct) { @@ -100,7 +101,8 @@ static void bl_gen_r_type(void **ptr, uint8_t opcode, *ptr = p; } -static void bl_gen_i_type(void **ptr, uint8_t opcode, +static void bl_gen_i_type(const BlCpuCfg *cfg, + void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, uint16_t imm) { uint32_t *p = *ptr; @@ -118,16 +120,17 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, } /* Single instructions */ -static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) +static void bl_gen_dsll(const BlCpuCfg *cfg, void **p, + bl_reg rd, bl_reg rt, uint8_t sa) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); + bl_gen_r_type(cfg, p, 0, 0, rt, rd, sa, 0x38); } else { g_assert_not_reached(); /* unsupported */ } } -static void bl_gen_jalr(void **p, bl_reg rs) +static void bl_gen_jalr(const BlCpuCfg *cfg, void **p, bl_reg rs) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { uint32_t insn = 0; @@ -136,13 +139,14 @@ static void bl_gen_jalr(void **p, bl_reg rs) insn = deposit32(insn, 21, 5, BL_REG_RA); insn = deposit32(insn, 16, 5, rs); - st_nm32_p(p, insn); + st_nm32_p(cfg, p, insn); } else { - bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09); + bl_gen_r_type(cfg, p, 0, rs, 0, BL_REG_RA, 0, 0x09); } } -static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20) +static void bl_gen_lui_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, uint32_t imm20) { uint32_t insn = 0; @@ -153,16 +157,18 @@ static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20) insn = deposit32(insn, 2, 10, extract32(imm20, 9, 10)); insn = deposit32(insn, 0, 1, sextract32(imm20, 19, 1)); - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } -static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm) +static void bl_gen_lui(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint16_t imm) { /* R6: It's a alias of AUI with RS = 0 */ - bl_gen_i_type(p, 0x0f, 0, rt, imm); + bl_gen_i_type(cfg, p, 0x0f, 0, rt, imm); } -static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12) +static void bl_gen_ori_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, bl_reg rs, uint16_t imm12) { uint32_t insn = 0; @@ -172,15 +178,17 @@ static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12) insn = deposit32(insn, 16, 5, rs); insn = deposit32(insn, 0, 12, imm12); - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } -static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) +static void bl_gen_ori(const BlCpuCfg *cfg, void **p, + bl_reg rt, bl_reg rs, uint16_t imm) { - bl_gen_i_type(p, 0x0d, rs, rt, imm); + bl_gen_i_type(cfg, p, 0x0d, rs, rt, imm); } -static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) +static void bl_gen_sw_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, uint8_t rs, uint16_t ofs12) { uint32_t insn = 0; @@ -191,66 +199,71 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) insn = deposit32(insn, 12, 4, 0b1001); insn = deposit32(insn, 0, 12, ofs12); - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } -static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sw(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - bl_gen_sw_nm(p, rt, base, offset); + bl_gen_sw_nm(cfg, p, rt, base, offset); } else { - bl_gen_i_type(p, 0x2b, base, rt, offset); + bl_gen_i_type(cfg, p, 0x2b, base, rt, offset); } } -static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sd(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_i_type(p, 0x3f, base, rt, offset); + bl_gen_i_type(cfg, p, 0x3f, base, rt, offset); } else { g_assert_not_reached(); /* unsupported */ } } /* Pseudo instructions */ -static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) +static void bl_gen_li(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint32_t imm) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); - bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); + bl_gen_lui_nm(cfg, p, rt, extract32(imm, 12, 20)); + bl_gen_ori_nm(cfg, p, rt, rt, extract32(imm, 0, 12)); } else { - bl_gen_lui(p, rt, extract32(imm, 16, 16)); - bl_gen_ori(p, rt, rt, extract32(imm, 0, 16)); + bl_gen_lui(cfg, p, rt, extract32(imm, 16, 16)); + bl_gen_ori(cfg, p, rt, rt, extract32(imm, 0, 16)); } } -static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) +static void bl_gen_dli(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint64_t imm) { - bl_gen_li(p, rt, extract64(imm, 32, 32)); - bl_gen_dsll(p, rt, rt, 16); - bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); - bl_gen_dsll(p, rt, rt, 16); - bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); + bl_gen_li(cfg, p, rt, extract64(imm, 32, 32)); + bl_gen_dsll(cfg, p, rt, rt, 16); + bl_gen_ori(cfg, p, rt, rt, extract64(imm, 16, 16)); + bl_gen_dsll(cfg, p, rt, rt, 16); + bl_gen_ori(cfg, p, rt, rt, extract64(imm, 0, 16)); } -static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) +static void bl_gen_load_ulong(const BlCpuCfg *cfg, void **p, + bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_dli(p, rt, imm); /* 64bit */ + bl_gen_dli(cfg, p, rt, imm); /* 64bit */ } else { - bl_gen_li(p, rt, imm); /* 32bit */ + bl_gen_li(cfg, p, rt, imm); /* 32bit */ } } /* Helpers */ -void bl_gen_jump_to(void **p, target_ulong jump_addr) +void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr) { - bl_gen_load_ulong(p, BL_REG_T9, jump_addr); - bl_gen_jalr(p, BL_REG_T9); - bl_gen_nop(p); /* delay slot */ + bl_gen_load_ulong(cfg, p, BL_REG_T9, jump_addr); + bl_gen_jalr(cfg, p, BL_REG_T9); + bl_gen_nop(cfg, p); /* delay slot */ } -void bl_gen_jump_kernel(void **p, +void bl_gen_jump_kernel(const BlCpuCfg *cfg, void **p, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, @@ -259,45 +272,48 @@ void bl_gen_jump_kernel(void **p, target_ulong kernel_addr) { if (set_sp) { - bl_gen_load_ulong(p, BL_REG_SP, sp); + bl_gen_load_ulong(cfg, p, BL_REG_SP, sp); } if (set_a0) { - bl_gen_load_ulong(p, BL_REG_A0, a0); + bl_gen_load_ulong(cfg, p, BL_REG_A0, a0); } if (set_a1) { - bl_gen_load_ulong(p, BL_REG_A1, a1); + bl_gen_load_ulong(cfg, p, BL_REG_A1, a1); } if (set_a2) { - bl_gen_load_ulong(p, BL_REG_A2, a2); + bl_gen_load_ulong(cfg, p, BL_REG_A2, a2); } if (set_a3) { - bl_gen_load_ulong(p, BL_REG_A3, a3); + bl_gen_load_ulong(cfg, p, BL_REG_A3, a3); } - bl_gen_jump_to(p, kernel_addr); + bl_gen_jump_to(cfg, p, kernel_addr); } -void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) +void bl_gen_write_ulong(const BlCpuCfg *cfg, void **p, + target_ulong addr, target_ulong val) { - bl_gen_load_ulong(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sd(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } else { - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } } -void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(const BlCpuCfg *cfg, void **p, + target_ulong addr, uint32_t val) { - bl_gen_li(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_li(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); + bl_gen_sw(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } -void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(const BlCpuCfg *cfg, void **p, + target_ulong addr, uint64_t val) { - bl_gen_dli(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_dli(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); + bl_gen_sd(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 1b44fb354c..8e210876e1 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -325,23 +325,24 @@ type_init(boston_register_types) static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { + const BlCpuCfg bl_cfg = { }; uint64_t regaddr; /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* @@ -352,7 +353,7 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) * a2/$6 = 0 * a3/$7 = 0 */ - bl_gen_jump_kernel(&p, + bl_gen_jump_kernel(&bl_cfg, &p, true, 0, true, (int32_t)-2, true, fdt_addr, true, 0, true, 0, kernel_entry); diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 6e4303ba47..a989637d3b 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -165,6 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) static void write_bootloader(CPUMIPSState *env, uint8_t *base, uint64_t kernel_addr) { + const BlCpuCfg bl_cfg = { }; uint32_t *p; /* Small bootloader */ @@ -178,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base, /* Second part of the bootloader */ p = (uint32_t *)(base + 0x040); - bl_gen_jump_kernel((void **)&p, + bl_gen_jump_kernel(&bl_cfg, (void **)&p, true, ENVP_VADDR - 64, true, 2, true, ENVP_VADDR, true, ENVP_VADDR + 8, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 664a2ae0a9..fc485cc884 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -624,6 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, static const char pci_pins_cfg[PCI_NUM_PINS] = { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; + const BlCpuCfg bl_cfg = { }; /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN @@ -635,29 +636,29 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, /* setup MEM-to-PCI0 mapping as done by YAMON */ /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(p, /* GT_ISD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(p, /* GT_PCI0IOLD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0IOHD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(p, /* GT_PCI0M0LD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M0HD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1LD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1HD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); @@ -668,16 +669,16 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); - bl_gen_jump_kernel(p, + bl_gen_jump_kernel(&bl_cfg, p, true, ENVP_VADDR - 64, /* * If semihosting is used, arguments have already From patchwork Mon Sep 30 07:34:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831527 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1833165wrw; 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd564d331sm8359558f8f.10.2024.09.30.00.35.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 05/13] hw/mips: Add cpu_is_bigendian field to BlCpuCfg structure Date: Mon, 30 Sep 2024 09:34:42 +0200 Message-ID: <20240930073450.33195-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add the BlCpuCfg::cpu_is_bigendian field, initialize it in machine code. Bootloader API use the ld/st_endian_p() to dispatch to target endianness. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/mips/bootloader.h | 1 + hw/mips/bootloader.c | 10 +++++----- hw/mips/boston.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index 744eb11d0e..ef778a38d0 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -13,6 +13,7 @@ #include "exec/target_long.h" typedef struct bl_cpu_cfg { + bool cpu_is_bigendian; } BlCpuCfg; void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr); diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index ee1a1c4f20..258cc5d8c8 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -58,9 +58,9 @@ static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, uint32_t insn) { uint16_t *p = *ptr; - stw_p(p, insn >> 16); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 16); p++; - stw_p(p, insn >> 0); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 0); p++; *ptr = p; @@ -74,7 +74,7 @@ static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr) } else { uint32_t *p = *ptr; - stl_p(p, 0); + stl_endian_p(cfg->cpu_is_bigendian, p, 0); p++; *ptr = p; } @@ -95,7 +95,7 @@ static void bl_gen_r_type(const BlCpuCfg *cfg, insn = deposit32(insn, 6, 5, shift); insn = deposit32(insn, 0, 6, funct); - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; *ptr = p; @@ -113,7 +113,7 @@ static void bl_gen_i_type(const BlCpuCfg *cfg, insn = deposit32(insn, 16, 5, rt); insn = deposit32(insn, 0, 16, imm); - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; *ptr = p; diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 8e210876e1..d4dd242d0d 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -325,7 +325,7 @@ type_init(boston_register_types) static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { - const BlCpuCfg bl_cfg = { }; + const BlCpuCfg bl_cfg = { .cpu_is_bigendian = TARGET_BIG_ENDIAN }; uint64_t regaddr; /* Move CM GCRs */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index a989637d3b..4fe5108845 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -165,7 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) static void write_bootloader(CPUMIPSState *env, uint8_t *base, uint64_t kernel_addr) { - const BlCpuCfg bl_cfg = { }; + const BlCpuCfg bl_cfg = { .cpu_is_bigendian = false }; uint32_t *p; /* Small bootloader */ diff --git a/hw/mips/malta.c b/hw/mips/malta.c index fc485cc884..6e73c896ff 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -624,7 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, static const char pci_pins_cfg[PCI_NUM_PINS] = { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; - const BlCpuCfg bl_cfg = { }; + const BlCpuCfg bl_cfg = { .cpu_is_bigendian = TARGET_BIG_ENDIAN }; /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN From patchwork Mon Sep 30 07:34:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831528 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1833341wrw; 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e9025c517sm147896025e9.0.2024.09.30.00.35.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 06/13] tests/tcg/plugins: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:43 +0200 Message-ID: <20240930073450.33195-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Acked-by: Alex Bennée --- tests/tcg/plugins/mem.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/tests/tcg/plugins/mem.c b/tests/tcg/plugins/mem.c index b0fa8a9f27..3586d05587 100644 --- a/tests/tcg/plugins/mem.c +++ b/tests/tcg/plugins/mem.c @@ -163,13 +163,9 @@ static void update_region_info(uint64_t region, uint64_t offset, { uint16_t *p = (uint16_t *) &ri->data[offset]; if (is_store) { - if (be) { - stw_be_p(p, value.data.u16); - } else { - stw_le_p(p, value.data.u16); - } + stw_endian_p(be, p, value.data.u16); } else { - uint16_t val = be ? lduw_be_p(p) : lduw_le_p(p); + uint16_t val = lduw_endian_p(be, p); unseen_data = val != value.data.u16; } break; @@ -178,13 +174,9 @@ static void update_region_info(uint64_t region, uint64_t offset, { uint32_t *p = (uint32_t *) &ri->data[offset]; if (is_store) { - if (be) { - stl_be_p(p, value.data.u32); - } else { - stl_le_p(p, value.data.u32); - } + stl_endian_p(be, p, value.data.u32); } else { - uint32_t val = be ? ldl_be_p(p) : ldl_le_p(p); + uint32_t val = ldl_endian_p(be, p); unseen_data = val != value.data.u32; } break; @@ -193,13 +185,9 @@ static void update_region_info(uint64_t region, uint64_t offset, { uint64_t *p = (uint64_t *) &ri->data[offset]; if (is_store) { - if (be) { - stq_be_p(p, value.data.u64); - } else { - stq_le_p(p, value.data.u64); - } + stq_endian_p(be, p, value.data.u64); } else { - uint64_t val = be ? ldq_be_p(p) : ldq_le_p(p); + uint64_t val = ldq_endian_p(be, p); unseen_data = val != value.data.u64; } break; From patchwork Mon Sep 30 07:34:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831518 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1828228wrw; Mon, 30 Sep 2024 00:48:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUyhXifuk9UgjF/IZ1gwLKgpCp8g8sbvyPxhGtd7fM13jr14s1BPMFribW9dNq9o61PDW2TSw==@linaro.org X-Google-Smtp-Source: AGHT+IE6aJT7xCB1SLHy7cl0kdcdmBhEk0cH0c2foKHm9HxvOcXtFu9sLQYU7rqFnMp+QMYBtUPc X-Received: by 2002:a05:6214:5692:b0:6cb:50c8:b5f7 with SMTP id 6a1803df08f44-6cb50c8b73amr86023836d6.52.1727682515933; Mon, 30 Sep 2024 00:48:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727682515; cv=none; d=google.com; s=arc-20240605; b=lm/td0DsROecXQ/qeKnROMCBQ1ZV6ECzXsraw/DAfPRfMyAnL7obuayxXbR/WO9hhD 64nCnbXLFqwSqYEiVx3Wif4CjhiPRZbqM6fC7KYm4fX/WZJk1ypb0VcfQZS7fosp0sEa V/o2V89PF7lkZK1jYnBp8XpD1ammJo07MrMFB13t3OW6I/1k1TC4trkjnUOlWDDqCEee W3LLOAlQAVEd4+vsW8Evjpk5NkuqWc+oRVNqWOO4k6Aetk3eyZitYnxAIScK3Ds2ZzNe ykIqup4i52erxNpi2tLqMmSAVy8zjs34pWm/uByAZza48WLe6NMVfgtI2UXkCqRVIN8+ sE6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PTheN6LnDYE/7gHrhVuAVd6VlwGt/9Pb92gg++hmAlc=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=Gzhwom74R2zPqyI7q839EZ9nYssQXuv212OB1J1R8bk2wRN7qHGH4SP5EcTCFJYo9D 4ZFGi7A4sjUq35tQ3FejzmeaioVmBQPAb4enWquKkBAbxYA8ZkDSukxkJisM2WrXBogh TRVcpnJrLjLPQp/kji2plR/2NFMh/6R+C0xBnrS9xrdCbYkBLlxa/PKKSGdkBuUudYBx 4fNYUSsfX0LOagKx9bzGDynX0whlhXyzxJ+IHKj0dKgKuV/3elq+vThNWn09nyhxlW7i xKh41V6dJoplNpH4P52GKlBdqLaLSQuDGZ16qEV8nnEAwgJwiU8MmgngznN0P4YJSbH9 2V6Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X3JHrWqG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e969ffce1sm142805165e9.28.2024.09.30.00.35.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 07/13] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry Date: Mon, 30 Sep 2024 09:34:44 +0200 Message-ID: <20240930073450.33195-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (deferred) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move code evaluation from preprocessor to compiler so both if() ladders are processed. Mostly style change. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier --- hw/xtensa/xtfpga.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 955e8867a3..228f00b045 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -415,8 +415,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) } } if (entry_point != env->pc) { - uint8_t boot[] = { -#if TARGET_BIG_ENDIAN + uint8_t boot_be[] = { 0x60, 0x00, 0x08, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -425,7 +424,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 0x0a, 0x00, 0x00, /* jx a0 */ -#else + }; + uint8_t boot_le[] = { 0x06, 0x02, 0x00, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -434,14 +434,16 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 0xa0, 0x00, 0x00, /* jx a0 */ -#endif }; + const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be) + : sizeof(boot_le); + uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le; uint32_t entry_pc = tswap32(entry_point); uint32_t entry_a2 = tswap32(tagptr); memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); - cpu_physical_memory_write(env->pc, boot, sizeof(boot)); + cpu_physical_memory_write(env->pc, boot, boot_sz); } } else { if (flash) { From patchwork Mon Sep 30 07:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831532 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1843992wrw; Mon, 30 Sep 2024 01:45:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUQafSWfCim3VMqBVmJl/xOxw5qOYPb6p30Qom7GUzYLUnvo9yKne1zDS75y3DfTSQdZtpApQ==@linaro.org X-Google-Smtp-Source: AGHT+IHm+GJAP625kihWkORughfVK1DnszIITNPBI7YgDKw/cbdvXSRhwHbS6xnxX8t/o8kDCQ8X X-Received: by 2002:ac8:7c45:0:b0:456:8b5e:bcf3 with SMTP id d75a77b69052e-45c9f2a75ddmr181329461cf.52.1727685917111; Mon, 30 Sep 2024 01:45:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727685917; cv=none; d=google.com; s=arc-20240605; b=kCwtrpAgZsVBS+A7ufZsiwoGPBdhTBh77GGdwHT+92raFwQty2rszrE+qAViq5CWZI 08Wr2j4Zr/SZ4NpJGl/GU07vBljbuoh3CIzBk5P3ech1xpVDibDcbdNfUXKjbCUaOnzw 8RuOg5+vzVVzg3/w1ehT89cE96y6j4w2I6hyCEiCbSaKMVVjj/+dpBOvOlOXoaKNO2sY PorytQZcYc8oIMhZhqDRCi9czWJ5i36Vlnu4jZCilv1hkrAANYThc9Ky9xz0tc/8nX3x TL40RIjt74QQmWGTnAVsurfWv0CFPIkwMGSrKDBjnYPS3n9dZQfBKZy1hwsrZcmuHsbk 38Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Zn1QOBKpxwHC7pwp1nDkwIemv7qUJthxbF0WBocU5ZE=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=HPNOvqzwM+MIPGVQLcJ1d70dnXbr+Qf0Gl4PGj76FcQYD5fkn7em/tMy3M50fKM/jD iiyaAYT+WtAJRrqEJvzG6dG9NQStNXnB1IZCeqR8scKE9chddcefrOa7Xraw2aBGKUqB LcPO7HjQK7O5eubu09c3ftHuHkRnLAA7UcnapRCbBDM9XtYnrl4a/wmqQjj2g/5MiV/T UlFkM19wji9Izej4/7mEayM9CLQUi2jfH4RpUuSnWJ9i+jfxbUL4gjmaqK6fRrZkmse9 rMlZa1OXEFivWOeFuXzmOidW3zS7vibOwMuKdvH4wJNXkk9rrOlHIcU47j9rp9tIQo1X jITA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vbqqrfJs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd565e881sm8323063f8f.44.2024.09.30.00.35.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p() Date: Mon, 30 Sep 2024 09:34:45 +0200 Message-ID: <20240930073450.33195-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (deferred) Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace a pair of memcpy() + tswap32() by stl_endian_p(), which also swap the value using target endianness. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/xtensa/xtfpga.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 228f00b045..521fe84b01 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -438,11 +438,9 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be) : sizeof(boot_le); uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le; - uint32_t entry_pc = tswap32(entry_point); - uint32_t entry_a2 = tswap32(tagptr); - memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); - memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); + stl_endian_p(TARGET_BIG_ENDIAN, boot + 4, entry_point); + stl_endian_p(TARGET_BIG_ENDIAN, boot + 8, tagptr); cpu_physical_memory_write(env->pc, boot, boot_sz); } } else { From patchwork Mon Sep 30 07:34:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831529 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1833695wrw; Mon, 30 Sep 2024 01:07:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXocXKWRTF8bOT7fJeqbo4Vg6Lbs+Vp8MJLBeEufH282ZBieZs2OZmXDDZORXmwLEtcbM+omg==@linaro.org X-Google-Smtp-Source: AGHT+IEvFTLyt/YHRrvtrwqZsxVX2gHHUYEEkNd46QkJEg+3EnBbcW2rFRvgt5iHGnFoc/G+nJuI X-Received: by 2002:a05:622a:188a:b0:45c:a600:c0f with SMTP id d75a77b69052e-45ca6000dd2mr146062451cf.15.1727683621469; Mon, 30 Sep 2024 01:07:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727683621; cv=none; d=google.com; s=arc-20240605; b=h5SekpxuuYsU0Oe3H5FSZKjcPqyih2P+cXY0dA798xV4eEoXgXdHFIhK+XJyY6g1va 3b2pGtxMwED+Ebih9C9jvtVgLCCP0uCtfWe6pUDVKEwehp/8m/nOsMNRqVp6KoxQ10V9 Md9Flyd3Hd3bnOLVIeGCVphCmCXEFGxvFKempHjOPu242tj6Uvyh6K8EBUQKPk3Tku8Z hkTpcuH5zq1n2uaZe1gVnZWebOC+8RhYXMsxha/Ks6VliO8JZUVkeGslpARlRozWB2Vx HonOjLP0M/Ipd6fHn+6fq6FRdSAYgvZVXiGqiiLl13OicK13vo+n4DIdlsitidKVADci 52Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RyfJ60ZwiZ7J7acEGIws/WvnHoIJtgQD50MT+DOE6Vo=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=fZ4EFbyRDjdTd5mRNOURFaLNsaUrVum1fLveWWj8DfkJx6h7y4+kJqcLf5nYuN+CTE X/PV5aPEtRj+vr6jSUW4mj8LZ1z8L4s4JJbrf0Oa4lNyeKUQjmlQyuW9Gvh3qu6ms+Uh 2n2sPNZNpxjN9WfA+TUnuTPqWNLZzQkLUDlrTz9IhrOBQRsx22HbVJMELFZrM2mAR4Xq Gi3c7jSrtiXdbbbXe5//zfjLJHM7YVt8tKfST4Dk7fiRb3sUDyTNAYb8r8CLuukHlw8u E7xW7PkNE0CzgLElVjAhNonQNMhnLDQlGqnQ62SkoT/YasySzOnNEJrRZg+nWahH/Dlc DDVw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Iw0cw9jh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a52308sm141836745e9.43.2024.09.30.00.36.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 09/13] exec/memory_ldst_phys: Introduce ld/st_endian_phys() API Date: Mon, 30 Sep 2024 09:34:46 +0200 Message-ID: <20240930073450.33195-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce the ld/st_endian_phys() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_phys() methods. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- TODO: Update docstring regexp --- include/exec/memory_ldst_phys.h.inc | 66 +++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc index ecd678610d..8ea162b40d 100644 --- a/include/exec/memory_ldst_phys.h.inc +++ b/include/exec/memory_ldst_phys.h.inc @@ -74,6 +74,16 @@ static inline uint16_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL); } +static inline uint16_t glue(lduw_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr addr) +{ + return big_endian + ? glue(address_space_lduw_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL) + : glue(address_space_lduw_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldl_le, SUFFIX)(ARG1, addr, @@ -86,6 +96,16 @@ static inline uint32_t glue(ldl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL); } +static inline uint32_t glue(ldl_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr addr) +{ + return big_endian + ? glue(address_space_ldl_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL) + : glue(address_space_ldl_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + static inline uint64_t glue(ldq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldq_le, SUFFIX)(ARG1, addr, @@ -98,6 +118,16 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL); } +static inline uint32_t glue(ldq_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr addr) +{ + return big_endian + ? glue(address_space_ldq_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL) + : glue(address_space_ldq_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val) { glue(address_space_stb, SUFFIX)(ARG1, addr, val, @@ -116,6 +146,18 @@ static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t va MEMTXATTRS_UNSPECIFIED, NULL); } +static inline void glue(stw_endian_phys, SUFFIX)(bool big_endian, ARG1_DECL, + hwaddr addr, uint16_t val) +{ + if (big_endian) { + glue(address_space_stw_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stw_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} + static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) { glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, @@ -128,6 +170,18 @@ static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t va MEMTXATTRS_UNSPECIFIED, NULL); } +static inline void glue(stl_endian_phys, SUFFIX)(bool big_endian, ARG1_DECL, + hwaddr addr, uint32_t val) +{ + if (big_endian) { + glue(address_space_stl_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} + static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) { glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, @@ -139,6 +193,18 @@ static inline void glue(stq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t va glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } + +static inline void glue(stq_endian_phys, SUFFIX)(bool big_endian, ARG1_DECL, + hwaddr addr, uint64_t val) +{ + if (big_endian) { + glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} #endif #undef ARG1_DECL From patchwork Mon Sep 30 07:34:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831526 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1833021wrw; Mon, 30 Sep 2024 01:05:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVrxxgrfK9LoRLg5/e1rTOfRrumQp1GC1HBj17TW/MG+4HQ6zznB+peayvn+bqQOETxXFNe2w==@linaro.org X-Google-Smtp-Source: AGHT+IHHKihocnO6Aww9zN0671vfFWVelbXfPyLY1JvwEmpHRCuE96Tthm2wYA/cEkRCZtXI3NVi X-Received: by 2002:a05:620a:414b:b0:7a9:d0d2:a5fd with SMTP id af79cd13be357-7ae378c28f1mr1674636985a.49.1727683507065; Mon, 30 Sep 2024 01:05:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727683507; cv=none; d=google.com; s=arc-20240605; b=caTz5vejWqeXMU/NoMtNs4DwmKxhcAQOSlevSca9/XvFmchyE3xclv305jQZMaKNIW vtz5whZnhvIRtffYb6WHU32ltWgKG0I/LvQU42KwIg/r+IjJZxvon8e+NXTNIFFD48Ze POVEfX3ZrwKDc9nQijJtg7CJ7kQwIXPujOuqRqLh4ZO/h0BNt1TzO2+eQ5b8jay22DQ3 piPpzV9gVIQbnS2cS9lKAmbcLBwW2dVQKXhmSciRPyLXHQwZcNgTucQu121NvezHGuGg wVgiVjgKTySq9sWo7LEmEPfPMYuTyO3fyeL+M6Sb8pDGa0X6+gE+r6gNCgteGOO4unY1 MTew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=No3UNTdnI2PUra55xn+9Km9SFh7ve86YSqv3e3Ulz3I=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=FmQgVUG6uRYNBpWPahcvAgaT+5IxQ4lr1/9ONc+q+f15yrrIypR4wgn4bkB2Yl4Qgh FOGeMVVNhDkuU77xPcGx8FeNnEQUqp9N3hC0kSGZZSnMI5g+VBQYpbKcBa/z99zTj2xw tRv7tjL0PGoY3LYOCOqI4kJ6ufJ0Nq+aPsxyI305/aqe8ZOutjBNFF5Idb0a+eil4PO8 6nqJBFbU8YT4ikoqN1Vdm7QVjtCA17pFDba0w7WSrMtY8VIaWBY+hHiWcIWBL5mG9ljn 8WC+BZmn7xE5+SPkeTiuzvaNiItQk5YKb1yqrIqUYyHMcLvvl7Xb798tS4pqfcIrCH2A 9m4g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cGPdYwHR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a54dd4sm141894255e9.45.2024.09.30.00.36.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 10/13] hw/virtio/virtio-access: Use ld/st_endian_phys() API Date: Mon, 30 Sep 2024 09:34:47 +0200 Message-ID: <20240930073450.33195-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Refactor to use the recently introduced ld/st_endian_phys() API. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/virtio/virtio-access.h | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-access.h index b920874be8..37a42407ea 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -43,30 +43,21 @@ static inline uint16_t virtio_lduw_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - return lduw_be_phys(dma_as, pa); - } - return lduw_le_phys(dma_as, pa); + return lduw_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } static inline uint32_t virtio_ldl_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - return ldl_be_phys(dma_as, pa); - } - return ldl_le_phys(dma_as, pa); + return ldl_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } static inline uint64_t virtio_ldq_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - return ldq_be_phys(dma_as, pa); - } - return ldq_le_phys(dma_as, pa); + return ldq_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } static inline void virtio_stw_phys(VirtIODevice *vdev, hwaddr pa, @@ -74,11 +65,7 @@ static inline void virtio_stw_phys(VirtIODevice *vdev, hwaddr pa, { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - stw_be_phys(dma_as, pa, value); - } else { - stw_le_phys(dma_as, pa, value); - } + stw_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa, value); } static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa, @@ -86,11 +73,7 @@ static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa, { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - stl_be_phys(dma_as, pa, value); - } else { - stl_le_phys(dma_as, pa, value); - } + stl_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa, value); } static inline void virtio_stw_p(VirtIODevice *vdev, void *ptr, uint16_t v) From patchwork Mon Sep 30 07:34:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831531 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1834349wrw; Mon, 30 Sep 2024 01:09:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXSvZ0s/fDI5oJPzYCI0e6aSDL0WiY1EFSWouorSqy4T/tZ3BP2LCXThZSO2MBnTnG9+4advw==@linaro.org X-Google-Smtp-Source: AGHT+IFI9y0MShwoLPmFHq/UAlD9D1ZOhOf2r30NnO2Q214k0ZqsqpDhk/warvn+cB+KbnxXRxqN X-Received: by 2002:a05:6214:328e:b0:6cb:2ad6:78ef with SMTP id 6a1803df08f44-6cb3b5c6732mr162583166d6.4.1727683744912; Mon, 30 Sep 2024 01:09:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727683744; cv=none; d=google.com; s=arc-20240605; b=AaihZ7dHLZ7mFkAO6yR7UZ1oKNTXJxw6cFe347MkIbBuQjtpGGEt+SxU4nFOpyUpJB 28j6uTRa//hV5DNmhCe9WxQ5KIvB7Pb32ktNJNn0N1bV+8BwUffuo1eNsfAGZ/Cv00+B OddWLq/hV+w1yT8clncfnz9pE34cU0iriz3ynCqA4fWsFRiSE5UBp+DcPbuQrn6/mBzV a6Btj9PkJA61pC7H1q1eVRGZ+6tQeBwbiSg4EdgtUd39GTcHViIK5aMq3db11rgWKNnu OZkeuvy1HFsS2toA3dm9T/fqf/Px9dwio4EKKdUANq0T8ejIGLJp4Flx/E32QL77o9dL 5ZHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=olm5MEqTuo7Wlc02c6b6qRoX+TEZG1pRsM1M0qwZSUk=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=lQhdEi7twUSEwxIztqrobWz5Zhk3zaFrQV/mxgqQ95WexdOZ4Ijqk9Rf24yjks+Ic2 9Sd6YPhZ/cCDRLH6rCV0vvnWj969dK3TXLrn6e6QAB5nF2F/Cmi2/Yzyy1E0RUj6ViMI fw7qZy8UO5i8hsxGFs9lHPqzWgvgu0QVl5UXLZXCp5TwESTm2ZSco7rqxDaTykmIv18S TjXoHvNvNB73d55G58IvE93FSC00BAcOFEcLZ9koAaqaapO8ObDRSg6n3SRtMmMXD9V4 7NKOtXwu1e6HTOjmgIvziv24RjFK5dFox8LmQOFA0CKLs7WiTMUZgIJC8mnlTX6Z5mWW b/Dg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zqYpeUnr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd56e6665sm8343859f8f.54.2024.09.30.00.36.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 11/13] hw/pci/pci_device: Add PCI_DMA_DEFINE_LDST_END() macro Date: Mon, 30 Sep 2024 09:34:48 +0200 Message-ID: <20240930073450.33195-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define both endianness variants with a single macro. Useful to add yet other endian specific definitions in the next commit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/pci/pci_device.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index 91df40f989..ff619241a4 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -298,13 +298,14 @@ static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ } +#define PCI_DMA_DEFINE_LDST_END(_l, _s, _bits) \ + PCI_DMA_DEFINE_LDST(_l##_le, _s##_le, _bits) \ + PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) + PCI_DMA_DEFINE_LDST(ub, b, 8); -PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) -PCI_DMA_DEFINE_LDST(l_le, l_le, 32); -PCI_DMA_DEFINE_LDST(q_le, q_le, 64); -PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) -PCI_DMA_DEFINE_LDST(l_be, l_be, 32); -PCI_DMA_DEFINE_LDST(q_be, q_be, 64); +PCI_DMA_DEFINE_LDST_END(uw, w, 16) +PCI_DMA_DEFINE_LDST_END(l, l, 32) +PCI_DMA_DEFINE_LDST_END(q, q, 64) #undef PCI_DMA_DEFINE_LDST From patchwork Mon Sep 30 07:34:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831520 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1828232wrw; Mon, 30 Sep 2024 00:48:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWZBLaQeJxB1yTSBrC3810FYW3q+9L6FtJztdp7mfT8/5j9DVnDJSMK5oJVj43hrqBIqh6VKw==@linaro.org X-Google-Smtp-Source: AGHT+IFlacHafwS/2rK9fGGPTkGAZZr3lkhUhXM0YYqzjIj7eW5sxBDOUhzzTfP6xVNQ4ZBT4rRl X-Received: by 2002:a05:6214:5f0d:b0:6c5:3122:ffac with SMTP id 6a1803df08f44-6cb3b6497ccmr125304236d6.45.1727682516444; Mon, 30 Sep 2024 00:48:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727682516; cv=none; d=google.com; s=arc-20240605; b=MMxvvhoqL0mzUabN8bSnMrJLh1N7Xmy39Q+PSbd5XaFUqwdGL1idrtSOvU40VEEX7x 5qEHx0Y4UCMAGRiEqNMnb6WwdjQY/9q8BzNjNnm/T2jmuq0XEoUmbrd0k/orn1gvDBfN HqB8h75J4V6FMTVi0pr63aXy6GvOrrDAnpZZL5pWNIStpzLyMPSD+1V6kvFamxtNj8fI JHTP+hlvDBcJDk08WRACGxi98ypLHy5rQHImfd5oxKgH1pJVODZ65ByGC/p3vbZ0M0aP 1ituIh/tEfiNkCvK5KQ8VYBSUxUwUuMQJ1XNAIjIoryJfEC4zmZo1CaayOi7PY25c3O3 OPzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=J3QK0sGMtG8TI1HL5/V5FwLZQoUZnlZNYr8FgmUN/RY=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=hLac8JOxCn9I3UGYeHYi5TmUyFML9DwIjGywndU0IaGbi7Y+51+m7k/A36csIafM97 qkpQxVVRD2aMhd9nWYNUM09rWvKH+nMomXA9e1TjIdsoLSRV4+mj09tzhB6Nlftyyqq1 0XuqchNVwHza/shEbZy92Tbh691ro5+sVB3jLIbTzzgk4Q1rlrD41/PoZtnczGLplmgP UffAt/MPA2FYZBLCw4sezNw5Gyb9ClQU4nr/fL6tsJJyNwLiG3sn+R1ciRDyDi+oYvV+ Z59ymkst5p/3aSvLgUbBiiv2r+ASIuO3nBQ6vit78TuwhCahk9jiBpBB6HrP3DesLRu4 5EkA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gmg7saSj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a54dedsm142631145e9.44.2024.09.30.00.36.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 12/13] hw/pci/pci_device: Introduce ld/st_endian_pci_dma() API Date: Mon, 30 Sep 2024 09:34:49 +0200 Message-ID: <20240930073450.33195-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce the ld/st_endian_pci_dma() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_pci_dma() methods. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- TODO: Update docstring regexp --- include/hw/pci/pci_device.h | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index ff619241a4..dc9b17dded 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -300,7 +300,29 @@ static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, #define PCI_DMA_DEFINE_LDST_END(_l, _s, _bits) \ PCI_DMA_DEFINE_LDST(_l##_le, _s##_le, _bits) \ - PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) + PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) \ + static inline MemTxResult ld##_l##_endian_pci_dma(bool is_big_endian, \ + PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t *val, \ + MemTxAttrs attrs) \ + { \ + AddressSpace *pci_as = pci_get_address_space(dev); \ + return is_big_endian \ + ? ld##_l##_be_dma(pci_as, addr, val, attrs) \ + : ld##_l##_le_dma(pci_as, addr, val, attrs); \ + } \ + static inline MemTxResult st##_s##_endian_pci_dma(bool is_big_endian, \ + PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t val, \ + MemTxAttrs attrs) \ + { \ + AddressSpace *pci_as = pci_get_address_space(dev); \ + return is_big_endian \ + ? st##_s##_be_dma(pci_as, addr, val, attrs) \ + : st##_s##_le_dma(pci_as, addr, val, attrs); \ + } PCI_DMA_DEFINE_LDST(ub, b, 8); PCI_DMA_DEFINE_LDST_END(uw, w, 16) From patchwork Mon Sep 30 07:34:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 831524 Delivered-To: patch@linaro.org Received: by 2002:a5d:66c8:0:b0:367:895a:4699 with SMTP id k8csp1831947wrw; Mon, 30 Sep 2024 01:02:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUhyXkloeNLX7snEVwC8CjDHQDYmthtXciIo4/1nANubNNogyW/KJuEb0dMJJVuAmvlACkHlQ==@linaro.org X-Google-Smtp-Source: AGHT+IFvFg7QF+Fe0BnyUOWqV1BKkZIQKAicavlCsBngDvPNsw5nbsmfjxTKkUOdaDzgCafrAKWv X-Received: by 2002:a05:6214:3d02:b0:6cb:3afd:f9f1 with SMTP id 6a1803df08f44-6cb3b5c54ffmr141233936d6.8.1727683328938; Mon, 30 Sep 2024 01:02:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1727683328; cv=none; d=google.com; s=arc-20240605; b=DvIJ4ijsT1YGyR4COu9nvcfahglzdSUhS/zW2+ZZst3yAN4DRLmyauZd8DJKIHkaP8 v1B14YKxvu+RF8KsSLh2dLbwueJT43YpVFkDsb+ZvW58+M9G9C8Vfah4nc1F4ZDk55Ei U13OkSUxXDU71g5FY5kM6zEZ/FAnu2+3GjsR2OkS9MU0VBv62APZmNcSll1lA3ZuPzOE fmyv1RMXI1A+VCuJ2CBfw6y1+AnKh1FIMpV99nPjv5YiUYg3AD9IzEi4MOAPHEZ1e1QY qd3vftkqNcVF0l9GFxiz/zJOiIBr8iaZFp7xn6DWBcfoqaLHMnGv3ucFWNcArPbfxvne gzXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qgFNx5loGg07bkVRCAPUaZ+t66SDahiEcwbYBeR9pKk=; fh=Wy2Q3sNWPDKxNwELUcZZKTFep4jJmSUk04d3iQNw3B8=; b=NXTu971B0QorANL09KmgVG0co8ssXqKXRCNvxHMvDaaWU1RH2s78LOr+dr5NczR/wJ sN8iZWFx9GVikeHN0lDDltUUdBWD0Bq3Lv8C6LMVqg5hiGwd2uc77KvqxMCu1ri+4R+n Kg4ASqYJc9ljRjNU/MXWD6ShMGtoQ24omn62ahy5yUxaASSITpVVzxCvJ0jrBGjXza03 sOF1ILqqZCQUaqT+ZzqpbiOuhN2ixvb3p685/+/yuZx8MtwBToTRT15GcqRXDRqvVv5J v35f5c5AL+uAoK/Rgtu+C8GlHA+LyC0cIPyuoH861GQmCP10y5q3keqoq3lnVV7fJzwy Toxw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OcrhSLLd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd57427c6sm8356329f8f.96.2024.09.30.00.36.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 13/13] hw/net/tulip: Use ld/st_endian_pci_dma() API Date: Mon, 30 Sep 2024 09:34:50 +0200 Message-ID: <20240930073450.33195-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Refactor to use the recently introduced ld/st_endian_pci_dma() API. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/net/tulip.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/hw/net/tulip.c b/hw/net/tulip.c index 9df3e17162..6c67958da7 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -71,36 +71,24 @@ static void tulip_desc_read(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { const MemTxAttrs attrs = { .memory = true }; + bool use_big_endian = s->csr[0] & CSR0_DBO; - if (s->csr[0] & CSR0_DBO) { - ldl_be_pci_dma(&s->dev, p, &desc->status, attrs); - ldl_be_pci_dma(&s->dev, p + 4, &desc->control, attrs); - ldl_be_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); - ldl_be_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); - } else { - ldl_le_pci_dma(&s->dev, p, &desc->status, attrs); - ldl_le_pci_dma(&s->dev, p + 4, &desc->control, attrs); - ldl_le_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); - ldl_le_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); - } + ldl_endian_pci_dma(use_big_endian, &s->dev, p, &desc->status, attrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 4, &desc->control, attrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 8, &desc->buf_addr1, attrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 12, &desc->buf_addr2, attrs); } static void tulip_desc_write(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { const MemTxAttrs attrs = { .memory = true }; + bool use_big_endian = s->csr[0] & CSR0_DBO; - if (s->csr[0] & CSR0_DBO) { - stl_be_pci_dma(&s->dev, p, desc->status, attrs); - stl_be_pci_dma(&s->dev, p + 4, desc->control, attrs); - stl_be_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); - stl_be_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); - } else { - stl_le_pci_dma(&s->dev, p, desc->status, attrs); - stl_le_pci_dma(&s->dev, p + 4, desc->control, attrs); - stl_le_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); - stl_le_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); - } + stl_endian_pci_dma(use_big_endian, &s->dev, p, desc->status, attrs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 4, desc->control, attrs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 8, desc->buf_addr1, attrs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 12, desc->buf_addr2, attrs); } static void tulip_update_int(TULIPState *s)