From patchwork Fri Nov 22 15:07:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 180064 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp353999ilf; Fri, 22 Nov 2019 07:08:58 -0800 (PST) X-Google-Smtp-Source: APXvYqwLMqDtjkqyQfFUbmg6iIBoYA22yyJnxnHiNpDxU/u5eUUl7n7ZEs3mRWnvkIVV5x5qySzO X-Received: by 2002:a17:906:3495:: with SMTP id g21mr23085946ejb.190.1574435338786; Fri, 22 Nov 2019 07:08:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574435338; cv=none; d=google.com; s=arc-20160816; b=y7qsFGXSc0JreYjSwdelHpt1ge369b3uD4A9KnH19T93q5brckLHIryJelK2lWrh0n p4dZRoMCsg10ynwiK6v3LZavPeonK46Ern1rooebwzS8Vqlqi/1Ps4r45GHPLeaAHbSF 6UGBXXLCv03wELIGxpyim4v8Z6puOyg7Z2n9w7sMF86VOcIYtAXYZsSVLLkLNfi9ZdA9 SOKagsuBZk0ZD/xLaDxZTdql1judyXBBMCGIIbZD6b5droL9GFFdg6hDNOV/tUeHTR5v T4Prnp6DLRKIDjVqrqVgKT6pt7FPkbkoVUzCfVYqr2dZW8pNAO7ZsgbDQqX3VMJbLPK3 Dheg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=+pVRv0zmwM6r6qh3u7jefx+roN9IpRfJikQs29Fs7Mc=; b=1HeZPqaLrFFAOf8y5RX3ISN1U7g4oay6XHEKECw28a1V/9DR9MkP+4xkPftc1uWavu yrfS9rEHR19GLmt+q6rM3nmdQLKQl7+0xKtDSRXRcml3b3Gyh/hST2Ltt7qRfirpIgEB K8NgJFS2fUnA5v40EaFBr/RanxMiZaDcFWIXRE+b3mM46bW4hscY/QwGRKTCxIK4BPEY 8fczEAnp4e8/Nh3fF6JK/aqbiDIlXvQXn1a0Ykv/tCcNK/b3Uk+FUILUiR/QLsFZ24RR Da4clmi+3oLi4tRzC3IvTUJ/xZB4WjCghreajiWgYwF972pA+U7HN6IrBgxeKurVAzdw +8+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r6E4DMv1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z33si4925889edb.183.2019.11.22.07.08.58; Fri, 22 Nov 2019 07:08:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r6E4DMv1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727097AbfKVPIz (ORCPT + 26 others); Fri, 22 Nov 2019 10:08:55 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:46104 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726100AbfKVPIy (ORCPT ); Fri, 22 Nov 2019 10:08:54 -0500 Received: by mail-pg1-f194.google.com with SMTP id r18so3443288pgu.13 for ; Fri, 22 Nov 2019 07:08:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+pVRv0zmwM6r6qh3u7jefx+roN9IpRfJikQs29Fs7Mc=; b=r6E4DMv1Ew1POCiZziHs0YwoBfyHUTq3KYUrRgtfb4vl0UK6dNOFfiH6gUaxO4D+Si nAKdspmLW+9QlY4Dohyh1Y82LJgbTL0/J+mKWoqN6tCCVfh66MKivVt6hmQuVvIqEEjr ycvmCeYBRQQ4BnbJ9FFQzrsZ9+nU3Hfhf57i6taLJTOwMXrUiGLUZgn9OLRcdhzXVGhV kOMfXA52pUudqEQZhIJNepSok+DmAQGPD9MLwvVpKOf2srwXLYtceFOIueJOR75AMNjj 0C/TK8wEk3A4oDUYhjl8zavOjysg3uzc3fAFPCObboqKbmjcJFey4/qAn6W8vVKxstfY XZ7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+pVRv0zmwM6r6qh3u7jefx+roN9IpRfJikQs29Fs7Mc=; b=UT4j+c0WJRDgbFHAbAPDUP2bCu/acYs8yeJH++uA8oI97HekMVrNDPe26tFuu+Xani sdr1aeyrb6AuFA1xNtjsrIham+pEnG9izaPArjQpEDx9k9u3VXURgwTWVj4KGPJbXPqp JMlT1+d5N/XaxkYGXILlPi/lRG0lYSNSBFXkT1KgaykU3yxgW/PpAT6mU5/wrrhtWUM7 CIuHzEeBxWhmxfkgorye811i4iyq87okTfZHFIYiPl+izgfbBSkr/aeJRk4AIhsYvRSM pMHZ4nH/uHNOhqsUjlkHN4gwsJRJbcaR+KhH97BQB2F89qsJrgTDB6RwSPutfdUC9dp5 oiKw== X-Gm-Message-State: APjAAAX0LILhMb5bRYaPxfbHgxiwqvIkVEqOaOLwGF4+RZ2hKb/G3KPz SeM554dMQvgYZCZLB/zzDLc8eg== X-Received: by 2002:a63:c18:: with SMTP id b24mr11367250pgl.291.1574435333618; Fri, 22 Nov 2019 07:08:53 -0800 (PST) Received: from localhost.localdomain ([240e:362:496:8600:f5af:2744:25c3:d01a]) by smtp.gmail.com with ESMTPSA id a19sm8066021pfn.144.2019.11.22.07.08.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 Nov 2019 07:08:52 -0800 (PST) From: Zhangfei Gao To: Greg Kroah-Hartman , Arnd Bergmann , Herbert Xu , jonathan.cameron@huawei.com, grant.likely@arm.com, jean-philippe , Jerome Glisse , ilias.apalodimas@linaro.org, francois.ozog@linaro.org, kenneth-lee-2012@foxmail.com, Wangzhou , "haojian . zhuang" , guodong.xu@linaro.org Cc: linux-accelerators@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, iommu@lists.linux-foundation.org, Kenneth Lee , Zaibo Xu , Zhangfei Gao Subject: [PATCH v9 1/4] uacce: Add documents for uacce Date: Fri, 22 Nov 2019 23:07:38 +0800 Message-Id: <1574435261-6031-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574435261-6031-1-git-send-email-zhangfei.gao@linaro.org> References: <1574435261-6031-1-git-send-email-zhangfei.gao@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kenneth Lee Uacce (Unified/User-space-access-intended Accelerator Framework) is a kernel module targets to provide Shared Virtual Addressing (SVA) between the accelerator and process. This patch add document to explain how it works. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/uacce.rst | 176 +++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 Documentation/misc-devices/uacce.rst -- 2.7.4 diff --git a/Documentation/misc-devices/uacce.rst b/Documentation/misc-devices/uacce.rst new file mode 100644 index 0000000..1db412e --- /dev/null +++ b/Documentation/misc-devices/uacce.rst @@ -0,0 +1,176 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Introduction of Uacce +--------------------- + +Uacce (Unified/User-space-access-intended Accelerator Framework) targets to +provide Shared Virtual Addressing (SVA) between accelerators and processes. +So accelerator can access any data structure of the main cpu. +This differs from the data sharing between cpu and io device, which share +only data content rather than address. +Because of the unified address, hardware and user space of process can +share the same virtual address in the communication. +Uacce takes the hardware accelerator as a heterogeneous processor, while +IOMMU share the same CPU page tables and as a result the same translation +from va to pa. + +:: + + __________________________ __________________________ + | | | | + | User application (CPU) | | Hardware Accelerator | + |__________________________| |__________________________| + + | | + | va | va + V V + __________ __________ + | | | | + | MMU | | IOMMU | + |__________| |__________| + | | + | | + V pa V pa + _______________________________________ + | | + | Memory | + |_______________________________________| + + + +Architecture +------------ + +Uacce is the kernel module, taking charge of iommu and address sharing. +The user drivers and libraries are called WarpDrive. + +The uacce device, built around the IOMMU SVA API, can access multiple +address spaces, including the one without PASID. + +A virtual concept, queue, is used for the communication. It provides a +FIFO-like interface. And it maintains a unified address space between the +application and all involved hardware. + +:: + + ___________________ ________________ + | | user API | | + | WarpDrive library | ------------> | user driver | + |___________________| |________________| + | | + | | + | queue fd | + | | + | | + v | + ___________________ _________ | + | | | | | mmap memory + | Other framework | | uacce | | r/w interface + | crypto/nic/others | |_________| | + |___________________| | + | | | + | register | register | + | | | + | | | + | _________________ __________ | + | | | | | | + ------------- | Device Driver | | IOMMU | | + |_________________| |__________| | + | | + | V + | ___________________ + | | | + -------------------------- | Device(Hardware) | + |___________________| + + +How does it work +---------------- + +Uacce uses mmap and IOMMU to play the trick. + +Uacce creates a chrdev for every device registered to it. New queue is +created when user application open the chrdev. The file descriptor is used +as the user handle of the queue. +The accelerator device present itself as an Uacce object, which exports as +a chrdev to the user space. The user application communicates with the +hardware by ioctl (as control path) or share memory (as data path). + +The control path to the hardware is via file operation, while data path is +via mmap space of the queue fd. + +The queue file address space: + +:: + + /** + * enum uacce_qfrt: qfrt type + * @UACCE_QFRT_MMIO: device mmio region + * @UACCE_QFRT_DUS: device user share region + */ + enum uacce_qfrt { + UACCE_QFRT_MMIO = 0, + UACCE_QFRT_DUS = 1, + }; + +All regions are optional and differ from device type to type. +Each region can be mmapped only once, otherwise -EEXIST returns. + +The device mmio region is mapped to the hardware mmio space. It is generally +used for doorbell or other notification to the hardware. It is not fast enough +as data channel. + +The device user share region is used for share data buffer between user process +and device. + + +The Uacce register API +---------------------- + +The register API is defined in uacce.h. + +:: + + struct uacce_interface { + char name[UACCE_MAX_NAME_SIZE]; + unsigned int flags; + const struct uacce_ops *ops; + }; + +According to the IOMMU capability, uacce_interface flags can be: + +:: + + /** + * UACCE Device flags: + * UACCE_DEV_SVA: Shared Virtual Addresses + * Support PASID + * Support device page faults (PCI PRI or SMMU Stall) + */ + #define UACCE_DEV_SVA BIT(0) + + struct uacce_device *uacce_alloc(struct device *parent, + struct uacce_interface *interface); + int uacce_register(struct uacce_device *uacce); + void uacce_remove(struct uacce_device *uacce); + +uacce_register results can be: + +a. If uacce module is not compiled, ERR_PTR(-ENODEV) + +b. Succeed with the desired flags + +c. Succeed with the negotiated flags, for example + + uacce_interface.flags = UACCE_DEV_SVA but uacce->flags = ~UACCE_DEV_SVA + + So user driver need check return value as well as the negotiated uacce->flags. + + +The user driver +--------------- + +The queue file mmap space will need a user driver to wrap the communication +protocol. Uacce provides some attributes in sysfs for the user driver to +match the right accelerator accordingly. +More details in Documentation/ABI/testing/sysfs-driver-uacce. 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Signed-off-by: Zhangfei Gao Signed-off-by: Zhou Wang --- drivers/crypto/hisilicon/zip/zip_main.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) -- 2.7.4 diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c index 1b2ee96..3de9412 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -264,9 +264,6 @@ static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 1-4096, v2 1-1024)"); -static int uacce_mode; -module_param(uacce_mode, int, 0); - static const struct pci_device_id hisi_zip_dev_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) }, { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) }, @@ -669,6 +666,7 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_set_drvdata(pdev, hisi_zip); qm = &hisi_zip->qm; + qm->use_dma_api = true; qm->pdev = pdev; qm->ver = rev_id; @@ -676,20 +674,6 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) qm->dev_name = hisi_zip_name; qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? QM_HW_PF : QM_HW_VF; - switch (uacce_mode) { - case 0: - qm->use_dma_api = true; - break; - case 1: - qm->use_dma_api = false; - break; - case 2: - qm->use_dma_api = true; - break; - default: - return -EINVAL; - } - ret = hisi_qm_init(qm); if (ret) { dev_err(&pdev->dev, "Failed to init qm!\n"); @@ -976,12 +960,10 @@ static int __init hisi_zip_init(void) goto err_pci; } - if (uacce_mode == 0 || uacce_mode == 2) { - ret = hisi_zip_register_to_crypto(); - if (ret < 0) { - pr_err("Failed to register driver to crypto.\n"); - goto err_crypto; - } + ret = hisi_zip_register_to_crypto(); + if (ret < 0) { + pr_err("Failed to register driver to crypto.\n"); + goto err_crypto; } return 0; @@ -996,8 +978,7 @@ static int __init hisi_zip_init(void) static void __exit hisi_zip_exit(void) { - if (uacce_mode == 0 || uacce_mode == 2) - hisi_zip_unregister_from_crypto(); + hisi_zip_unregister_from_crypto(); pci_unregister_driver(&hisi_zip_pci_driver); hisi_zip_unregister_debugfs(); }