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[84.217.220.205]) by smtp.gmail.com with ESMTPSA id 15sm4016640ljq.62.2019.11.25.06.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:33 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, Jorge Ramirez-Ortiz , Niklas Cassel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: qcom: qcs404: Add DVFS support Date: Mon, 25 Nov 2019 15:25:09 +0100 Message-Id: <20191125142511.681149-5-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jorge Ramirez-Ortiz Support dynamic voltage and frequency scaling on qcs404. CPUFreq will soon be superseded by Core Power Reduction (CPR, a form of Adaptive Voltage Scaling found on some Qualcomm SoCs like the qcs404). Due to the CPR upstreaming already being in progress - and some commits already merged - the following commit will need to be reverted to enable CPUFreq support Author: Jorge Ramirez-Ortiz Date: Thu Jul 25 12:41:36 2019 +0200 cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -Removed incorrect newline in the middle of the cpu0 DT node. (This extra newline must have been added by mistake, since no other cpuX node in the same cluster had this extra newline added.) arch/arm64/boot/dts/qcom/qcs404.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) -- 2.23.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ee5ecf413664..03aa80f2814a 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -42,6 +42,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU1: cpu@101 { @@ -52,6 +55,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU2: cpu@102 { @@ -62,6 +68,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU3: cpu@103 { @@ -72,6 +81,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; L2_0: l2-cache { @@ -94,6 +106,24 @@ }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-microvolt = <1224000 1224000 1224000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1288000 1288000 1288000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1384000 1384000 1384000>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-qcs404", "qcom,scm"; From patchwork Mon Nov 25 14:25:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 180166 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp3225012ilf; Mon, 25 Nov 2019 06:25:43 -0800 (PST) X-Google-Smtp-Source: APXvYqxLYoCjg/hpIkTdSw5WpwffKA8m9G2IJ8ZobRlAj2Kbqe6/OstH8k2L6wMBeo28aigvBkzA X-Received: by 2002:a05:6402:611:: with SMTP id n17mr18731744edv.143.1574691943444; Mon, 25 Nov 2019 06:25:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574691943; cv=none; d=google.com; s=arc-20160816; b=KPJhRyF1ApfYbp/quKdqChJywvJKr2JLVRGwql8VOQ32gfk1FqAwU4b8+siQzQC7Pm YPZeLPgHyOiF0xqLCYMlb6klbWMpvcHwAg0BWuXTBADbX5DrZX37GSkZ/3naNOkCIUbv I/0YcBnROHsY0beBECdHJt1bWVC1rNIVNVEklaJOHDhW6gC0hRKHl5ekCurnHGlT/OQC k6tbh5tbLAfikVlWRZDjTST32hdRJT0rlPykAfyqmR3tf3b9qJ9Y+HRMz+1AaV0PQp6Y 37jZ1Map859ldd+pr29VE9MplldpxwLHdQn/oKEaLHQMueOl+QdFCoolgHWQIcqOOtgb vfMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lk8SRgnsKjAXBRx1hwjdc4Ni4aIadkTu9BDcS7y9BzI=; b=BXkDTbv0PZybAtVpJkhxiAG9gO/zrK6awazfj1y9czueebTcM82kYZfdpZZXxa/Bvz PCwBk/jRDq1X8p07bZeUN9IH46jZdVYSQT22eeJXt/lycsoLibGD/BNbLqIKTL15AFVb Uzb1/JYFcBkHWVLSit60XXvwIP/3895cBK+ynceR6uXpuKzpKLA05yQ36AVW83yJqFJ2 xyG0oDDLzALLBgLsvatpsscIRyTRkQYMNUJxJp8zKtf7WSobTDGQr08n/Xc3IyBm+Moi qHWA+83Yjr69ZZYgX2XCbgVUqe6XJoJKCA7EvTgsojGXIvVAOQ2jrDCfOO734IPTeN1V vwGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zchG2SUm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[84.217.220.205]) by smtp.gmail.com with ESMTPSA id 15sm4016640ljq.62.2019.11.25.06.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:35 -0800 (PST) From: Niklas Cassel To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, bjorn.andersson@linaro.org, Jorge Ramirez-Ortiz , Niklas Cassel , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/5] arm64: defconfig: Enable HFPLL Date: Mon, 25 Nov 2019 15:25:10 +0100 Message-Id: <20191125142511.681149-6-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jorge Ramirez-Ortiz The high frequency pll is required on compatible Qualcomm SoCs to support the CPU frequency scaling feature. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -None arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) -- 2.23.0 diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7fa92defb964..e76b42b25dd6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -727,6 +727,7 @@ CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y CONFIG_SDM_GCC_845=y CONFIG_SM_GCC_8150=y +CONFIG_QCOM_HFPLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_ARM_MHU=y