From patchwork Fri Oct 4 10:30:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soutrik Mukhopadhyay X-Patchwork-Id: 832793 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 401A7155393; Fri, 4 Oct 2024 10:31:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037892; cv=none; b=BTGME1p6+a9Zr7CfL6tC7EX4f+gotfie9biBnLNQKJkMMrwPXTrymhyo1lQe3/WDJ0/j638GqZmjmVk/O54T8Eqts5y1gLpMRveuRD+tmE/rS2K7VMkf8hnlHWkDowUJOt/OuVY5yQI6ev2M1dhH2nwSqsbOXDJE2c9mfnpG/9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037892; c=relaxed/simple; bh=5BDwqHpjn2XZ+3cj41neoVTuNLhYlT0kCDBhEm7nnXU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=QpGRRj1ivNVJchw75OrkuWSRh8oByy2odNesbgb9iOGVqYHiUxEu/73oajNhsRlriKisX5iwovHwzkyN5zlaMMgXfDtHhBq2w6lV+oVsETxOOfyhHaZzcy/1SoEs/OwRWtj9Nth08QE8XUjUUL3v51gKW79DkOZL68lM7uTgRMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=i7xkNh2O; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="i7xkNh2O" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493HxtsS017372; Fri, 4 Oct 2024 10:30:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=PKIOy7Ft4cBy5Bf7ui0ydnI8un4Jv8lqb3+8vViK9qQ=; b=i7 xkNh2Oz5vDAaBs8Kicl4GLFbKrdEmPC/QF9FbteE1WjQUJEB4KADCjBKT8Ibr8xm +rpwMcKf9MVPBLN1+/bTNUr/q+QjX1hc+afsmMb8PO671nf/NIowsbW68WtWfz5l U/uq38dSwILqukFwkglRanOB7sA+E5hVuSG5wyCUF1sznllCLgFYIW3z/qDy/G3w eLgERbuERxur5GHQkRq/F6GNVFG00qCj8mibwR5z3U3prRPcur8D+pWoX7WasprV GpRccNK8QhLB1G1b5tgZD10KldnwOa05s6CiZt6a7y3wGn00zGUYwair8ATMi3Kt VUI5kpQwPKeF7KosULvg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42205n1t0n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:30:54 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 494AUomh005779; Fri, 4 Oct 2024 10:30:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 41xavmrk0e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 04 Oct 2024 10:30:50 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 494AUnCT005747; Fri, 4 Oct 2024 10:30:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 494AUn2k005744; Fri, 04 Oct 2024 10:30:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id BD0E25000AE; Fri, 4 Oct 2024 16:00:48 +0530 (+0530) From: Soutrik Mukhopadhyay To: vkoul@kernel.org, kishon@kernel.org, konradybcio@kernel.org, andersson@kernel.org, simona@ffwll.ch, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_khsieh@quicinc.com, konrad.dybcio@linaro.org, quic_parellan@quicinc.com, quic_bjorande@quicinc.com Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH v4 1/5] dt-bindings: phy: Add eDP PHY compatible for sa8775p Date: Fri, 4 Oct 2024 16:00:42 +0530 Message-Id: <20241004103046.22209-2-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241004103046.22209-1-quic_mukhopad@quicinc.com> References: <20241004103046.22209-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9QjkeuBXfO3YqRE1M8swNUgLb7FGgn-f X-Proofpoint-GUID: 9QjkeuBXfO3YqRE1M8swNUgLb7FGgn-f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040076 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add compatible string for the supported eDP PHY on sa8775p platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Soutrik Mukhopadhyay --- v2: No change v3: No change v4: No change --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 4e15d90d08b0..293fb6a9b1c3 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,sa8775p-edp-phy - qcom,sc7280-edp-phy - qcom,sc8180x-edp-phy - qcom,sc8280xp-dp-phy From patchwork Fri Oct 4 10:30:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soutrik Mukhopadhyay X-Patchwork-Id: 832792 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63A3B15ECDC; Fri, 4 Oct 2024 10:31:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037894; cv=none; b=YVMBEHnaMIulV4WrgwPhNtSRvlsAKVnBA70c/e1mri6n+8hqhCN3HH7c812nTiAhkBhvbVzsdZ7PM9OdY1zGa5xMvEIwTPwUAG/GuQu7A/Syg7eHznlgleuFYox6858pUl1nsUmPId31kXyUOwvKpJRAbzBlrE/An+Dc0nmXAtg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037894; c=relaxed/simple; bh=xzxKkKb+YEE2udUyyx43IpqHgIGYiHY09yIISw8ViPw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=C3uyaRL5EZjp9aMaFAGFzsVPGKFflEuiqJgsJvsEyK0fEuZ+V/1h2g1pau/S5+UhgLbaWLxDf1OR0dCwpjeWI4g7seIbpftDPXgJhIvjVny100slbcE7zgiTQ8twVRrklpB1Vi1vJSKUt0eVExgZ20NimMv789qjUgNKk9ZVHDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=J8ITnxSo; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="J8ITnxSo" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493I032j021789; Fri, 4 Oct 2024 10:30:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=R1itHP4dBNV6EjfnQURPAFDJta+dkTf9U361hUTx0aM=; b=J8 ITnxSokGeKd7tYCrJ9EvMh/cT8bb8Jgk84gSTbK1yBrb0XaEg1HUGC7Fkr1Zd2pb Msqfunq3z6U6L+oc7HglNtWsGZMVrVqW+Km1UmH1+H27JGaz11OavneNQFjV+RvN ujZS1Dq/mz45FCntYTskV9nMbqo/0gG+EBzMO/5YG7xepYZ0jyTLbQpFG0Jqkix8 zbWGwKSCgbzsq8UWW6jcIbkg5BNk9MwAo8Z2AGMKI83xGc1Mj6CIaAyZqwC/e2mq VB154UXKb4hDfrsAoNQFoZo/Ddl07lQ//Zjz2QiDExkdd437jfjYKgAdsk4qptSB IwyZop8FqBHHOxgf4ePQ== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42205p9tg0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:30:55 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 494AUoGB005780; Fri, 4 Oct 2024 10:30:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 41xavmrk0f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 04 Oct 2024 10:30:50 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 494AUnA4005749; Fri, 4 Oct 2024 10:30:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 494AUnra005745; Fri, 04 Oct 2024 10:30:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id C18D55000B0; Fri, 4 Oct 2024 16:00:48 +0530 (+0530) From: Soutrik Mukhopadhyay To: vkoul@kernel.org, kishon@kernel.org, konradybcio@kernel.org, andersson@kernel.org, simona@ffwll.ch, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_khsieh@quicinc.com, konrad.dybcio@linaro.org, quic_parellan@quicinc.com, quic_bjorande@quicinc.com Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH v4 2/5] phy: qcom: edp: Introduce aux_cfg array for version specific aux settings Date: Fri, 4 Oct 2024 16:00:43 +0530 Message-Id: <20241004103046.22209-3-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241004103046.22209-1-quic_mukhopad@quicinc.com> References: <20241004103046.22209-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kb1z2-cXWxJ2PIkdzebxU64CuXp8Cku1 X-Proofpoint-ORIG-GUID: kb1z2-cXWxJ2PIkdzebxU64CuXp8Cku1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040076 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: In order to support different HW versions, introduce aux_cfg array to move v4 specific aux configuration settings. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay --- v2: Fixed review comments from Bjorn and Dmitry - Made aux_cfg array as const. v3: Fixed review comments from Dmitry - Used a for loop to write the dp_phy_aux_cfg registers. - Pre-defined the aux_cfg size to prevent any magic numbers. v4: No change --- drivers/phy/qualcomm/phy-qcom-edp.c | 41 ++++++++++++----------------- 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index da2b32fb5b45..2ecff164ec44 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -32,16 +32,8 @@ #define DP_PHY_PD_CTL 0x001c #define DP_PHY_MODE 0x0020 -#define DP_PHY_AUX_CFG0 0x0024 -#define DP_PHY_AUX_CFG1 0x0028 -#define DP_PHY_AUX_CFG2 0x002C -#define DP_PHY_AUX_CFG3 0x0030 -#define DP_PHY_AUX_CFG4 0x0034 -#define DP_PHY_AUX_CFG5 0x0038 -#define DP_PHY_AUX_CFG6 0x003C -#define DP_PHY_AUX_CFG7 0x0040 -#define DP_PHY_AUX_CFG8 0x0044 -#define DP_PHY_AUX_CFG9 0x0048 +#define DP_AUX_CFG_SIZE 10 +#define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 @@ -90,6 +82,7 @@ struct phy_ver_ops { struct qcom_edp_phy_cfg { bool is_edp; + const u8 *aux_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; @@ -186,11 +179,15 @@ static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = { .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3, }; +static const u8 edp_phy_aux_cfg_v4[10] = { + 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp = phy_get_drvdata(phy); + u8 aux_cfg[DP_AUX_CFG_SIZE]; int ret; - u8 cfg8; ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); if (ret) @@ -200,6 +197,8 @@ static int qcom_edp_phy_init(struct phy *phy) if (ret) goto out_disable_supplies; + memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); @@ -222,22 +221,12 @@ static int qcom_edp_phy_init(struct phy *phy) * even needed. */ if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) - cfg8 = 0xb7; - else - cfg8 = 0x37; + aux_cfg[8] = 0xb7; writel(0xfc, edp->edp + DP_PHY_MODE); - writel(0x00, edp->edp + DP_PHY_AUX_CFG0); - writel(0x13, edp->edp + DP_PHY_AUX_CFG1); - writel(0x24, edp->edp + DP_PHY_AUX_CFG2); - writel(0x00, edp->edp + DP_PHY_AUX_CFG3); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); - writel(0x26, edp->edp + DP_PHY_AUX_CFG5); - writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); - writel(0x03, edp->edp + DP_PHY_AUX_CFG7); - writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); - writel(0x03, edp->edp + DP_PHY_AUX_CFG9); + for (int i = 0; i < DP_AUX_CFG_SIZE; i++) + writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | @@ -519,16 +508,19 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = { }; static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { + .aux_cfg = edp_phy_aux_cfg_v4, .ver_ops = &qcom_edp_phy_ops_v4, }; static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = { + .aux_cfg = edp_phy_aux_cfg_v4, .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, .ver_ops = &qcom_edp_phy_ops_v4, }; static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = { .is_edp = true, + .aux_cfg = edp_phy_aux_cfg_v4, .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, .ver_ops = &qcom_edp_phy_ops_v4, }; @@ -707,6 +699,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = { }; static struct qcom_edp_phy_cfg x1e80100_phy_cfg = { + .aux_cfg = edp_phy_aux_cfg_v4, .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, .ver_ops = &qcom_edp_phy_ops_v6, }; From patchwork Fri Oct 4 10:30:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soutrik Mukhopadhyay X-Patchwork-Id: 832794 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24DA6156220; Fri, 4 Oct 2024 10:31:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037877; cv=none; b=C45zEx1MASNqVxxuFxcyG+OLv2DpbNNHdYQhrRWfCTrD+nLPAiCYhS7fPZWScDCTMgNtwSW6t9AmCFZZBvFHFISKYlcwf92Ogm7y7XC4D3kIuXWhed5lRqwktbmSH5DWGgILOUF82gh8hPnXJ3plbka0gcYEo075eYP70PpiO6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037877; c=relaxed/simple; bh=QwWbFbbdvqKYlpegD4ObfTwOC61utTi1EH50AXl5KR4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=OfeqsFdEP9P7puQGaPu8aZjsrP/FMpm8+TlBhxayXZ959iAJ7NCcpB6KA70C62nLaYbPYa5V/b/+X9zTI/lTSkr+KAjZKHqWfW+KgXc3utBRSWaHBF5fRxfwlXCmerMJuH9J+tsQYEFhTqtGfoD9ApAJX2nod6WnhT2WByhMSuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=dHd+eTMV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="dHd+eTMV" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4949tiFJ026659; Fri, 4 Oct 2024 10:30:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=wofS2V5cOCn0YNSaz5NkaQtDc4eF8kvAYiZTvMfZpt4=; b=dH d+eTMVD9NIYi23AwhIXMPeBXmSdNY1u3keWQhbuX1TrDj+wOl+I/HBIHcVGETAkJ 2ZgZzIw5mIpFzwTp/ZtlWDBuxhmbOr0kgYuwYMwwaOZryi5A779wdE3dbCcKa4qn 7FJ8uB9Br/McXsE2my2gtVY4Gvch0Ehfb0qOstVkar8tghFVNzloBsTBcwAU5fMg VIAHUluLg6ZUpd2SyJAvkBuVfp3R7OKfNotVg7ufPDSB1WVRVYhZlUcehwidYRrP bqWsGNK3HXfTxkq/4gg3rLtC3r9ipiohMDd7UWzK9fGWYpJy5bNC2oq4I1nAufXB V/Y7fioRlajLQwa6vTVg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42207v1saa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:30:55 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 494AUoPo005782; Fri, 4 Oct 2024 10:30:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 41xavmrk0h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 04 Oct 2024 10:30:50 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 494AUbuN005260; Fri, 4 Oct 2024 10:30:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 494AUnWB005742; Fri, 04 Oct 2024 10:30:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id C5EBF5000B1; Fri, 4 Oct 2024 16:00:48 +0530 (+0530) From: Soutrik Mukhopadhyay To: vkoul@kernel.org, kishon@kernel.org, konradybcio@kernel.org, andersson@kernel.org, simona@ffwll.ch, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_khsieh@quicinc.com, konrad.dybcio@linaro.org, quic_parellan@quicinc.com, quic_bjorande@quicinc.com Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH v4 3/5] phy: qcom: edp: Add support for eDP PHY on SA8775P Date: Fri, 4 Oct 2024 16:00:44 +0530 Message-Id: <20241004103046.22209-4-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241004103046.22209-1-quic_mukhopad@quicinc.com> References: <20241004103046.22209-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Frg0cQoRh5vVCzpewOjk9Yb5YKLgAv50 X-Proofpoint-ORIG-GUID: Frg0cQoRh5vVCzpewOjk9Yb5YKLgAv50 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 bulkscore=0 spamscore=0 adultscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040076 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add support for eDP PHY v5 found on the Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay --- v2: Fixed review comments from Dmitry - Reused edp_swing_hbr_rbr and edp_swing_hbr2_hbr3 for v5. v3: No change v4: No change --- drivers/phy/qualcomm/phy-qcom-edp.c | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 2ecff164ec44..f1b51018683d 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -183,6 +183,31 @@ static const u8 edp_phy_aux_cfg_v4[10] = { 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 }; +static const u8 edp_pre_emp_hbr_rbr_v5[4][4] = { + { 0x05, 0x11, 0x17, 0x1d }, + { 0x05, 0x11, 0x18, 0xff }, + { 0x06, 0x11, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] = { + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x0b, 0x15, 0x19, 0xff }, + { 0x0e, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v5 = { + .swing_hbr_rbr = &edp_swing_hbr_rbr, + .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr_v5, + .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v5, +}; + +static const u8 edp_phy_aux_cfg_v5[10] = { + 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp = phy_get_drvdata(phy); @@ -507,6 +532,13 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = { .com_configure_ssc = qcom_edp_com_configure_ssc_v4, }; +static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = { + .is_edp = false, + .aux_cfg = edp_phy_aux_cfg_v5, + .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5, + .ver_ops = &qcom_edp_phy_ops_v4, +}; + static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { .aux_cfg = edp_phy_aux_cfg_v4, .ver_ops = &qcom_edp_phy_ops_v4, @@ -1101,6 +1133,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) } static const struct of_device_id qcom_edp_phy_match_table[] = { + { .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, }, { .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, }, { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, }, { .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, }, From patchwork Fri Oct 4 10:30:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soutrik Mukhopadhyay X-Patchwork-Id: 833055 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BF341487E9; Fri, 4 Oct 2024 10:31:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037887; cv=none; b=hRys28e8MSzEBBJsVSsjUojZVHam1MQMcui9QhEOIbHuOKrCooE3MmtrovRzq1M2RKpHNosIZtLRb8coHm9koxqGOWicsE1na5yFTqY6//A3VHwJfotS9tbyH2msWmajWvNY90Vsm40RTmCSizv5TTAoMZDRdLHpYfebt84YfRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037887; c=relaxed/simple; bh=yF7TxTc8WA36RjcbE/O/0jEfH+jtc44O1NbnULm3NeE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=EKTrHUq76QZPEN8pAkUUqSTjbJY1f4YH/j1eY6Ye6Z7gF0H7GizYHymytGNsim4ASEmqqJVKwJy9Yp51gg6g2aqEbiqB5oXAvQZyQQAw8/xKh1xyrMQJkQsPuRA7K68fLa9ti4XlUBulUyxjY1oAqWN5loDnYxIow+LUZsyY5NI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=XDQIdBFA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XDQIdBFA" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493HxsIn022093; Fri, 4 Oct 2024 10:30:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=frdevttfGOk++bD+iRMgNWzOnpxV00mq2CYnqusj+64=; b=XD QIdBFAnWO+INErin35WK35XYAWvC5oOQOjtxlIK8t0sTkeuBYYAfGePq7gOEv2eW HdtdYQS7mM9wZFOaGpfEdRcOMPqjGR3tgmilYFufYIQ7YwjzB92IAGqPs0QnUr8R gBRFY4AG278QnukDi+j+4L4CBmpW6g3V6iaZ5zO/6J/3HncG9zSEVej1qh6Zpfrh BkHUGi8jKGlBm2gXL9EHUaO6ZYxvDqEK5t9YabVnaDYqJgXX6EVZHuVQHJG0mZKN bpQwVFmiDXmfb7QEUZS1l+DeMgBo8QTbeVFWQInNk0CPCvUenHd7WoH+dk472qI6 wdWIwpXbLCtl4UTdBC0A== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42205kssxm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:30:54 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 494AUohE005778; Fri, 4 Oct 2024 10:30:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 41xavmrk0d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 04 Oct 2024 10:30:50 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 494AUn9S005748; Fri, 4 Oct 2024 10:30:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 494AUn87005746; Fri, 04 Oct 2024 10:30:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id CA10C5001BA; Fri, 4 Oct 2024 16:00:48 +0530 (+0530) From: Soutrik Mukhopadhyay To: vkoul@kernel.org, kishon@kernel.org, konradybcio@kernel.org, andersson@kernel.org, simona@ffwll.ch, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_khsieh@quicinc.com, konrad.dybcio@linaro.org, quic_parellan@quicinc.com, quic_bjorande@quicinc.com Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH v4 4/5] dt-bindings: display: msm: dp-controller: document SA8775P compatible Date: Fri, 4 Oct 2024 16:00:45 +0530 Message-Id: <20241004103046.22209-5-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241004103046.22209-1-quic_mukhopad@quicinc.com> References: <20241004103046.22209-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: M_yfykuptOgQG_nVY9V7J7Ab_B3x40Wn X-Proofpoint-ORIG-GUID: M_yfykuptOgQG_nVY9V7J7Ab_B3x40Wn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 clxscore=1011 lowpriorityscore=0 bulkscore=0 mlxscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040075 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add compatible string for the DisplayPort controller found on the Qualcomm SA8775P platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Soutrik Mukhopadhyay --- v2: No change v3: No change v4: No change --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 97993feda193..a212f335d5ff 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,sa8775p-dp - qcom,sc7180-dp - qcom,sc7280-dp - qcom,sc7280-edp From patchwork Fri Oct 4 10:30:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soutrik Mukhopadhyay X-Patchwork-Id: 833054 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0912415CD79; Fri, 4 Oct 2024 10:31:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037893; cv=none; b=mUlL+2Gpst9CkiAelm+4lrNkFqPx+HsSj1mbgQz9cTTqTMDiyIDahdPtjtE0tTgDUrZtfZwdWyiWMpI+wjw1LgOg5/E/WoFibF7YNFyYze1d+z8MoS3735516oOjBKGhWlzKIK7Eb+4q/CQPwRagSYcniAaVpnQEGDqbhl+Sbps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037893; c=relaxed/simple; bh=qh1dJmz9Niyfu2oHwfupkB8xyeHzIoyc1Tg7CLZqXg8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=KBYAEDUfv6zvT/IOi+0GcQbHOL347JLbzODb33q7oPySJrRGy4+jk2i9JikOAwCzrjvDP4vEPPXp6vPDtp5kk97Yf12lN4vYWv8BVeI+nU5/mkxseexsA2ZZRmDWFT9ApZgktiUE0e+WKYh3OfbKNMiAtS6Q2huDBmU+IUO8XOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Bvfvx73r; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Bvfvx73r" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493I04U2019310; Fri, 4 Oct 2024 10:30:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=ZrRGGH8wPdT3FVfI0KiGv6u4QRqtiYJOLJYc2CPf60I=; b=Bv fvx73rtYCvPVN5woRaSaS3NLylv9Dzagg5LkFGGS4qI0tE5TUIx7Evma7NFc3PPS M5ZUrub6YWkFqroLvzLq68D9B14HiXSP1pOE5rdDGLIRotmv940kd8PPOaTrCBiq oH6dyetVSJcMnWhmUF1gijUHKjX0PiUyk/H9r67R6owUz6faxQkIGX8ZBPOVumlQ Hf4dx2n+dSXpJpyxzXrGgEnq4/e1OMtjY3AbNXl/PLjHEm98QJ99pQ+OpXag4JN8 ClcPxp+yQbG12K3oL2YD503RrxFdI3EYdCF0lWjHNUKCbXyfSDmQI3qFTM3I5d3f m6LaNuGHVdqANqnUqShw== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42205n1t0p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:30:55 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 494AUoPp005782; Fri, 4 Oct 2024 10:30:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 41xavmrk0y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 04 Oct 2024 10:30:51 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 494AUbuP005260; Fri, 4 Oct 2024 10:30:51 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 494AUo4i005788; Fri, 04 Oct 2024 10:30:50 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id CE2FE5009EF; Fri, 4 Oct 2024 16:00:48 +0530 (+0530) From: Soutrik Mukhopadhyay To: vkoul@kernel.org, kishon@kernel.org, konradybcio@kernel.org, andersson@kernel.org, simona@ffwll.ch, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_khsieh@quicinc.com, konrad.dybcio@linaro.org, quic_parellan@quicinc.com, quic_bjorande@quicinc.com Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH v4 5/5] drm/msm/dp: Add DisplayPort controller for SA8775P Date: Fri, 4 Oct 2024 16:00:46 +0530 Message-Id: <20241004103046.22209-6-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241004103046.22209-1-quic_mukhopad@quicinc.com> References: <20241004103046.22209-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0U8tKL-V8NF6DtQG7pdjq1yc3iy9PwvH X-Proofpoint-GUID: 0U8tKL-V8NF6DtQG7pdjq1yc3iy9PwvH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040076 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Qualcomm SA8775P platform comes with 2 DisplayPort controllers for each mdss, having different base offsets than the previous SoCs. The support for all 4 DPTX have been added here, and validation of only MDSS0 DPTX0 and DPTX1 have been conducted. Reviewed-by: Dmitry Baryshkov Signed-off-by: Soutrik Mukhopadhyay --- v2: No change v3: Fixed review comments from Konrad and Bjorn -Added all the necessary DPTX controllers for this platform. v4: Updated commit message --- drivers/gpu/drm/msm/dp/dp_display.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index e1228fb093ee..2195779584dc 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -118,6 +118,14 @@ struct msm_dp_desc { bool wide_bus_supported; }; +static const struct msm_dp_desc sa8775p_dp_descs[] = { + { .io_start = 0xaf54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, + { .io_start = 0xaf5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, + { .io_start = 0x22154000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true }, + { .io_start = 0x2215c000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true }, + {} +}; + static const struct msm_dp_desc sc7180_dp_descs[] = { { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, {} @@ -162,6 +170,7 @@ static const struct msm_dp_desc x1e80100_dp_descs[] = { }; static const struct of_device_id dp_dt_match[] = { + { .compatible = "qcom,sa8775p-dp", .data = &sa8775p_dp_descs }, { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_descs }, { .compatible = "qcom,sc7280-dp", .data = &sc7280_dp_descs }, { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_descs },