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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Document the SDHCI Controller on the X1E80100 Platform. Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 11979b026d211050270d018c03fa73c107e7c10f..8c7e016306f14be20e4a3cff289317ed603633f3 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -62,6 +62,7 @@ properties: - qcom,sm8450-sdhci - qcom,sm8550-sdhci - qcom,sm8650-sdhci + - qcom,x1e80100-sdhci - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 reg: From patchwork Tue Oct 8 14:05:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 833793 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E060F1DFD80 for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Describe the two SHDC v5 controllers found on x1e80100 platform. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 108 +++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a36076e3c56b5b8815eb41ec55e2e1e5bd878201..b835fd87b977ae81f687c4ea15f6f2f89e02e9b1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3880,6 +3880,114 @@ lpass_lpicx_noc: interconnect@7430000 { #interconnect-cells = <2>; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x520 0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + sdhc_4: mmc@8844000 { + compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08844000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC4_AHB_CLK>, + <&gcc GCC_SDCC4_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x160 0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc4_opp_table>; + + interconnects = <&aggre2_noc MASTER_SDCC_4 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_4 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + status = "disabled"; + + sdhc4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; 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Tue, 08 Oct 2024 07:06:25 -0700 (PDT) From: Abel Vesa Date: Tue, 08 Oct 2024 17:05:57 +0300 Subject: [PATCH 3/4] arm64: dts: qcom: x1e80100: Describe TLMM pins for SDC2 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241008-x1e80100-qcp-sdhc-v1-3-dfef4c92ae31@linaro.org> References: <20241008-x1e80100-qcp-sdhc-v1-0-dfef4c92ae31@linaro.org> In-Reply-To: <20241008-x1e80100-qcp-sdhc-v1-0-dfef4c92ae31@linaro.org> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Johan Hovold , Dmitry Baryshkov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=1463; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=jbN6Xob5YJFb0MxA9IvVkAB2WqTY7IjHlPTtNsNyFV0=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnBTxYQTKHwucGS/OGdimtbGnaPUMArcmMQ7JX8 rcqbhODueWJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZwU8WAAKCRAbX0TJAJUV Vg8lEACPG35Z6Zn05gn/sIL8J0/b4S8uZWJy4WKvZ5by0ZPSwE6ODc49CczU6elO/z0lx7JQea9 p8z4uUKz3GdFN3JWGphlKd2OoRp+cv9jW35gp71zZGN91ZHHdVPWWYK7YBjm6hRRxL9f2NJfJMG I2209FL/LMW1XI/WZiJyJggbLkySLWK3XLwHCdl6iecIO+w4sPsUK3RdZ3isAUWwOx/tlxy3vIc SCSF9Q5h216Q0NCNf8rwvOhQ9m6CWASPsxwF/ebC57786WzeUx4JrHKMme2Mw/4grm9o84rlYCr Zpk+PWfniEtkDYJBrKEyniTRCpS4mzFVpy4+4bJvhjzjju1XfIMLTE+ycD182fSs/j3Zgilr4XU 1t2ryHVynColYGBRx+JVM5JcZwFSN7oOlNq5ObUmUyI3+XdjrX6H+33xwv4S5j8MeGtyFUN6eLT FnmiGSZmqtDQqMKaV3KaEvmPGzBxY5qbo966fAUhoJH+zQQlOHr3YFlZGFWf2lQol7y0+N/QfwP u+awWSiSuoLG5dgJzMpzJlPqQczf4OIQkpIjWt3O9Cf4GJBmDUzqR20njeKRb6C9+K64Lim29NU 0jT3uTlz30KW0Zv7NWbngBHLukHpxFnJL0C0lEkazYt+I4eoCk1Y8rMyP5wmNgsr9aw7tXhp8qC BIZ/Sj+Ko5+R7/Q== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Describe the SDC2 default and sleep state pins configuration in TLMM. Do this in SoC dtsi file since they will be shared across multiple boards. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index b835fd87b977ae81f687c4ea15f6f2f89e02e9b1..f9f5da60244cdda7499883dd593b809c4274510a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5740,6 +5740,46 @@ rx-pins { bias-disable; }; }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; }; apps_smmu: iommu@15000000 { From patchwork Tue Oct 8 14:05:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 833792 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6ADF1DFE1D for ; Tue, 8 Oct 2024 14:06:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728396390; cv=none; b=MXdreSioEF/NskVp9CfMTdbnjoHWanYhOhf8mEYw2SKKz4s17SR80goGSqcQfiENUNn3DXWB8e8UH3nuMsaee3+6i4WLXeA63lUTYjsYC1kPqCCvEhpgwQaKIWyp++h03O1IIyHKui1vhL7m9L/ypnX+MVtmoLVl3D2dugdVuLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728396390; c=relaxed/simple; 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Tue, 08 Oct 2024 07:06:26 -0700 (PDT) From: Abel Vesa Date: Tue, 08 Oct 2024 17:05:58 +0300 Subject: [PATCH 4/4] arm64: dts: qcom: x1e80100-qcp: Enable SD card support Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241008-x1e80100-qcp-sdhc-v1-4-dfef4c92ae31@linaro.org> References: <20241008-x1e80100-qcp-sdhc-v1-0-dfef4c92ae31@linaro.org> In-Reply-To: <20241008-x1e80100-qcp-sdhc-v1-0-dfef4c92ae31@linaro.org> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Johan Hovold , Dmitry Baryshkov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=1388; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=HnTSSieNZnln6w8Vcr1MEzPJufKQo6Dj8CE0MlH5veg=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBnBTxZ5pw5/X59abM1PzRowDFyBM4dfWvQvCZKC 68ku9qUTSiJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZwU8WQAKCRAbX0TJAJUV VsDpD/47F+PiwUrg4V1wuq9sTBq0KrtQ4LmgaCq02mRN7AU7b/+bCIEpW9nYZw7XIs0WhZZp3xP DdVQeHV5HUcPZr4CA0ZghAO1InQYeiwD6sciR0tuN02VYftouZx+Eu9LD2zamJslkzZiaFcbCQ5 gXzgh4S0lyOXM/d6Rsdn3H27D+z5BVRgBXCBEUzRGxFxPCJnCMjCyjl3KTqPBwTBxi5EHGgue2n MHo1wohwNVZ8K6Y5gEha9m6c0RZub5OMgVls5z3I4UQY7DSHcAc3kOHP2bgiTfDBHJK/CMqevP1 oW3emd8H3KMhEqW9HwgW4bzTkiIUgIkSw0CS/os5GK6bEv8A3jRS50wizmaKSij/DJmqnkxTJwy yauuZs0Sd2HxFITFWNv5IxPL9blpOhtgQaZviOcFmBn3KGY0mbnIn6cuaXbACC8H2b74lQXQRAD Xm30RKgAFAZRx5WVPFozoMsZx6JFiCNgHl/X83uU1UlxOobqgrf6HVpf+l6P+PTIX0M2mBREkZ/ aMHzq8jxS+d/PYnOzU1wDj9CQ0IJ2NXlFMMp1byiG7ccklfWVJG0WU5SLHjorLK76IjtktFfL1T U+k6IBktWgDNVdBDhRSgRTn5aq1VgDSZhkvu9UsjadAF0FX3xnFO//J5dx3px54cc8vrrjV+iDO +mI/ECC0kKtrJeA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE One of the SD card slots found on the X Elite QCP board is controlled by the SDC2. Enable it and describe the board specific resources. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 1c3a6a7b3ed628e9e05002cf4b4505d9f4fb1a63..a82fabaaac9010ce3b8d6718b3425e84d8864171 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -729,6 +729,19 @@ &remoteproc_cdsp { status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + &smb2360_0_eusb2_repeater { vdd18-supply = <&vreg_l3d_1p8>; vdd3-supply = <&vreg_l2b_3p0>; @@ -870,6 +883,13 @@ wake-n-pins { }; }; + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio191"; function = "gpio";