From patchwork Thu Oct 17 11:39:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 836362 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5911DA619; Thu, 17 Oct 2024 11:39:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729165197; cv=none; b=MelSkDGZRovLux43Pu0ntpMw/t0VjcVq1t/nHf+9vuafI77LaDICuj8PQkH66L01Xh3hJ5izc3EL9MAJPfWOTLN/yCFQAKTvLN2rzbRvsBvTFqicETheJIVviA/TB/JQsRvWjM7X5yUXFAr9QFqQOOvX4+0Eq9iLiRgFaMQLPAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729165197; c=relaxed/simple; bh=OrcepXx4xODgS8EEORLedQ7ezdiPNjZqltCvPaIPAps=; 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AJvYcCUNjJ/Z3KgStdjkUHEFPW1k9GRs1hfezeBn+YN0dH1IPn8fSRKsvZbUDC10B7p2/zrHY/ClJ+lBaDOA@vger.kernel.org, AJvYcCX1ibyG06owa0b97/NvZb2A6EpjBQFXzugHaANVpmHA3CeGPLXJhQzkxTARqopTF2fD+iw3NjnkQgLHTA==@vger.kernel.org, AJvYcCXkHBCYYJFan7om0JjVpeQWL7pjRDPVadTqqHOAICCit/x/eiIP/zFOk762Nq7JtA40yMti5ymhQzOiCWxCXNL1Fkg=@vger.kernel.org X-Gm-Message-State: AOJu0Yzni1VCELoMdF/ldZvPPlm3eOzWd6ghq1gtj0hDpQZH5KKp5GBq gB2uYWXPKV/CTaSoQyQHMeJH5RPAAE6mbjqewaDPN5K/G4imA3F6 X-Google-Smtp-Source: AGHT+IGQzALL8gJ0LUU0w64wb3YMwN9fdRLEJntNWKAwYoYNkK/HAMUuoJ0RjlIdqF68Aq1q/+LxDQ== X-Received: by 2002:a05:600c:3ba9:b0:42c:b52b:4335 with SMTP id 5b1f17b1804b1-4311decaa31mr191141305e9.10.1729165192389; Thu, 17 Oct 2024 04:39:52 -0700 (PDT) Received: from prasmi.Home ([2a02:c7c:e309:f400:f6f5:4306:392d:908d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d7fbf82b1sm7060399f8f.72.2024.10.17.04.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 04:39:51 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Linus Walleij , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/7] pinctrl: renesas: rzg2l: Release all the virq's in free callback Date: Thu, 17 Oct 2024 12:39:38 +0100 Message-ID: <20241017113942.139712-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The `free` callback in `struct irq_domain_ops` expects to free nr_irqs interrupts starting from virq. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 39 ++++++++++++++----------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 8ffb9430a134..1a09ccbfebad 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2477,25 +2477,30 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { + struct rzg2l_pinctrl *pctrl; + irq_hw_number_t hwirq; + struct gpio_chip *gc; + unsigned long flags; struct irq_data *d; + unsigned int i, j; - d = irq_domain_get_irq_data(domain, virq); - if (d) { - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); - irq_hw_number_t hwirq = irqd_to_hwirq(d); - unsigned long flags; - unsigned int i; - - for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { - if (pctrl->hwirq[i] == hwirq) { - rzg2l_gpio_irq_endisable(pctrl, hwirq, false); - rzg2l_gpio_free(gc, hwirq); - spin_lock_irqsave(&pctrl->bitmap_lock, flags); - bitmap_release_region(pctrl->tint_slot, i, get_order(1)); - spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); - pctrl->hwirq[i] = 0; - break; + for (j = 0; j < nr_irqs; j++) { + d = irq_domain_get_irq_data(domain, virq + j); + if (d) { + gc = irq_data_get_irq_chip_data(d); + pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + hwirq = irqd_to_hwirq(d); + + for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { + if (pctrl->hwirq[i] == hwirq) { + rzg2l_gpio_irq_endisable(pctrl, hwirq, false); + rzg2l_gpio_free(gc, hwirq); + spin_lock_irqsave(&pctrl->bitmap_lock, flags); + bitmap_release_region(pctrl->tint_slot, i, get_order(1)); + spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); + pctrl->hwirq[i] = 0; + break; + } } } } From patchwork Thu Oct 17 11:39:40 2024 Content-Type: text/plain; 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When GPIO pin is requested as interrupt through `gpios` DT property the gpio_request() is called through the code path and when releasing GPIO pin it goes through the gpio_free() path, so drop calling gpio_request() in rzg2l_gpio_child_to_parent_hwirq() path and also drop rzg2l_gpio_free() in rzg2l_gpio_irq_domain_free(). This fixes case where rzg2l_gpio_free() was being called twice after the GPIO interrupt pin is freed (after unbinding the module). When GPIO pin is requested as interrupt through `interrupt` DT property this doesn't go through gpio_request()/gpio_free() code path. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 33 +++---------------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index d8b942fbf537..b9a8bf43a92a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2372,26 +2372,6 @@ static const struct irq_chip rzg2l_gpio_irqchip = { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; -static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) -{ - struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - u64 *pin_data = pin_desc->drv_data; - u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); - u8 bit = RZG2L_PIN_ID_TO_PIN(offset); - u8 reg8; - int ret; - - reg8 = readb(pctrl->base + PMC(off)); - if (reg8 & BIT(bit)) { - ret = rzg2l_gpio_request(chip, offset); - if (ret) - return ret; - } - - return rzg2l_gpio_direction_input(chip, offset); -} - static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned int child, unsigned int child_type, @@ -2407,17 +2387,15 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, if (gpioint < 0) return gpioint; - ret = rzg2l_gpio_interrupt_input_mode(gc, child); + ret = rzg2l_gpio_direction_input(gc, child); if (ret) return ret; spin_lock_irqsave(&pctrl->bitmap_lock, flags); irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); - if (irq < 0) { - ret = -ENOSPC; - goto err; - } + if (irq < 0) + return -ENOSPC; rzg2l_gpio_irq_endisable(pctrl, child, true); pctrl->hwirq[irq] = child; @@ -2427,10 +2405,6 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, *parent_type = IRQ_TYPE_LEVEL_HIGH; *parent = RZG2L_PACK_HWIRQ(gpioint, irq); return 0; - -err: - rzg2l_gpio_free(gc, child); - return ret; } static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) @@ -2494,7 +2468,6 @@ static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { if (pctrl->hwirq[i] == hwirq) { rzg2l_gpio_irq_endisable(pctrl, hwirq, false); - rzg2l_gpio_free(gc, hwirq); spin_lock_irqsave(&pctrl->bitmap_lock, flags); bitmap_release_region(pctrl->tint_slot, i, get_order(1)); spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); From patchwork Thu Oct 17 11:39:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 836360 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D60971DD89A; Thu, 17 Oct 2024 11:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729165203; cv=none; b=OIiUnkJSi8udQ74yUtcNqKOL+JRKl0VQpq3VlogKAu6IEs854oHu5u3OSy7D8nrtoTvCuWgB8Rw2+PYlJrmz4owpRisJ/Cuee8wutMlPIWRhM/BSGRDWJOrVct2M1Ei7saTvzhmmE8n8uN4Dwkc3zbqxQOsBLYsz7tC5xBCOWwQ= ARC-Message-Signature: i=1; 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Thu, 17 Oct 2024 04:39:56 -0700 (PDT) Received: from prasmi.Home ([2a02:c7c:e309:f400:f6f5:4306:392d:908d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d7fbf82b1sm7060399f8f.72.2024.10.17.04.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 04:39:56 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Linus Walleij , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 7/7] pinctrl: renesas: pinctrl-rzg2l: Override irq_request/release_resources Date: Thu, 17 Oct 2024 12:39:42 +0100 Message-ID: <20241017113942.139712-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241017113942.139712-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Override the default `irq_request_resources` and `irq_release_resources` functions with `rzg2l_gpio_irq_request_resources` and `rzg2l_gpio_irq_release_resources` in the RZ/G2L pinctrl driver. The `rzg2l_gpio_irq_request_resources()` function now ensures that the pin is requested by the pinctrl core before locking the GPIO as an IRQ. This ensures that the `pinmux-pins` file in sysfs correctly reports the pin as claimed. Additionally, the `rzg2l_gpio_direction_input()` call is moved into the `rzg2l_gpio_irq_request_resources()` callback, as it makes sense to configure the GPIO pin as an input after it has been requested. The `rzg2l_gpio_irq_release_resources()` function unlocks the GPIO as an IRQ and then frees the GPIO, ensuring proper cleanup when the IRQ is no longer needed. This guarantees that the `pinmux-pins` file in sysfs correctly reports the pin as unclaimed. Also add a `pin_requested()` check in `rzg2l_gpio_free()` to return early if the pin is already released. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 41 +++++++++++++++++++++---- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b9a8bf43a92a..47b3e296d094 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1772,8 +1772,12 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) { + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); unsigned int virq; + if (!pin_requested(pctrl->pctl, offset)) + return; + virq = irq_find_mapping(chip->irq.domain, offset); if (virq) irq_dispose_mapping(virq); @@ -2357,6 +2361,35 @@ static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int rzg2l_gpio_irq_request_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + unsigned int child = irqd_to_hwirq(d); + int ret; + + if (!pin_requested(pctrl->pctl, child)) { + ret = rzg2l_gpio_request(gc, child); + if (ret) + return ret; + } + + ret = rzg2l_gpio_direction_input(gc, child); + if (ret) + return ret; + + return gpiochip_irq_reqres(d); +} + +static void rzg2l_gpio_irq_release_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int child = irqd_to_hwirq(d); + + gpiochip_irq_relres(d); + rzg2l_gpio_free(gc, child); +} + static const struct irq_chip rzg2l_gpio_irqchip = { .name = "rzg2l-gpio", .irq_disable = rzg2l_gpio_irq_disable, @@ -2368,8 +2401,9 @@ static const struct irq_chip rzg2l_gpio_irqchip = { .irq_print_chip = rzg2l_gpio_irq_print_chip, .irq_set_affinity = irq_chip_set_affinity_parent, .irq_set_wake = rzg2l_gpio_irq_set_wake, + .irq_request_resources = rzg2l_gpio_irq_request_resources, + .irq_release_resources = rzg2l_gpio_irq_release_resources, .flags = IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, @@ -2381,16 +2415,11 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; int gpioint, irq; - int ret; gpioint = rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; - ret = rzg2l_gpio_direction_input(gc, child); - if (ret) - return ret; - spin_lock_irqsave(&pctrl->bitmap_lock, flags); irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);