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Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v2 2/5] x86/cpufeatures: Add feature bits for AMD heterogeneous processor Date: Mon, 21 Oct 2024 22:46:05 -0500 Message-ID: <20241022034608.32396-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022034608.32396-1-mario.limonciello@amd.com> References: <20241022034608.32396-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B078:EE_|BL1PR12MB5732:EE_ X-MS-Office365-Filtering-Correlation-Id: 491395ec-7a2b-4449-0af6-08dcf24c2a76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|36860700013|7416014|1800799024; X-Microsoft-Antispam-Message-Info: DSCLDAO/rOTw+oEwLd2QjrvY/YLtL6yIKsZXIU9p/r72C98i2pyfLegZqKNzDNd3hhB/PJJSKW6mTEO6Wx0IZXr8XqqrZ/uJwdAh+2JHQyiQO2on1+z2npaWQsPtuPQGjS9AtpsNPHReU4obwl5vyKx6q070Z6+9SIF6C8ElCFxjBBza52n28YcZHRB7bHdI8KvajEn/3Yiso8k3Xi9luOzpAJegvUFr+T2LpFwG4ei7UYiHowU5I0hEO6KiQOOOCACCnux2TumThgkwC08v3x5QCx4WhDhE//tMxtO0WxpiqKkql9G0YHbjSdITwSXHyGUupZAJRfcuYmlnuSmXUq8kqaJm0GnDq8VrcNqBl7Z1NPqVnU+lsXdvqNvFj7FrHTGe1jdtbgB52LKNkOC/BMBEmWiAyw4CUTf6XvNrIwaCyo2sceu0On60GPYt5ERgoa0XRz6kaRhuy9te+68MXzZnfFGB6aL+ACOzHknoem9EbyKmnsrIlmuMvib8KD8+HUnh3UECTQVuVQIbUnw/XEt7dO9fFc5UOdU73eAv236emQCfKPzQ7OJ6/+cMEeqzkuEplGY7Tb1w8oEDlTaXd4tUp69ZFAKLccKiEQnjGQTikqRJ2G1hG5yXj4JZUex7ikts9X/DpojV6JefwrnYb76ktvNBY5Gey8JSR0ouvOblYdymTosjmG2IDPPA0/ZYHye8OwuaV7LAMvMnphxSgwWFSuLQ4J2TM+TSjwGA9oQU9P6bBy1KiSIi17VfIjxjINAV/slhcSfLGERRzJWeomuU2J8mPWIzoqlsiceHm47/Ta1pYCoy5Xe6irB0x6O6LX964G05Q9ap8kezdcOHKW8OWniasklzcUEPR2Kc3mlvwHzSpTyPboCWPSXKRR82o/Hb0ssU7KA3UaPIWGpBTz5oQDy6jBOd9WJlOSR/8pVcRVsFFThvcdzBQMNYwWEre53kjNBO1aNLQcZu7jadMHNLYhK93eDrc1UZk9wiIbRfYPH/l9prva307aig/WnhY3VjpSSB0U18kO7AW/K/mcgQjvXh5etOT6m3Z+Fb/cdBGBIA46ttPwIrX1fubk3KOllE4r2kn5DnxHeMZFGwGrEO9pEDU1+gLhyDCZdGZ3idPnkXrXCxREKT75R7ioQ4bxN1kK5RCyp2HBWkSUNDzxVj1/pQfxpAJHbCbDG7Fr6XIBqkL88KEI8Wgr7jINSX9L9e3IEV/qlttJxDEUAxmK0ZLSW78kpqd98n5Go7bE4iZS5CRDrHhljdgkWsaTZdVizG9o/FRl3qoL17Oq6/KbdNv007/REOcKmXRHh5c0ppAGBI6gTMQy1scXeRQ+OIGYtnpxS/JJ5dNhSGhKimXHvT1khwyLZ6+tqZYMhn5dc38Vl+ascQUPMdKIbiCW3OkCictAlqhVs1+P8R5IvV0w== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(7416014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 03:46:52.2958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 491395ec-7a2b-4449-0af6-08dcf24c2a76 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B078.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5732 From: Perry Yuan CPUID leaf 0x80000026 advertises core types with different efficiency rankings. Bit 30 indicates the heterogeneous core topology feature, if the bit set, it means not all instances at the current hierarchical level have the same core topology. This is described in the AMD64 Architecture Programmers Manual Volume 2 and 3, doc ID #25493 and #25494. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v1->v2: * Drop tags * Squash original attempt and new changes with feedback together --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index aa63437a677c0..51b38bc667960 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -474,6 +474,7 @@ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 1db2bb81a3847..307a917415343 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -52,6 +52,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, + { X86_FEATURE_AMD_HETEROGENEOUS_CORES, CPUID_EAX, 30, 0x80000026, 0 }, { 0, 0, 0, 0, 0 } }; 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Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v2 5/5] x86/amd: Use heterogeneous core topology for identifying boost numerator Date: Mon, 21 Oct 2024 22:46:08 -0500 Message-ID: <20241022034608.32396-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022034608.32396-1-mario.limonciello@amd.com> References: <20241022034608.32396-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|SA1PR12MB7365:EE_ X-MS-Office365-Filtering-Correlation-Id: 4da1fa2d-03b8-455c-f4e1-08dcf24c2c9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: fopKHDYmT5F8gFpeEHL2P3t3QQN9B0mZy4qh0FXlzdGz5yhSu71Dn1yqtYXucarhfFihSW8lB27JwJxviyoG9PZkA35WGU7q97nP3lPz639QBZ22w7kFThPK1FDKJs9zbp2KxoTDANb8rAzhqtFIS1lNDLoXp5mugHsBVQshQHIVJ1VeRtENVEY53AH9JKu28PW3KvPfFzDom7yHEvazmYTZbiBcFYV3bUf/NXdLgCkqEhkoPoFqf8SpIQKWp0vGnS7HgZyG/wxl0pm8W8sWs3VFoLSBtqXC/sj0zEIbF0l4rTBTgVrIFFs+MVC/xXAYOl6gYxIt0T36Q8k+lA3y2J2uleXs6/kj7CQUXl3bWLjIJhRbio0o/60sFTJYWBSW3gdAfGvDXnVmAVXWpA/psfCXjM22m3liGpl0iXLNgPoudOzvlC7i5QXYpVno8mkeKDU8z9hAZFv8dHm2/9A6G1rfmnPFdGwmJYHOrIMTSh3owmmOxRX2Ckr9jAcnulqjuHm+YewCsmr70uJd4MMkMK2njei8aT75mrRTXsADb6umJofPPS97arbf+YWRlQ0o6xx/v/4GwTyFrxn+oaoSod5H6lzFHFkQ2hjn+rc+wsDw8syiQ2i7Hi7ER6Qc4tWKitzGSSiLbg+gZfeNqxk3R+fNeTWTIGB08z1Eswgai4XFCYOqWrnQ2cRbb8GxuU2/uFwVVvqTZVGrRSu9k4r1d8Mku/WPRXVOjA8lmU5YnzwoKhS93FwSCNgyr+n5xgh0xoEaTbe5pdXTfwiiIfw7f7wc9+JzvxdHUk2CpxuJfR6GZlmMVOvQ31Dj7yMtG4PMfxUxV+jKyCEQVyop9/JluNL+9XlqvF7PC1WL4OwZV9j2+Nq4pLzSc9pjJjBzi9/WS+NkbM2MCcAjFh19+4w5YLKj7H68Zgj6lGLooQua1APuhL9Tj6gkVbziCj9wnJ5xvd4UiZEyuoY49SrxDSKKku99T/o+eAjsFKkjL4AJnv0O25+MwA+pAMHmFWG6T7R1mrXDy7DAkiPGQR4jBahMCMl4FO2kIL4J80NpBYBOruiCWdzo4O/oCEi+llgPkx8O4ye0JOXWueAUuyn+FaxdG+pr32p7SVctOvr1S+gmr0fpbIUiEaRxaKvVOllWNqDDe1UG6NsWzezlVQ9hr9HBW4QM1MWAMKDCqnbfQdwC5Cc+VGiDpgaUFNBnf9aMClYZGqdR7zJ051/a0jafFRCMyLLhPR6sjrkQQmslgqLYpoh7Web8AXdfdYJ4f+FKktgftIx/f8JbZP09347LuL13XMDqSZ1XsxZKBL+WCh/HOUJ1+wSbthyjwz2h4v7yREZq3ABu7S3c8YVltjiREE5fX2rDVpTtDxn825NgAd65XlPUz28i8WvFHmITrsLAV8FMPlLQpILEhiyLhIuRP4KVEQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 03:46:55.8906 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4da1fa2d-03b8-455c-f4e1-08dcf24c2c9c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7365 AMD heterogeneous designs include two types of cores: * Performance * Efficiency Each core type has different highest performance values configured by the platform. Drivers such as `amd_pstate` need to identify the type of core to correctly set an appropriate boost numerator to calculate the maximum frequency. X86_FEATURE_AMD_HETEROGENEOUS_CORES is used to identify whether the SoC supports heterogeneous core type by reading CPUID leaf Fn_0x80000026. On performance cores the scaling factor of 196 is used. On efficiency cores the scaling factor is the value reported as the highest perf. Efficiency cores have the same preferred core rankings. Suggested-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/kernel/acpi/cppc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 956984054bf30..4fd007eac0c71 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -234,8 +234,10 @@ EXPORT_SYMBOL_GPL(amd_detect_prefcore); */ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) { + enum x86_topology_cpu_type core_type = topology_cpu_type(&cpu_data(cpu)); bool prefcore; int ret; + u32 tmp; ret = amd_detect_prefcore(&prefcore); if (ret) @@ -261,6 +263,27 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) break; } } + + /* detect if running on heterogeneous design */ + switch (core_type) { + case TOPO_CPU_TYPE_UNKNOWN: + break; + case TOPO_CPU_TYPE_PERFORMANCE: + /* use the max scale for performance cores */ + *numerator = CPPC_HIGHEST_PERF_PERFORMANCE; + return 0; + case TOPO_CPU_TYPE_EFFICIENCY: + /* use the highest perf value for efficiency cores */ + ret = amd_get_highest_perf(cpu, &tmp); + if (ret) + return ret; + *numerator = tmp; + return 0; + default: + pr_warn("WARNING: Undefined core type %d found\n", core_type); + break; + } + *numerator = CPPC_HIGHEST_PERF_PREFCORE; return 0;