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Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v3 3/5] x86/cpu: Enable SD_ASYM_PACKING for PKG Domain on AMD Processors Date: Wed, 23 Oct 2024 12:43:55 -0500 Message-ID: <20241023174357.34338-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241023174357.34338-1-mario.limonciello@amd.com> References: <20241023174357.34338-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|CY8PR12MB7315:EE_ X-MS-Office365-Filtering-Correlation-Id: 02ddfe8b-cd4d-49b9-c4b3-08dcf38a605a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: NNtnSzRYVeTPP06gFQTOdTYdo3Gi6ePGbhVAMbFcmgbxqua0fqek5t1sIOmqltwAlS25913oUosfrh/8lp5k+mUOXKJbjQM6BKyVRNF5082QeqND1h0XaBEIWfYyBwJsVkxTUfpz00pd6dSiKCexGlM1OC7eCo+IfH90yjdlZ5o6gnqfM7D1axL00AQcf8fZtoSYhN8KUaPq3x6/pYDHwvqQYyY8NRy7Df/cVyEquwYX94h9r4BxpIkHWnYNqG8iAgmhBWL9za//pI5ewMWM/S/HUP9U7rbIaqHpkaFXPzSjMxQ+YZ3IM1Y+oW2JPQckX2xZMDQtkC6NKo8L7J/vG/0dMCGOgGC2JhJzr30gQFgQkovsE/m8bQCS3juyG+0keMQNz0gNJ8O+zW9rN7W/PmLMJdBlPOnv71F9MDBS/1jXvps/tswLwtcYjYrQD4dT0C+we2pwUdi41kI4rVyYv9OLj9j6I9vJ0Y1XXXns0emQRIjPtzb0jgFYtsanopMLzEWHEqyV1eiiS4r2JWrUZY5fTi3DNlaccyhEkgE7zARLbtU/Wm3hvvrnsVYyc6whxJWQlQN0N4z7hcCGJV5vSDrAv30LxnuMe+McytpPyxHX6clk7uuZkkSaVYKYqdZJYe3p5zJ6tM795jZciTFvgsTjzR1wi8h9CPMv+lqJei8xwlEu0PONVX+PtWZlZbld9WmqV6fm8YDOtsxdA8klZwgGEOBPi3Ix0YbQ87GhhaP2LxmQ9TDzJ7P4JvkC5RhHHrK8LkIBzfaCyR3SSEVsevSuRY3SO3++Ko2iMfSasD3upg+uFi9weF2FvtXXORG6lfWKk8A1E3onAK/3ZSbJOyG2qCYtUNqnzviQMEJaWMxfKmgK0XVEyPVj0MyzZ24nMn8m1oeu6m/lEKKS38DepedKQoPe+WyAdmhpyOqZtkAfafm4Nl2qOy+LfLS6mBudZQpspTrYG3OPz8nhviCTVqRy9fZ0eaVkOujoHzQEKq/sb/Z3WsEsOkXVkHks0nEpmJT87QU/2GM0A3gL3QLOr/yK1r7BSy7cPKKZthvM9ZxXRvOBCLp99DU1s0/xGNc3S7DFOcz787wSwNji1fZaZEgRrTd4jICUZjndqUrpznVURUzYULQA1jh03w5nxdD0KoCvhOK36pvZ7O5C23zzCFa9Fxgn5OoN1IPzlYDF9it5bHF32bULh27fmbTAr9uBnBWS1U+uTUnc/XzUTrBDLBcGsHUYX5Pc/KpCj3daDObJvfHt9V9bF4n4m0/nR6p9C4yqE+QCMUe4PlCChs8LJaUlgkgxB4B2XEPP8neeFW6ri57xX/o2P1bSlHJsWVw2HXToNcNtnMjOtietY383u1Hlaq8lS/gD5xKAeQzv5VGTbrr4YfzhPny4OuX9Vp8w6bOVYJ9/fYgM++NLUoCobA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 17:44:42.5646 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02ddfe8b-cd4d-49b9-c4b3-08dcf38a605a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7315 From: Perry Yuan Enable the SD_ASYM_PACKING domain flag for the PKG domain on AMD heterogeneous processors. This flag is beneficial for processors with one or more CCDs and relies on x86_sched_itmt_flags(). Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v3: * Pick up tag --- arch/x86/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 766f092dab80b..b5a8f0891135b 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -497,8 +497,9 @@ static int x86_cluster_flags(void) static int x86_die_flags(void) { - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return x86_sched_itmt_flags(); + if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) || + cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) + return x86_sched_itmt_flags(); return 0; } From patchwork Wed Oct 23 17:43:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 837836 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2086.outbound.protection.outlook.com [40.107.220.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5117F1C9DF0; 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Wed, 23 Oct 2024 12:44:40 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v3 4/5] x86/cpu: Add CPU type to struct cpuinfo_topology Date: Wed, 23 Oct 2024 12:43:56 -0500 Message-ID: <20241023174357.34338-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241023174357.34338-1-mario.limonciello@amd.com> References: <20241023174357.34338-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|SJ2PR12MB8181:EE_ X-MS-Office365-Filtering-Correlation-Id: 49bcdb5f-a964-47c2-8533-08dcf38a60bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: VCTEEN8OXFj+wubX+2AfM5o+1Vr0hsfRBnhska8h5TRaKhho9O6j/WttTQ3ClLV6Bl61+iM9en4zuFaFQxVvKTnoxw/FMPpRjGHxyrkjd6fVX9VP9rrRQj7PygLf/atasbgBddGD8/tEENVuuJRjdGFzvHg7uSFyDw0lP07bQrXZXD6/DCxXjU9gvyKPAb4ch+iY9AbVeWI5MQmZZylrsfKlM5DW7rWvOisg96dqynjeQusab43FejykngDh8KjMrlM6SMIXgLFkSO2wIYFwQZw4+YMeGktnj0XUwfqd4VC3H3XzBs+//MY27h/cp+rcSkAdYo6NZtSvC/OeCXyZV4TA5QDVYW2QrhihT5pO0Vc7B8N+r37NH51SLRW/pOc8lr7I2wNP8dyTD18dB5SzzlnOpMZOPaI/xOkG0jQ2Iep78FTcIoaiuxCPvf6VENbsS7Sh9Cl1L3QBeiclAWmdOOT0Q2I/w+MmCnE36hnmmJXLeA+vwXyvGSUgUW/yUJk4nL1IZz0Tm2cpn3ER50tEitcFJYsyY/M30wzW3f0Lq2qoQ1huxUx+pUmvesNUA7LRK9l51eF61/hf6Jkm4QDdz6Jq/y0gcMOJWJ64Z86oKstouVSNvSycE75GSJx5/KVZ6svmkUYzZWEToX+WMpf7CvEhrmBdtukjGWE2tmIW3SQeZAA4eYaSQrMOcqnw85pY+fojqV+5lMJD1IINJvnmJ3PDDSNBZ/+1JJ06axDdoDrysTV8qEkgnj1+7fRelzDh2zw/1vlZPUOpHRnh27tHE2DVSTl0kyR2qmTDEv4WU+v1DvO7Kqm2s80rsGFou6MC25JLnO36Ob/tkwZvgtVozoDVBvI9XtTyXC4Cs5wf5dE1xMojjdNBCPQWtU9KnnBgIX+fvvbJy6b6vGPYAcl35pKfK7sa261duWwHbskcGvsQd5lbTVz2/Vx5p+++NSaWpqG9EAPW3dgipfvyH5/YZasU4Vwvn3zMdv62VaurfqaMNGIl2xsOdn2Sgf++xAMqOmDvYYqc5D6aXbs770SBPiGlbpLsk7ONlvshhh6NaT7eY0IWvvctgI2dxvgnqAIbaoMi5WIn21fnduh2aYNgYvlPi/AVa2FLwTRaQ4ncQ5j00YDGkwEN6UdTYmNB2g4yHG3Vjv7v97IOtmxVH8NUxC4lNi6AIVkX74m75rbegQkrPs1ww22+40uo6CVzISq44G+TBmxSqzeMe+rJSFQx+atf4Yna6NsNsl1iuw4/+FIqN6lWM+TZcT+VbguUp6m/5qTqBGUPO6STY5Dei85QJJc/jsQKRlYVQCVLo04vm5WE3dvYtCtC0qOXQPDd+XuY5PlE5943GxaQRq8wm+OZVOTBaAe08npLgcyTa11Ejc5j6SHd9ZTc8RweHawZnY6qFFerIWifgTGFSkK4BZSg8g== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(7416014)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 17:44:43.2209 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49bcdb5f-a964-47c2-8533-08dcf38a60bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8181 From: Pawan Gupta Sometimes it is required to take actions based on if a CPU is a performance or efficiency core. As an example, intel_pstate driver uses the Intel core-type to determine CPU scaling. Also, some CPU vulnerabilities only affect a specific CPU type, like RFDS only affects Intel Atom. Hybrid systems that have variants P+E, P-only(Core) and E-only(Atom), it is not straightforward to identify which variant is affected by a type specific vulnerability. Such processors do have CPUID field that can uniquely identify them. Like, P+E, P-only and E-only enumerates CPUID.1A.CORE_TYPE identification, while P+E additionally enumerates CPUID.7.HYBRID. Based on this information, it is possible for boot CPU to identify if a system has mixed CPU types. Add a new field hw_cpu_type to struct cpuinfo_topology that stores the hardware specific CPU type. This saves the overhead of IPIs to get the CPU type of a different CPU. CPU type is populated early in the boot process, before vulnerabilities are enumerated. Signed-off-by: Pawan Gupta Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2->v3: * Remove a bunch of boilerplate code * Convert to showing string in debugfs * Rename to get_topology_generic_cpu_type/get_topology_cpu_type_name * Add Intel definitions to intel-family.h --- arch/x86/include/asm/intel-family.h | 6 +++++ arch/x86/include/asm/processor.h | 18 ++++++++++++++ arch/x86/include/asm/topology.h | 9 +++++++ arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_amd.c | 3 +++ arch/x86/kernel/cpu/topology_common.c | 34 +++++++++++++++++++++++++++ 6 files changed, 71 insertions(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 1a42f829667a3..7367644720484 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -183,4 +183,10 @@ /* Family 19 */ #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ +/* CPU core types */ +enum intel_cpu_type { + INTEL_CPU_TYPE_ATOM = 0x20, + INTEL_CPU_TYPE_CORE = 0x40, +}; + #endif /* _ASM_X86_INTEL_FAMILY_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4a686f0e5dbf6..c0975815980c8 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -105,6 +105,24 @@ struct cpuinfo_topology { // Cache level topology IDs u32 llc_id; u32 l2c_id; + + // Hardware defined CPU-type + union { + u32 cpu_type; + struct { + // CPUID.1A.EAX[23-0] + u32 intel_native_model_id :24; + // CPUID.1A.EAX[31-24] + u32 intel_type :8; + }; + struct { + // CPUID 0x80000026.EBX + u32 amd_num_processors :16, + amd_power_eff_ranking :8, + amd_native_model_id :4, + amd_type :4; + }; + }; }; struct cpuinfo_x86 { diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index aef70336d6247..795619ea13346 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -114,6 +114,12 @@ enum x86_topology_domains { TOPO_MAX_DOMAIN, }; +enum x86_topology_cpu_type { + TOPO_CPU_TYPE_PERFORMANCE, + TOPO_CPU_TYPE_EFFICIENCY, + TOPO_CPU_TYPE_UNKNOWN, +}; + struct x86_topology_system { unsigned int dom_shifts[TOPO_MAX_DOMAIN]; unsigned int dom_size[TOPO_MAX_DOMAIN]; @@ -149,6 +155,9 @@ extern unsigned int __max_threads_per_core; extern unsigned int __num_threads_per_package; extern unsigned int __num_cores_per_package; +const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c); +enum x86_topology_cpu_type get_topology_generic_cpu_type(struct cpuinfo_x86 *c); + static inline unsigned int topology_max_packages(void) { return __max_logical_packages; diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 3baf3e4358347..10719aba62768 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -22,6 +22,7 @@ static int cpu_debug_show(struct seq_file *m, void *p) seq_printf(m, "die_id: %u\n", c->topo.die_id); seq_printf(m, "cu_id: %u\n", c->topo.cu_id); seq_printf(m, "core_id: %u\n", c->topo.core_id); + seq_printf(m, "cpu_type: %s\n", get_topology_cpu_type_name(c)); seq_printf(m, "logical_pkg_id: %u\n", c->topo.logical_pkg_id); seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); seq_printf(m, "llc_id: %u\n", c->topo.llc_id); diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c index 7d476fa697ca5..03b3c9c3a45e2 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -182,6 +182,9 @@ static void parse_topology_amd(struct topo_scan *tscan) if (cpu_feature_enabled(X86_FEATURE_TOPOEXT)) has_topoext = cpu_parse_topology_ext(tscan); + if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) + tscan->c->topo.cpu_type = cpuid_ebx(0x80000026); + if (!has_topoext && !parse_8000_0008(tscan)) return; diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index 9a6069e7133c9..60d5d74189a30 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -3,6 +3,7 @@ #include +#include #include #include #include @@ -27,6 +28,36 @@ void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom, } } +enum x86_topology_cpu_type get_topology_generic_cpu_type(struct cpuinfo_x86 *c) +{ + if (c->x86_vendor == X86_VENDOR_INTEL) { + switch (c->topo.intel_type) { + case INTEL_CPU_TYPE_ATOM: return TOPO_CPU_TYPE_EFFICIENCY; + case INTEL_CPU_TYPE_CORE: return TOPO_CPU_TYPE_PERFORMANCE; + } + } + if (c->x86_vendor == X86_VENDOR_AMD) { + switch (c->topo.amd_type) { + case 0: return TOPO_CPU_TYPE_PERFORMANCE; + case 1: return TOPO_CPU_TYPE_EFFICIENCY; + } + } + + return TOPO_CPU_TYPE_UNKNOWN; +} + +const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c) +{ + switch (get_topology_generic_cpu_type(c)) { + case TOPO_CPU_TYPE_PERFORMANCE: + return "performance"; + case TOPO_CPU_TYPE_EFFICIENCY: + return "efficiency"; + default: + return "unknown"; + } +} + static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c) { struct { @@ -87,6 +118,7 @@ static void parse_topology(struct topo_scan *tscan, bool early) .cu_id = 0xff, .llc_id = BAD_APICID, .l2c_id = BAD_APICID, + .cpu_type = TOPO_CPU_TYPE_UNKNOWN, }; struct cpuinfo_x86 *c = tscan->c; struct { @@ -132,6 +164,8 @@ static void parse_topology(struct topo_scan *tscan, bool early) case X86_VENDOR_INTEL: if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) parse_legacy(tscan); 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Wed, 23 Oct 2024 17:44:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CE.mail.protection.outlook.com (10.167.241.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Wed, 23 Oct 2024 17:44:44 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 23 Oct 2024 12:44:41 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v3 5/5] x86/amd: Use heterogeneous core topology for identifying boost numerator Date: Wed, 23 Oct 2024 12:43:57 -0500 Message-ID: <20241023174357.34338-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241023174357.34338-1-mario.limonciello@amd.com> References: <20241023174357.34338-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|MN2PR12MB4222:EE_ X-MS-Office365-Filtering-Correlation-Id: 972544a5-42ab-4bd0-a555-08dcf38a615e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: MsIQymDLo3U7hjHcrAso1uy/yUQICFGqa3PPbJTTnmwAOjdpt5Hn0F/Q2CDU6gMStnSmZh9NEIHtrbGicMs6zNHzCOJgyrw0pLAZ+b50PauJqn59xgY4gX2PND7snfQih9dlKXxVisVTj75QrgHFSRB7Z76AWOnPn3T/JnrapLHZ9/htyVcQYKKy5hm8fcxsB0V0lxzXUxo2ofIXAysnOPV5t3H2wNzj2u/G7t1/yRotsHhCC64UjR6qqoKBwuk+e0S4WMjxpcCdcuk1ISqbDDscxKtfenMH7VI4BcY67hZ8xQu9YaI9mpMO2mohWh4RDWqbXVOblnrjF6JjPL8fAxFVjlW25gzuxCWOuD9koJXatLm174oKmztp1bmESRKHy2AdtzzQbePzpIcO79RCwP384x/RQdlMyllIAkPlTqaRejJGbZeBDZUBBgblI86lmxSfOjgZ6o5jSKW/MQ/qy5pPQqfLJA1Z1cxhcqc8YPk+NHIvnQtXg4pHHfyfi8dQsOLFuUtwmRMpaKGO/KQPExQDmySq1ov0eQ6cjBuMNFxeUqsSgO0CUcVe2TrXjMUKOlDRmD6rAXuZ6hof/ILCG25Omk6nt3rA7v2iG60aLyvT/Cjr6pVt27IWm3JElC+dK92/49tFb/4Vc83M1OthoH0JpDFVAL7ZLMi6/0inUDadA6fX0Vgx34W+o/qC/5D6aXPEHMlKe+fCBpFzj7IyVHMO6gqczCzz/2AH/85erIvSXsNQqg8jGPyknHyreLIQZpJ7rNkV83rtxPQtHf7dNGxBCHsO5wn7Y712S8UNud8a3/2gkG5Kr0KBpS8Q9hhGwg7vAOK9ot8kdk51mAEHfuYZ8HZXYmpdNcNnKqhpaKtXCEAs7s6IJvmHYd2uf5q6wQCOk2+fGKizXSDhHURPYMyqI0GErbQNMPlSXSqs2Ne8mwuBLRYlwQXF0wNwZcAAcWn/M2iQU+KXgC6sThrbtrrGiIKI9rYmGPC4y46Hov3zRtMxS/PsXoGZ/rNzwO2T2IVw4X09KaLu365qDBb6MUKW/XPBbB7bDuEge6yopJveQu6sEGa3VDTLQo60kZ/6FIVwKEN9EubQB+jnkDKYIpaJ9rR51d2sVE3zdADAp5Kv6ugovuLB86/BfHZPk4qoMEw5k/z/EPCvxNcE/wfJMBDzJewRR1m14Q6EEeI7tQSoNOPFf4QBeLMUqfD8i5evgsb6+GiWzKFNEmiskm5nYHGLK+zuvHqDuDlmx8gRmUFT4eDt7VctWKCMI2OBSPAXzp3usypw2gtMOW75WeaZMiRzxpst3IimvQ1M159vPZOTByQByD3JtwsUPCx8ZXXpdRN+OJVwxIzqVxE2uEzA1Z+NuvJ1bDHwbfRwLrv57qjNpoomDDTmVhSJ0W86o7/wK2lKGQGEOuCj+M/hC8DXzw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 17:44:44.2678 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 972544a5-42ab-4bd0-a555-08dcf38a615e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4222 AMD heterogeneous designs include two types of cores: * Performance * Efficiency Each core type has different highest performance values configured by the platform. Drivers such as `amd_pstate` need to identify the type of core to correctly set an appropriate boost numerator to calculate the maximum frequency. X86_FEATURE_AMD_HETEROGENEOUS_CORES is used to identify whether the SoC supports heterogeneous core type by reading CPUID leaf Fn_0x80000026. On performance cores the scaling factor of 196 is used. On efficiency cores the scaling factor is the value reported as the highest perf. Efficiency cores have the same preferred core rankings. Suggested-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/kernel/acpi/cppc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 956984054bf30..9983d4537968f 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -234,8 +234,10 @@ EXPORT_SYMBOL_GPL(amd_detect_prefcore); */ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) { + enum x86_topology_cpu_type core_type = get_topology_generic_cpu_type(&cpu_data(cpu)); bool prefcore; int ret; + u32 tmp; ret = amd_detect_prefcore(&prefcore); if (ret) @@ -261,6 +263,27 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) break; } } + + /* detect if running on heterogeneous design */ + switch (core_type) { + case TOPO_CPU_TYPE_UNKNOWN: + break; + case TOPO_CPU_TYPE_PERFORMANCE: + /* use the max scale for performance cores */ + *numerator = CPPC_HIGHEST_PERF_PERFORMANCE; + return 0; + case TOPO_CPU_TYPE_EFFICIENCY: + /* use the highest perf value for efficiency cores */ + ret = amd_get_highest_perf(cpu, &tmp); + if (ret) + return ret; + *numerator = tmp; + return 0; + default: + pr_warn("WARNING: Undefined core type %d found\n", core_type); + break; + } + *numerator = CPPC_HIGHEST_PERF_PREFCORE; return 0;