From patchwork Thu Oct 24 13:31:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 838147 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAC321EF928; Thu, 24 Oct 2024 13:31:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729776715; cv=none; b=BPPd4FSRa76m4d0TR9QYubKN02RVxgtFkYP4C39zd0KfUFkc4S0d2ih6GxzxUlWerRofo1ifpZQxrZ56z8OYm2e+P3dXwlHE4M9WxflNpQnNZd3BchgjM3DAoCjJN5HrHctCK6uHrO2r8Jac+cf2vCHQCkjEjrGU9EAkXSwhaUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729776715; c=relaxed/simple; bh=lxL4+ShEeB0aAqtdAu7aM+/JImXr3PIFw2XFqyYr3s4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=k/RY6u7P6OnqPShJENVaUGtQsLO5Nt10o/WTjlPYBrWXo9c6UepRZbVQ35DFnTGouX306gvMQRN9tGSyK7Nt20bGvLrKwGopbh5pUVNkc4jDIV1E1zes1500vDL9IqROvugf4LkXZAoWShv/SJZLyU7s6CK6wG8H3du+i/x08x0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=eHenJET5; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="eHenJET5" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49OA3U8U027440; Thu, 24 Oct 2024 13:31:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= arXgYvBxFyTJWJevkLx19Bhn50Kerp9xnES/ZxAxfqY=; b=eHenJET5ak3UmlWd dq+hPbwiWUpbE51qaq2PUwAI/j+fnmlW29ISaSapQXM7xuGs+P90qEEs3TFS1k9r +HEVv1mMa00/KyoJlW4iKgColVNI1OdfNShH/IfTSepDs92th74aTCNWQeH2s/Jz VXY+yh/uKcBr7QzMmq8jQfi40ghm6wmYpfmVZd2Os0ZzXXw9HbSK4gSt47ODU8cR UMhjvIdybzr+sicdBajjK6nXkh8Qvvu1ggIZHzZo287OXqkPp1WAP03vT7L6LkRu 2njgMGcxKTSWP9g+EA1ds0QCTOAI12y0AgVgjqlvmk1RVAsFzt0EdsAA0H1ejnIs nPWCEw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em41wr1b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 13:31:48 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49ODVlq2023974 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 13:31:47 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 06:31:42 -0700 From: Imran Shaik Date: Thu, 24 Oct 2024 19:01:15 +0530 Subject: [PATCH v2 2/6] clk: qcom: Add support for GPU Clock Controller on QCS8300 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241024-qcs8300-mm-patches-v2-2-76c905060d0a@quicinc.com> References: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> In-Reply-To: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik , Dmitry Baryshkov X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1Z0tubpg6QuJstPsm_m-C2Hy-v0nnzpy X-Proofpoint-ORIG-GUID: 1Z0tubpg6QuJstPsm_m-C2Hy-v0nnzpy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410240110 Add support to the QCS8300 GPU clock controller by extending the SA8775P GPU clock controller, which is mostly identical but QCS8300 has few additional clocks and minor differences. Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/gpucc-sa8775p.c | 47 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c index f8a8ac343d70..99a8344b00db 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk = { }, }; +static struct clk_branch gpu_cc_cx_accu_shift_clk = { + .halt_reg = 0x95e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x95e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_accu_shift_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_cx_ff_clk = { .halt_reg = 0x914c, .halt_check = BRANCH_HALT, @@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk = { }, }; +static struct clk_branch gpu_cc_gx_accu_shift_clk = { + .halt_reg = 0x95e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x95e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_gx_accu_shift_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { .halt_reg = 0x7000, .halt_check = BRANCH_HALT_VOTED, @@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = { [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] = NULL, [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, @@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = { [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] = NULL, [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, @@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = { }; static const struct of_device_id gpu_cc_sa8775p_match_table[] = { + { .compatible = "qcom,qcs8300-gpucc" }, { .compatible = "qcom,sa8775p-gpucc" }, { } }; @@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) { + gpu_cc_pll0_config.l = 0x31; + gpu_cc_pll0_config.alpha = 0xe555; + + gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr; + gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr; + } + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); From patchwork Thu Oct 24 13:31:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 838146 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32DF61F5855; Thu, 24 Oct 2024 13:32:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729776723; cv=none; b=YTXG/4mHQSQ+rYsiIfV3/5xu0zT5m1PTNY7TDHPc01YZW6FU+v5MxZ+Gp0NCUwUzinyqXSL3BacvBuD1v1x2ihG2L4VK808tjeNWRNKLSw+V4SyGWnL52DI8l37uB3cuhVnHKsIk1uSFNLf5ZZmKQHJyuXB6AIGOqEI6CfoXAnE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729776723; c=relaxed/simple; bh=gnaZBrHw6Y06sk/K4PEIIl9i/nErCdVqzLZNDCyk1uE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qK/R/WvWgqJ6ov3hgGe8he1X8pTJaTljSkqGZ7xDRreTBR90dpBRMoNHJql/LxTtjvh19Z9Mo4foKJahwR8fyghRRNvJk9iI5PMFDB778gYd9hf311fmmOZn3k4b/s1DcKTN1Iw4i41du6vT1JWbNLHqUzYCkJc9rrWKG3gDimM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aTra7APL; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aTra7APL" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49O9pJG6005091; Thu, 24 Oct 2024 13:31:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= gZgrw86mYvz5SNMZxTklmU2+XSi1g6JxNhzC2L+S4Bc=; b=aTra7APLg+jk+e08 FSXJvmlbe2ElFP+HgKN8NM4vct6jEnK8z9ThX6GYiqkl7M2k0hgwr0n/oHOay0/K EKqipMlMX5LMwscGcse9tO5XjmwaLV2tGr2Hmi8rYkaL4/w2e1rP8goJLhjD0hzl T1OKcpODbAMrujCvB8VObPueLvYWYS8Jv3ubiP1+195WNwCBjPy1FBDsRPz83TPv ML4HNwQcg8jub6SZOxgk+93pORP+VWnZGqDknTbJKkM+tMQJfMSkpp5tJLK0VssP X0I9/Ac/dVrtb6+VZ/G0JiRkNfHkP7uqjvMZvk5orzjm5H/bhv9XDw5WaEYzUfw9 rdSzgg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em685rsv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 13:31:57 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49ODVtu0028781 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 13:31:55 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 06:31:51 -0700 From: Imran Shaik Date: Thu, 24 Oct 2024 19:01:17 +0530 Subject: [PATCH v2 4/6] clk: qcom: Add support for Camera Clock Controller on QCS8300 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241024-qcs8300-mm-patches-v2-4-76c905060d0a@quicinc.com> References: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> In-Reply-To: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik , Dmitry Baryshkov X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0f-_HXTP827mzry3xEjBannnfa4MKXRz X-Proofpoint-GUID: 0f-_HXTP827mzry3xEjBannnfa4MKXRz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410240110 Add support to the QCS8300 Camera clock controller by extending the SA8775P Camera clock controller, which is mostly identical but QCS8300 has few additional clocks and few other differences. Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/camcc-sa8775p.c | 99 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa8775p.c index c04801a5af35..0ef3c6015c34 100644 --- a/drivers/clk/qcom/camcc-sa8775p.c +++ b/drivers/clk/qcom/camcc-sa8775p.c @@ -1682,6 +1682,24 @@ static struct clk_branch cam_cc_sm_obs_clk = { }, }; +static struct clk_branch cam_cc_titan_top_accu_shift_clk = { + .halt_reg = 0x131f0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x131f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_titan_top_accu_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc cam_cc_titan_top_gdsc = { .gdscr = 0x131bc, .en_rest_wait_val = 0x2, @@ -1776,6 +1794,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = { [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr, + [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL, [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, }; @@ -1812,6 +1831,7 @@ static struct qcom_cc_desc cam_cc_sa8775p_desc = { }; static const struct of_device_id cam_cc_sa8775p_match_table[] = { + { .compatible = "qcom,qcs8300-camcc" }, { .compatible = "qcom,sa8775p-camcc" }, { } }; @@ -1842,10 +1862,81 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - /* Keep some clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) { + cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154; + cam_cc_camnoc_axi_clk.halt_reg = 0x1316c; + cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c; + cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174; + cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174; + + cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054; + cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078; + cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098; + cam_cc_csid_clk_src.cmd_rcgr = 0x13134; + + cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000; + cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c; + cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038; + + cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104; + cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c; + cam_cc_xo_clk_src.cmd_rcgr = 0x131b8; + cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4; + + cam_cc_core_ahb_clk.halt_reg = 0x131b4; + cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4; + + cam_cc_cpas_ahb_clk.halt_reg = 0x130f4; + cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4; + cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc; + cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc; + + cam_cc_csi0phytimer_clk.halt_reg = 0x1506c; + cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c; + cam_cc_csi1phytimer_clk.halt_reg = 0x15090; + cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090; + cam_cc_csi2phytimer_clk.halt_reg = 0x150b0; + cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0; + cam_cc_csid_clk.halt_reg = 0x1314c; + cam_cc_csid_clk.clkr.enable_reg = 0x1314c; + cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074; + cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074; + cam_cc_csiphy0_clk.halt_reg = 0x15070; + cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070; + cam_cc_csiphy1_clk.halt_reg = 0x15094; + cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094; + cam_cc_csiphy2_clk.halt_reg = 0x150b4; + cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4; + + cam_cc_mclk0_clk.halt_reg = 0x15018; + cam_cc_mclk0_clk.clkr.enable_reg = 0x15018; + cam_cc_mclk1_clk.halt_reg = 0x15034; + cam_cc_mclk1_clk.clkr.enable_reg = 0x15034; + cam_cc_mclk2_clk.halt_reg = 0x15050; + cam_cc_mclk2_clk.clkr.enable_reg = 0x15050; + + cam_cc_titan_top_gdsc.gdscr = 0x131a0; + + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = + &cam_cc_titan_top_accu_shift_clk.clkr; + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ + } else { + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + } ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); From patchwork Thu Oct 24 13:31:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 838145 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEFC01F667E; Thu, 24 Oct 2024 13:32:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729776730; cv=none; b=QRlxPmfX6wE1goEfTo9WUegGU/b+gLmXqA99MvXnz6z8l4T7vIHoo/8RIZV5XKfGbMoKW1M8ST17zWPwLzXjyKUa0/jWxHNAGU0f6bUVL1r299/9fkNY6KP+K+XfTk6y5fGmfmHIBz6KvUj55ofNrsNKygTZ/ZEfcjLjjlp4Egc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729776730; c=relaxed/simple; bh=Mn2pmr6wwJiDzx8Q+vyNXKeaGJlP9Z5kxfsmkd+Ur1Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nPpM/dhUWIcXZgWK8GbWOftBwVWUZymlEykEBbYdT9959V93tCcSl2mP+plcEWKduaFWW0tlqyIaTJMLjW1NfwKOcAV6hJfBGTULyZ8i0suahhQJ1iRoDuFleoVhP8pKJu4ecP+4WioD6ON0HPXB0T6/jtwfcPJYiWc7/PGk7EA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=H6lZmS94; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="H6lZmS94" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49O9aJeJ028304; Thu, 24 Oct 2024 13:32:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ZtMlp4gGjKBW6FEZSa2ElwA4XN8uyE3U9LyxPPYzKiI=; b=H6lZmS947vbQ2sgJ 2lCXgGmmBn6VUVLj1ozFz/C2WU1woQ4entH57AwUx2yjPzaVNq+Av886d0Umv0KU Gu/QQCPJycPVRsYe6Vo+v/NM454CK4afZjXx6ELQW1Lzz36wXmXQZmGhbBEskjYB S/mbbG+RNSnYQkhrkt2T4oWhbmw//S00mBVLJRPg47fSNiXVa7gfMZsH683pGcMO EDrujaTwioW8Rxshwy2fsTp9QryDLUl0CDfLJ4t1u22KM4mHH2o/rmZbzzL3QEEG Ei215/+CWO2Uzr7OGAdktecujm59Wqy5HQENhOpV8hK1cLgCoc6ZWa4cGVHMMBUg f0pVog== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42em41wr25-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 13:32:05 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49ODW4K3011643 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Oct 2024 13:32:04 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 06:32:00 -0700 From: Imran Shaik Date: Thu, 24 Oct 2024 19:01:19 +0530 Subject: [PATCH v2 6/6] clk: qcom: Add support for Video Clock Controller on QCS8300 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241024-qcs8300-mm-patches-v2-6-76c905060d0a@quicinc.com> References: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> In-Reply-To: <20241024-qcs8300-mm-patches-v2-0-76c905060d0a@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ceIQ2rEd0lUguhqMY5t8TUoA8Qz6iBE5 X-Proofpoint-ORIG-GUID: ceIQ2rEd0lUguhqMY5t8TUoA8Qz6iBE5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410240110 Add support to the QCS8300 Video clock controller by extending the SA8775P Video clock controller, which is mostly identical but QCS8300 has minor difference. Signed-off-by: Imran Shaik --- drivers/clk/qcom/videocc-sa8775p.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/videocc-sa8775p.c b/drivers/clk/qcom/videocc-sa8775p.c index bf5de411fd5d..db492984fd7d 100644 --- a/drivers/clk/qcom/videocc-sa8775p.c +++ b/drivers/clk/qcom/videocc-sa8775p.c @@ -523,6 +523,7 @@ static struct qcom_cc_desc video_cc_sa8775p_desc = { }; static const struct of_device_id video_cc_sa8775p_match_table[] = { + { .compatible = "qcom,qcs8300-videocc" }, { .compatible = "qcom,sa8775p-videocc" }, { } }; @@ -550,6 +551,13 @@ static int video_cc_sa8775p_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_evo_pll_configure(&video_pll1, regmap, &video_pll1_config); + /* + * Set mvs0c clock divider to div-3 to make the mvs0 and + * mvs0c clocks to run at the same frequency on QCS8300 + */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-videocc")) + regmap_write(regmap, video_cc_mvs0c_div2_div_clk_src.reg, 2); + /* Keep some clocks always enabled */ qcom_branch_set_clk_en(regmap, 0x80ec); /* VIDEO_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x8144); /* VIDEO_CC_SLEEP_CLK */