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AJvYcCWQSK+C6A29weZiSGEkOxSocq5G84M8UIXyiHxdmvaHrlpGEjBy1cuCpd7htjj8t3AgKhXiwY7FhLL3@vger.kernel.org X-Gm-Message-State: AOJu0YxvW8ufFT0qJA3dd3VdjzeOQFPeMFC9amvdePoW2FRdiblZoB0I t6lGn7kF4So8eP57TBXNjGvIsBphTi4uxGrDyMqoRdkCvhXtyQiz5d073UD2o1w= X-Google-Smtp-Source: AGHT+IEoUmmF2a29+b6OYTb4dbCjEKsfEZfPzHCBO3Ytnq8YsVvh+s+5uHtHvSiBw8IREAZ9aiGHMw== X-Received: by 2002:a05:600c:468f:b0:42c:a6da:a149 with SMTP id 5b1f17b1804b1-4318c73a46amr48990985e9.25.1729862089150; Fri, 25 Oct 2024 06:14:49 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:14:48 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 01/11] scsi: ufs: exynos: Allow UFS Gear 4 Date: Fri, 25 Oct 2024 14:14:32 +0100 Message-ID: <20241025131442.112862-2-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 UFS Gear 4 offers faster speeds, and better power usage so lets enable it. Currently ufshcd_init_host_params() sets UFS_HS_G3 as a default, so even if the device supports G4 we end up negotiating down to G3. For SoCs like gs101 which have a UFS major controller version of 3 or above advertise Gear 4. This then allows a Gear 4 link on Pixel 6. For earlier controller versions keep the current default behaviour of reporting G3. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 9ec318ef52bf..e25de4b86ac0 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -771,6 +771,21 @@ static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs, exynos_ufs_disable_ov_tm(hba); } +#define UFS_HW_VER_MAJOR_MASK GENMASK(15, 8) + +static u32 exynos_ufs_get_hs_gear(struct ufs_hba *hba) +{ + u8 major; + + major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, hba->ufs_version); + + if (major >= 3) + return UFS_HS_G4; + + /* Default is HS-G3 */ + return UFS_HS_G3; +} + static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_max_params, struct ufs_pa_layer_attr *dev_req_params) @@ -787,6 +802,8 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, } ufshcd_init_host_params(&host_params); + /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */ + host_params.hs_tx_gear = host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); 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Fri, 25 Oct 2024 06:14:50 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 02/11] scsi: ufs: exynos: add check inside exynos_ufs_config_smu() Date: Fri, 25 Oct 2024 14:14:33 +0100 Message-ID: <20241025131442.112862-3-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move the EXYNOS_UFS_OPT_UFSPR_SECURE check inside exynos_ufs_config_smu(). This way all call sites will benefit from the check. This fixes a bug currently in the exynos_ufs_resume() path on gs101 which will cause a serror. Fixes: d11e0a318df8 ("scsi: ufs: exynos: Add support for Tensor gs101 SoC") Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index e25de4b86ac0..939d08bce545 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -724,6 +724,9 @@ static void exynos_ufs_config_smu(struct exynos_ufs *ufs) { u32 reg, val; + if (ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE) + return; + exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); /* make encryption disabled by default */ @@ -1457,8 +1460,8 @@ static int exynos_ufs_init(struct ufs_hba *hba) if (ret) goto out; exynos_ufs_specify_phy_time_attr(ufs); - if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) - exynos_ufs_config_smu(ufs); + + exynos_ufs_config_smu(ufs); hba->host->dma_alignment = DATA_UNIT_SIZE - 1; return 0; From patchwork Fri Oct 25 13:14:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 838676 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5ECC32003C1 for ; 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Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 939d08bce545..d685d3e93ea1 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -2142,8 +2142,7 @@ static const struct exynos_ufs_drv_data gs101_ufs_drvs = { UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, - .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | - EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | + .opts = EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | EXYNOS_UFS_OPT_UFSPR_SECURE | EXYNOS_UFS_OPT_TIMER_TICK_SELECT, .drv_init = exynosauto_ufs_drv_init, From patchwork Fri Oct 25 13:14:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 838675 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2DA820BB23 for ; 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Fri, 25 Oct 2024 06:14:54 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:14:53 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 04/11] scsi: ufs: exynos: Add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR check Date: Fri, 25 Oct 2024 14:14:35 +0100 Message-ID: <20241025131442.112862-5-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The values calculated in exynos_ufs_specify_phy_time_attr() are only used in exynos_ufs_config_phy_time_attr() and exynos_ufs_config_phy_cap_attr() if EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR flag is not set. Add a check for this flag to exynos_ufs_specify_phy_time_attr() and return for platforms that don't set it. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index d685d3e93ea1..a1a2fdcb8a40 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -546,6 +546,9 @@ static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; + if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR) + return; + t_cfg->tx_linereset_p = exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); t_cfg->tx_linereset_n = From patchwork Fri Oct 25 13:14:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 839089 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A96320BB3B for ; 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Fri, 25 Oct 2024 06:14:55 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:14:55 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 05/11] scsi: ufs: exynos: gs101: remove unused phy attribute fields Date: Fri, 25 Oct 2024 14:14:36 +0100 Message-ID: <20241025131442.112862-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Now that exynos_ufs_specify_phy_time_attr() checks the appropriate EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR flag. Remove the unused fields in gs101_uic_attr. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index a1a2fdcb8a40..9d668d13fe94 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -2068,26 +2068,6 @@ static const struct exynos_ufs_drv_data exynos_ufs_drvs = { static struct exynos_ufs_uic_attr gs101_uic_attr = { .tx_trailingclks = 0xff, - .tx_dif_p_nsec = 3000000, /* unit: ns */ - .tx_dif_n_nsec = 1000000, /* unit: ns */ - .tx_high_z_cnt_nsec = 20000, /* unit: ns */ - .tx_base_unit_nsec = 100000, /* unit: ns */ - .tx_gran_unit_nsec = 4000, /* unit: ns */ - .tx_sleep_cnt = 1000, /* unit: ns */ - .tx_min_activatetime = 0xa, - .rx_filler_enable = 0x2, - .rx_dif_p_nsec = 1000000, /* unit: ns */ - .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ - .rx_base_unit_nsec = 100000, /* unit: ns */ - .rx_gran_unit_nsec = 4000, /* unit: ns */ - .rx_sleep_cnt = 1280, /* unit: ns */ - .rx_stall_cnt = 320, /* unit: ns */ - .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), - .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), - .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), - .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), - .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), - .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), .pa_dbg_opt_suite1_val = 0x90913C1C, .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1, .pa_dbg_opt_suite2_val = 0xE01C115F, From patchwork Fri Oct 25 13:14:37 2024 Content-Type: text/plain; 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Secondly this assignment can't get executed as samsung,sysreg dt property is provided in for this platform. Meaning the execution flow will return on regmap_update_bits call above. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 9d668d13fe94..d4e786afbbbc 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -205,8 +205,6 @@ static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) { - struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; - /* IO Coherency setting */ if (ufs->sysreg) { return regmap_update_bits(ufs->sysreg, @@ -214,8 +212,6 @@ static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) UFS_SHARABLE, UFS_SHARABLE); } - attr->tx_dif_p_nsec = 3200000; - return 0; } From patchwork Fri Oct 25 13:14:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 838674 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E85020D507 for ; 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Fri, 25 Oct 2024 06:14:58 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:14:58 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 07/11] scsi: ufs: exynos: add gs101_ufs_drv_init() hook and enable WriteBooster Date: Fri, 25 Oct 2024 14:14:38 +0100 Message-ID: <20241025131442.112862-8-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Factor out the common code into a new exynos_ufs_shareability() function and provide a dedicated gs101_drv_init() hook. This allows us to enable WriteBooster capability (UFSHCD_CAP_WB_EN) in a way that doesn't effect other SoCs supported in this driver. WriteBooster improves write speeds by enabling a pseudo SLC cache. Using the `fio seqwrite` test we can achieve speeds of 945MB/s with this feature enabled (until the cache is exhausted) before dropping back to ~260MB/s (which are the speeds we see without the WriteBooster feature enabled). Assuming the UFSHCD_CAP_WB_EN capability is set by the host then WriteBooster can also be enabled and disabled via sysfs so it is possible for the system to only enable it when extra write performance is required. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index d4e786afbbbc..40b2563fe011 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -203,7 +203,7 @@ static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) return 0; } -static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) +static int exynos_ufs_shareability(struct exynos_ufs *ufs) { /* IO Coherency setting */ if (ufs->sysreg) { @@ -215,6 +215,21 @@ static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) return 0; } +static int gs101_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) +{ + struct ufs_hba *hba = ufs->hba; + + /* Enable WriteBooster */ + hba->caps |= UFSHCD_CAP_WB_EN; + + return exynos_ufs_shareability(ufs); +} + +static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) +{ + return exynos_ufs_shareability(ufs); +} + static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) { struct ufs_hba *hba = ufs->hba; @@ -2124,7 +2139,7 @@ static const struct exynos_ufs_drv_data gs101_ufs_drvs = { .opts = EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | EXYNOS_UFS_OPT_UFSPR_SECURE | EXYNOS_UFS_OPT_TIMER_TICK_SELECT, - .drv_init = exynosauto_ufs_drv_init, + .drv_init = gs101_ufs_drv_init, .pre_link = gs101_ufs_pre_link, .post_link = gs101_ufs_post_link, .pre_pwr_change = gs101_ufs_pre_pwr_change, From patchwork Fri Oct 25 13:14:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 839087 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 661E5231C91 for ; Fri, 25 Oct 2024 13:15:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 25 Oct 2024 06:14:59 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:14:59 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 08/11] scsi: ufs: exynos: enable write line unique transactions on gs101 Date: Fri, 25 Oct 2024 14:14:39 +0100 Message-ID: <20241025131442.112862-9-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Previously just AXIDMA_RWDATA_BURST_LEN[3:0] field was set to 8. To enable WLU transaction additionally we need to set Write Line Unique enable [31], Write Line Unique Burst Length [30:27] and AXIDMA_RWDATA_BURST_LEN[3:0]. To support WLU transaction, both burth length fields need to be 0x3. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 40b2563fe011..b0cbb147c7a1 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -48,6 +48,8 @@ #define HCI_UNIPRO_APB_CLK_CTRL 0x68 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C +#define WLU_EN BIT(31) +#define WLU_BURST_LEN(x) ((x) << 27 | ((x) & 0xF)) #define HCI_GPIO_OUT 0x70 #define HCI_ERR_EN_PA_LAYER 0x78 #define HCI_ERR_EN_DL_LAYER 0x7C @@ -1925,6 +1927,12 @@ static int gs101_ufs_post_link(struct exynos_ufs *ufs) { struct ufs_hba *hba = ufs->hba; + /* + * Enable Write Line Unique. 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Fri, 25 Oct 2024 06:15:00 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 09/11] scsi: ufs: exynos: set ACG to be controlled by UFS_ACG_DISABLE Date: Fri, 25 Oct 2024 14:14:40 +0100 Message-ID: <20241025131442.112862-10-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 HCI_IOP_ACG_DISABLE is an undocumented register in the TRM but the downstream driver sets this register so we follow suit here. The register is already 0 presumed to be set by the bootloader as the comment downstream implies the reset state is 1. So whilst this is a nop currently, it should help with suspend/resume. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index b0cbb147c7a1..fa4e61f152c4 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -76,6 +76,10 @@ #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ UNIPRO_PCLK_CTRL_EN |\ UNIPRO_MCLK_CTRL_EN) + +#define HCI_IOP_ACG_DISABLE 0x100 +#define HCI_IOP_ACG_DISABLE_EN BIT(0) + /* Device fatal error */ #define DFES_ERR_EN BIT(31) #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ @@ -220,10 +224,15 @@ static int exynos_ufs_shareability(struct exynos_ufs *ufs) static int gs101_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) { struct ufs_hba *hba = ufs->hba; + u32 reg; /* Enable WriteBooster */ hba->caps |= UFSHCD_CAP_WB_EN; + /* set ACG to be controlled by UFS_ACG_DISABLE */ + reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE); + hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE); 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In v2 this was updated to an enum based on the review feedback in [1]. ufs-exynos hibernate calls have always been broken upstream as it follows the v1 bool implementation. [1] https://patchwork.kernel.org/project/linux-scsi/patch/001f01d23994$719997c0$54ccc740$@samsung.com/ Signed-off-by: Peter Griffin --- --- drivers/ufs/host/ufs-exynos.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index fa4e61f152c4..3bbb71f7bae7 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -1529,12 +1529,12 @@ static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) hci_writel(ufs, 1 << 0, HCI_GPIO_OUT); } -static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter) +static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) { struct exynos_ufs *ufs = ufshcd_get_variant(hba); struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; - if (!enter) { + if (cmd == UIC_CMD_DME_HIBER_EXIT) { if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) exynos_ufs_disable_auto_ctrl_hcc(ufs); exynos_ufs_ungate_clks(ufs); @@ -1562,11 +1562,11 @@ static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter) } } -static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter) +static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) { struct exynos_ufs *ufs = ufshcd_get_variant(hba); - if (!enter) { + if (cmd == UIC_CMD_DME_HIBER_EXIT) { u32 cur_mode = 0; u32 pwrmode; @@ -1585,7 +1585,7 @@ static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter) if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) exynos_ufs_establish_connt(ufs); - } else { + } else if (cmd == UIC_CMD_DME_HIBER_ENTER) { ufs->entry_hibern8_t = ktime_get(); exynos_ufs_gate_clks(ufs); if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) @@ -1672,15 +1672,15 @@ static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, } static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, - enum uic_cmd_dme enter, + enum uic_cmd_dme cmd, enum ufs_notify_change_status notify) { switch ((u8)notify) { case PRE_CHANGE: - exynos_ufs_pre_hibern8(hba, enter); + exynos_ufs_pre_hibern8(hba, cmd); break; case POST_CHANGE: - exynos_ufs_post_hibern8(hba, enter); + exynos_ufs_post_hibern8(hba, cmd); break; } } From patchwork Fri Oct 25 13:14:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 838672 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC999231CA4 for ; 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Fri, 25 Oct 2024 06:15:04 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:15:03 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 11/11] scsi: ufs: exynos: gs101: enable clock gating with hibern8 Date: Fri, 25 Oct 2024 14:14:42 +0100 Message-ID: <20241025131442.112862-12-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable clock gating and hibern8 capabilities for gs101. This leads to a significantly cooler phone when running the upstream kernel. The exynos_ufs_post_hibern8() hook is also updated to remove the UIC_CMD_DME_HIBER_EXIT code path as this causes a hang on gs101. The code path is removed rather than re-factored as no other SoC in ufs-exynos driver sets UFSHCD_CAP_HIBERN8_WITH_CLK_GATING capability. Additionally until the previous commit the hibern8 callbacks were broken anyway as they expected a bool. Signed-off-by: Peter Griffin --- drivers/ufs/host/ufs-exynos.c | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 3bbb71f7bae7..7c8195f27bb6 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -229,6 +229,9 @@ static int gs101_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) /* Enable WriteBooster */ hba->caps |= UFSHCD_CAP_WB_EN; + /* Enable clock gating and hibern8 */ + hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; + /* set ACG to be controlled by UFS_ACG_DISABLE */ reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE); hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE); @@ -1566,26 +1569,7 @@ static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) { struct exynos_ufs *ufs = ufshcd_get_variant(hba); - if (cmd == UIC_CMD_DME_HIBER_EXIT) { - u32 cur_mode = 0; - u32 pwrmode; - - if (ufshcd_is_hs_mode(&ufs->dev_req_params)) - pwrmode = FAST_MODE; - else - pwrmode = SLOW_MODE; - - ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode); - if (cur_mode != (pwrmode << 4 | pwrmode)) { - dev_warn(hba->dev, "%s: power mode change\n", __func__); - hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; - hba->pwr_info.pwr_tx = cur_mode & 0xf; - ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); - } - - if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) - exynos_ufs_establish_connt(ufs); - } else if (cmd == UIC_CMD_DME_HIBER_ENTER) { + if (cmd == UIC_CMD_DME_HIBER_ENTER) { ufs->entry_hibern8_t = ktime_get(); exynos_ufs_gate_clks(ufs); if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)