From patchwork Mon Oct 28 06:05:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 839182 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 340A718DF81; Mon, 28 Oct 2024 06:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730095549; cv=none; b=s2c/8qy8ISiFHKAK9dSiYVlLyIJfvi+OZrSL9vzOLL0zKHcUsEW1l2Ym83PDHTunT76tEWDmbqrrATMwAvjRfjUy3QZ7duq2E0ovDy+BAMlHnrpCnRopakYi1Rftj35mYsjA4za8V+pZ/WK5LE/CYwZJY0vTl8MJPMaAtGht/D4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730095549; c=relaxed/simple; bh=7rJjAAFmFhzZ4UK+KU9wn38mYGILozen9mRVegVWG+E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l3vJGnQ+RRLacwbFpvd/dpKUNHVLAaZpL9/8cTe7f6o5T+i/UNk7WXpfrxnmqBNXewY9OsDOTVbhOsoe8MVn6XKRPvObVWw9YSmedwbIvBhtBIDxMZF4txaaXEidx5O8kglfDViAXM6ykxWOd6xX5ZjsjeFdDcwszx9AJwmHkNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=EiLUximr; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="EiLUximr" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49RNRX8g008963; Mon, 28 Oct 2024 06:05:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= LVnFtOXmE+Y7sKGJrZAQcLjc6S03g2DmTdJzfrNUROo=; b=EiLUximrE7wN7tjf 3sMb+rkS3pMbHtQrxQVH6QHhkB1a7vj+0+hPSdrZfzPDb+tq5tEPO4Q1XZ0ZiWrZ FsFIz34G5TRhmGe1W09Fhf6GgYOrRt5hIItCYOCpsYMeCYN7cEElMUs9ZGzf0wUT nQYMeGclWMW5TpG2KMyHaDICNr+0MCIaKkSdUM4MqN+idiF58lWt7NrrRQb5K8B7 DqrEUjhiy17v6uU1cNujs6MVUKGMMOde1dDUVKzgws0t2mzjHCphY4mNdvLdj/jK b6bRfCfvdXKTlfM2M83KRn79IyI0u9SczZsafxXOIt6tDzRQqqr+CfOuScdqKVJw M80A3w== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42grgubt4m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 06:05:33 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49S65WS9016249 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 06:05:32 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 27 Oct 2024 23:05:25 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V5 1/6] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 Date: Mon, 28 Oct 2024 11:35:01 +0530 Message-ID: <20241028060506.246606-2-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028060506.246606-1-quic_srichara@quicinc.com> References: <20241028060506.246606-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: t-UnNmWQiYAktstgA83exxea6eHHVTgx X-Proofpoint-GUID: t-UnNmWQiYAktstgA83exxea6eHHVTgx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 mlxscore=0 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 mlxlogscore=924 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280050 From: Devi Priya Add support for NSS Huayra alpha pll found on ipq9574 SoCs. Programming sequence is the same as that of Huayra type Alpha PLL, so we can re-use the same. Reviewed-by: Dmitry Baryshkov Signed-off-by: Devi Priya --- drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4b1715a5d71a..b8351f8c0b84 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -267,6 +267,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x30, [PLL_OFF_STATUS] = 0x3c, }, + [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_TEST_CTL] = 0x0c, + [PLL_OFF_TEST_CTL_U] = 0x10, + [PLL_OFF_USER_CTL] = 0x14, + [PLL_OFF_CONFIG_CTL] = 0x18, + [PLL_OFF_CONFIG_CTL_U] = 0x1c, + [PLL_OFF_STATUS] = 0x20, + }, + }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 55eca04b23a1..c6d1b8429f95 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -32,6 +32,7 @@ enum { CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, CLK_ALPHA_PLL_TYPE_STROMER_PLUS, + CLK_ALPHA_PLL_TYPE_NSS_HUAYRA, CLK_ALPHA_PLL_TYPE_MAX, }; From patchwork Mon Oct 28 06:05:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 839181 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E64B18DF8D; Mon, 28 Oct 2024 06:06:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730095571; cv=none; b=iLQO30gCqlEs//k2OQwHXzFHeRH+MYbwQbc7fJVCcBG7J0Gx9YFRZ6yKFXP+JI60Ph7N3JiNEeBEUMYCBC+3mmTHGfOiorUKNqgRJ7BdEm3X4WC+f5krjfWf7WO3d4SkuvlqIpGBAsx+BrzbOPF9gHE4jC75FdeyzG2jyJeOY/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730095571; c=relaxed/simple; bh=zxClmlOfsNHVkOG0RUwNUbP0Va1IXbjRxfwaqpAHzSw=; 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Mon, 28 Oct 2024 06:05:51 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 27 Oct 2024 23:05:45 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V5 4/6] dt-bindings: qcom: Add ipq5424 boards Date: Mon, 28 Oct 2024 11:35:04 +0530 Message-ID: <20241028060506.246606-5-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028060506.246606-1-quic_srichara@quicinc.com> References: <20241028060506.246606-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r7SmzSlPQ5gyow33tDc65k9F5Fx_yWzd X-Proofpoint-ORIG-GUID: r7SmzSlPQ5gyow33tDc65k9F5Fx_yWzd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280049 From: Sricharan Ramabadhran The IPQ5424 is Qualcomm's 802.11be SoC for Routers, Gateways and access Points. It has a quad core Cortex-a55 with a per core L1, Unified L2 caches and a common Unified L3 cache. Document the new ipq5424 SoC/board device tree bindings. Acked-by: Krzysztof Kozlowski Signed-off-by: Sricharan Ramabadhran --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 0f18cb35c774..59c325e8a63d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -25,6 +25,7 @@ description: | ipq4018 ipq5018 ipq5332 + ipq5424 ipq6018 ipq8074 ipq9574 @@ -351,6 +352,11 @@ properties: - qcom,ipq5332-ap-mi01.9 - const: qcom,ipq5332 + - items: + - enum: + - qcom,ipq5424-rdp466 + - const: qcom,ipq5424 + - items: - enum: - mikrotik,rb3011 From patchwork Mon Oct 28 06:05:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 839180 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43BB018FC91; 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Mon, 28 Oct 2024 06:06:05 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49S6649f003359 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 06:06:04 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 27 Oct 2024 23:05:58 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V5 6/6] arm64: defconfig: Enable IPQ5424 RDP466 base configs Date: Mon, 28 Oct 2024 11:35:06 +0530 Message-ID: <20241028060506.246606-7-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241028060506.246606-1-quic_srichara@quicinc.com> References: <20241028060506.246606-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: beeTx0Bfp0RbDcPZBKOEJbG7bB0yiVKY X-Proofpoint-GUID: beeTx0Bfp0RbDcPZBKOEJbG7bB0yiVKY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 clxscore=1015 bulkscore=0 adultscore=0 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=751 priorityscore=1501 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280050 From: Sricharan Ramabadhran Enable GCC, Pinctrl for Qualcomm's IPQ5424 SoC which is required to boot IPQ5424-RDP466 boards to a console shell. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sricharan Ramabadhran --- Added reviewed by tag arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 36b33b9f1704..6b7f5f1a3a87 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -596,6 +596,7 @@ CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ5018=y CONFIG_PINCTRL_IPQ5332=y +CONFIG_PINCTRL_IPQ5424=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_IPQ9574=y @@ -1310,6 +1311,7 @@ CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y +CONFIG_IPQ_GCC_5424=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_IPQ_GCC_9574=y