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Add bindings for it. Cc: Konrad Dybcio Cc: Konrad Dybcio Cc: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio [alexey.klimov] slightly changed the commit message Signed-off-by: Alexey Klimov --- .../bindings/clock/qcom,sm6115-lpasscc.yaml | 46 +++++++++++++++++++ .../dt-bindings/clock/qcom,sm6115-lpasscc.h | 15 ++++++ 2 files changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-lpasscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml new file mode 100644 index 000000000000..247b6b0a9f5a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SM6115 + +maintainers: + - Konrad Dybcio + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock controllers provide audio-related resets + on SM6115 and its derivatives. + + See also:: + include/dt-bindings/clock/qcom,sm6115-lpasscc.h + +properties: + compatible: + enum: + - qcom,sm6115-lpassaudiocc + - qcom,sm6115-lpasscc + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + lpass_audiocc: clock-controller@a6a9000 { + compatible = "qcom,sm6115-lpassaudiocc"; + reg = <0x0a6a9000 0x1000>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-lpasscc.h b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h new file mode 100644 index 000000000000..799274517c9a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H + +/* LPASS CC */ +#define LPASS_SWR_TX_CONFIG_CGCR 0 + +/* LPASS_AUDIO CC */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 + +#endif From patchwork Fri Nov 1 01:22:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Klimov X-Patchwork-Id: 840425 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBCD13CF73 for ; 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Thu, 31 Oct 2024 18:22:53 -0700 (PDT) Received: from localhost.localdomain ([2.222.231.247]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c116ad3fsm3501622f8f.95.2024.10.31.18.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2024 18:22:52 -0700 (PDT) From: Alexey Klimov To: konradybcio@kernel.org, konrad.dybcio@oss.qualcomm.com, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, krzk+dt@kernel.org Cc: robh@kernel.org, conor+dt@kernel.org, srinivas.kandagatla@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v2 2/2] clk: qcom: Add SM6115 LPASSCC Date: Fri, 1 Nov 2024 01:22:47 +0000 Message-ID: <20241101012247.216825-3-alexey.klimov@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241101012247.216825-1-alexey.klimov@linaro.org> References: <20241101012247.216825-1-alexey.klimov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Konrad Dybcio SM6115 (and its derivatives or similar SoCs) has an LPASS clock controller block which provides audio-related resets. Add the required code to support them. Cc: Konrad Dybcio Cc: Konrad Dybcio Cc: Srinivas Kandagatla Signed-off-by: Konrad Dybcio [alexey.klimov] fixed compilation errors after rebase, slightly changed the commit message Signed-off-by: Alexey Klimov --- drivers/clk/qcom/Kconfig | 9 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sm6115.c | 85 +++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sm6115.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 953589e07c59..26021166e329 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1193,6 +1193,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_LPASSCC_6115 + tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_6115 + help + Support for the LPASS clock controller on SM6115 devices. + Say Y if you want to toggle LPASS-adjacent resets within + this clock controller to reset the LPASS subsystem. + config SM_TCSRCC_8550 tristate "SM8550 TCSR Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index fac4b9b61e55..784434febd4c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -150,6 +150,7 @@ obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o +obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o obj-$(CONFIG_SM_VIDEOCC_7150) += videocc-sm7150.o diff --git a/drivers/clk/qcom/lpasscc-sm6115.c b/drivers/clk/qcom/lpasscc-sm6115.c new file mode 100644 index 000000000000..8ffdab71b948 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sm6115.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, 2023 Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpass_audiocc_sm6115_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { .reg = 0x98, .bit = 1, .udelay = 500 }, +}; + +static struct regmap_config lpass_audiocc_sm6115_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-audio-csr", + .max_register = 0x1000, +}; + +static const struct qcom_cc_desc lpass_audiocc_sm6115_reset_desc = { + .config = &lpass_audiocc_sm6115_regmap_config, + .resets = lpass_audiocc_sm6115_resets, + .num_resets = ARRAY_SIZE(lpass_audiocc_sm6115_resets), +}; + +static const struct qcom_reset_map lpasscc_sm6115_resets[] = { + [LPASS_SWR_TX_CONFIG_CGCR] = { .reg = 0x100, .bit = 1, .udelay = 500 }, +}; + +static struct regmap_config lpasscc_sm6115_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-tcsr", + .max_register = 0x1000, +}; + +static const struct qcom_cc_desc lpasscc_sm6115_reset_desc = { + .config = &lpasscc_sm6115_regmap_config, + .resets = lpasscc_sm6115_resets, + .num_resets = ARRAY_SIZE(lpasscc_sm6115_resets), +}; + +static const struct of_device_id lpasscc_sm6115_match_table[] = { + { + .compatible = "qcom,sm6115-lpassaudiocc", + .data = &lpass_audiocc_sm6115_reset_desc, + }, { + .compatible = "qcom,sm6115-lpasscc", + .data = &lpasscc_sm6115_reset_desc, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, lpasscc_sm6115_match_table); + +static int lpasscc_sm6115_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_sm6115_driver = { + .probe = lpasscc_sm6115_probe, + .driver = { + .name = "lpasscc-sm6115", + .of_match_table = lpasscc_sm6115_match_table, + }, +}; + +module_platform_driver(lpasscc_sm6115_driver); + +MODULE_DESCRIPTION("QTI LPASSCC SM6115 Driver"); +MODULE_LICENSE("GPL");