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Signed-off-by: Ciprian Marian Costea --- .../bindings/serial/fsl,s32-linflexuart.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml index 4171f524a928..2716a9cd6c22 100644 --- a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml @@ -34,10 +34,24 @@ properties: interrupts: maxItems: 1 + clocks: + items: + - description: + ipg clock drives the access to the LINFlexD + iomapped registers + - description: lin is the frequency of the baud clock + + clock-names: + items: + - const: ipg + - const: lin + required: - compatible - reg - interrupts + - clocks + - clock-names unevaluatedProperties: false @@ -47,4 +61,19 @@ examples: compatible = "fsl,s32v234-linflexuart"; reg = <0x40053000 0x1000>; interrupts = <0 59 4>; + clocks = <&clks 132>, <&clks 131>; + clock-names = "ipg", "lin"; + }; + + - | + #include + #include + + serial@401c8000 { + compatible = "nxp,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401c8000 0x3000>; + interrupts = ; + clocks = <&clks 13>, <&clks 14>; + clock-names = "ipg", "lin"; }; From patchwork Thu Nov 7 11:46:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ciprian Costea X-Patchwork-Id: 841666 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2073.outbound.protection.outlook.com [40.107.20.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5055B20EA2C; Thu, 7 Nov 2024 11:46:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.20.73 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730979988; cv=fail; b=UC/l2pUCj2wTGdslMIOvTzc8F3alHbEEfR7gPBuc94XT+IrSOZILKCKaL1ns9v1Wz7k+5ciwZZJNUiyyTqhsE5OxXNSylsg5v72isywiNIVND4wm+1G2H+/CnVaSTPDm9ig9x9CrEuDkLMydUuOslyOBbNARJUdZcCMkL5BdQys= ARC-Message-Signature: i=2; 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Thu, 7 Nov 2024 11:46:21 +0000 Received: from DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd]) by DU0PR04MB9251.eurprd04.prod.outlook.com ([fe80::708f:69ee:15df:6ebd%6]) with mapi id 15.20.8137.018; Thu, 7 Nov 2024 11:46:21 +0000 From: Ciprian Costea To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chester Lin Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, NXP S32 Linux Team , imx@lists.linux.dev, Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Ciprian Marian Costea Subject: [PATCH v3 2/2] serial: fsl_linflexuart: add clock support Date: Thu, 7 Nov 2024 13:46:11 +0200 Message-ID: <20241107114611.758433-3-ciprianmarian.costea@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107114611.758433-1-ciprianmarian.costea@oss.nxp.com> References: <20241107114611.758433-1-ciprianmarian.costea@oss.nxp.com> X-ClientProxiedBy: AM0PR04CA0114.eurprd04.prod.outlook.com (2603:10a6:208:55::19) To DU0PR04MB9251.eurprd04.prod.outlook.com (2603:10a6:10:352::15) Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|AM9PR04MB8762:EE_ X-MS-Office365-Filtering-Correlation-Id: c9045ccc-782e-470e-82b4-08dcff21cc3b X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|366016|376014; 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It is used by S32G2 and S32G3 SoCs. Clocking support is added as optional in order to not break existing support for S32V234 SoC. Signed-off-by: Ciprian Marian Costea --- drivers/tty/serial/fsl_linflexuart.c | 67 +++++++++++++++++++++------- 1 file changed, 51 insertions(+), 16 deletions(-) diff --git a/drivers/tty/serial/fsl_linflexuart.c b/drivers/tty/serial/fsl_linflexuart.c index e972df4b188d..23aed3bbff6c 100644 --- a/drivers/tty/serial/fsl_linflexuart.c +++ b/drivers/tty/serial/fsl_linflexuart.c @@ -3,9 +3,10 @@ * Freescale LINFlexD UART serial port driver * * Copyright 2012-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2019 NXP + * Copyright 2017-2019, 2024 NXP */ +#include #include #include #include @@ -120,6 +121,12 @@ #define PREINIT_DELAY 2000 /* us */ +struct linflex_port { + struct uart_port port; + struct clk *clk_lin; + struct clk *clk_ipg; +}; + static const struct of_device_id linflex_dt_ids[] = { { .compatible = "fsl,s32v234-linflexuart", @@ -807,12 +814,13 @@ static struct uart_driver linflex_reg = { static int linflex_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + struct linflex_port *lfport; struct uart_port *sport; struct resource *res; int ret; - sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); - if (!sport) + lfport = devm_kzalloc(&pdev->dev, sizeof(*lfport), GFP_KERNEL); + if (!lfport) return -ENOMEM; ret = of_alias_get_id(np, "serial"); @@ -826,6 +834,7 @@ static int linflex_probe(struct platform_device *pdev) return -ENOMEM; } + sport = &lfport->port; sport->line = ret; sport->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); @@ -844,39 +853,65 @@ static int linflex_probe(struct platform_device *pdev) sport->flags = UPF_BOOT_AUTOCONF; sport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE); - linflex_ports[sport->line] = sport; + lfport->clk_lin = devm_clk_get_optional_enabled(&pdev->dev, "lin"); + if (IS_ERR(lfport->clk_lin)) + return dev_err_probe(&pdev->dev, PTR_ERR(lfport->clk_lin), + "Failed to get linflexuart clk\n"); - platform_set_drvdata(pdev, sport); + lfport->clk_ipg = devm_clk_get_optional_enabled(&pdev->dev, "ipg"); + if (IS_ERR(lfport->clk_ipg)) + return dev_err_probe(&pdev->dev, PTR_ERR(lfport->clk_ipg), + "Failed to get linflexuart ipg clk\n"); + + linflex_ports[sport->line] = sport; + platform_set_drvdata(pdev, lfport); return uart_add_one_port(&linflex_reg, sport); } static void linflex_remove(struct platform_device *pdev) { - struct uart_port *sport = platform_get_drvdata(pdev); + struct linflex_port *lfport = platform_get_drvdata(pdev); - uart_remove_one_port(&linflex_reg, sport); + uart_remove_one_port(&linflex_reg, &lfport->port); } -#ifdef CONFIG_PM_SLEEP -static int linflex_suspend(struct device *dev) +static int __maybe_unused linflex_suspend(struct device *dev) { - struct uart_port *sport = dev_get_drvdata(dev); + struct linflex_port *lfport = dev_get_drvdata(dev); + + uart_suspend_port(&linflex_reg, &lfport->port); - uart_suspend_port(&linflex_reg, sport); + clk_disable_unprepare(lfport->clk_lin); + clk_disable_unprepare(lfport->clk_ipg); return 0; } -static int linflex_resume(struct device *dev) +static int __maybe_unused linflex_resume(struct device *dev) { - struct uart_port *sport = dev_get_drvdata(dev); + struct linflex_port *lfport = dev_get_drvdata(dev); + int ret; - uart_resume_port(&linflex_reg, sport); + if (lfport->clk_lin) { + ret = clk_prepare_enable(lfport->clk_lin); + if (ret) { + dev_err(dev, "Failed to enable linflexuart clk: %d\n", ret); + return ret; + } + } - return 0; + if (lfport->clk_ipg) { + ret = clk_prepare_enable(lfport->clk_ipg); + if (ret) { + dev_err(dev, "Failed to enable linflexuart ipg clk: %d\n", ret); + clk_disable_unprepare(lfport->clk_lin); + return ret; + } + } + + return uart_resume_port(&linflex_reg, &lfport->port); } -#endif static SIMPLE_DEV_PM_OPS(linflex_pm_ops, linflex_suspend, linflex_resume);