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Wed, 20 Nov 2024 07:04:04 -0500 (EST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , linux-renesas-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 1/2] thermal: rcar_gen3: Use lowercase hex constants Date: Wed, 20 Nov 2024 13:03:35 +0100 Message-ID: <20241120120336.1063979-2-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241120120336.1063979-1-niklas.soderlund+renesas@ragnatech.se> References: <20241120120336.1063979-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The style of the driver is to use lowercase hex constants, correct the few outlines. Signed-off-by: Niklas Söderlund --- * Changes since v1 - Update a few more defines not related to the fuses missed and pointed out by Geert, thanks! --- drivers/thermal/renesas/rcar_gen3_thermal.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/thermal/renesas/rcar_gen3_thermal.c b/drivers/thermal/renesas/rcar_gen3_thermal.c index 810f86677461..95b636f79e07 100644 --- a/drivers/thermal/renesas/rcar_gen3_thermal.c +++ b/drivers/thermal/renesas/rcar_gen3_thermal.c @@ -21,11 +21,11 @@ /* Register offsets */ #define REG_GEN3_IRQSTR 0x04 #define REG_GEN3_IRQMSK 0x08 -#define REG_GEN3_IRQCTL 0x0C +#define REG_GEN3_IRQCTL 0x0c #define REG_GEN3_IRQEN 0x10 #define REG_GEN3_IRQTEMP1 0x14 #define REG_GEN3_IRQTEMP2 0x18 -#define REG_GEN3_IRQTEMP3 0x1C +#define REG_GEN3_IRQTEMP3 0x1c #define REG_GEN3_THCTR 0x20 #define REG_GEN3_TEMP 0x28 #define REG_GEN3_THCODE1 0x50 @@ -38,9 +38,9 @@ #define REG_GEN4_THSFMON00 0x180 #define REG_GEN4_THSFMON01 0x184 #define REG_GEN4_THSFMON02 0x188 -#define REG_GEN4_THSFMON15 0x1BC -#define REG_GEN4_THSFMON16 0x1C0 -#define REG_GEN4_THSFMON17 0x1C4 +#define REG_GEN4_THSFMON15 0x1bc +#define REG_GEN4_THSFMON16 0x1c0 +#define REG_GEN4_THSFMON17 0x1c4 /* IRQ{STR,MSK,EN} bits */ #define IRQ_TEMP1 BIT(0) @@ -57,11 +57,11 @@ /* THSCP bits */ #define THSCP_COR_PARA_VLD (BIT(15) | BIT(14)) -#define CTEMP_MASK 0xFFF +#define CTEMP_MASK 0xfff #define MCELSIUS(temp) ((temp) * 1000) -#define GEN3_FUSE_MASK 0xFFF -#define GEN4_FUSE_MASK 0xFFF +#define GEN3_FUSE_MASK 0xfff +#define GEN4_FUSE_MASK 0xfff #define TSC_MAX_NUM 5