From patchwork Thu Nov 21 18:52:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844837 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B73141DE3D6 for ; Thu, 21 Nov 2024 18:53:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215203; cv=none; b=O8AdSqAjMvrWqBJ1Kg1PB4Yfk24PSTaHJS2U59vU00BaRgepsoFZv4Isn8zNC/kMEK9ksG+zVmvbeGfHlqQlRdWSsRtslOkdnev6KBExzrWO4I9DAURzPS2KvUSUhK4c7mQcbj0BG7WSNCCj/2e88LER4GboGgyISpu+vK9b8qs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215203; c=relaxed/simple; bh=1MOR7DCPmoVrL2EupOMAwcUroCAGOgOeQudXxZyVN2g=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=MgYpCsZmtQBuEHTohPvhvS0gQAN+QnpcyE6Ud5NGhSF2NVShKZZTsXhInYpHJ4QjcKaN9qBxU6FxKPxS6JVVCrgSIqeDoTsoGuB+QukvN8e6xnTa77LNyv/AzbqtzBfAy/1bfnecfk6DwrI6gQ2zDDyK9/4RPsJpQagocoyMqMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=ktVOWZII; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ktVOWZII" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6eeb9152b2cso23164567b3.1 for ; Thu, 21 Nov 2024 10:53:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1732215201; x=1732820001; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=yX+GRl14cPObJa/kACzBQrLOUmiZNTxc+R8PcnYIGO8=; b=ktVOWZIIM9e6kSmCyKrD20l+GKNugXeKhziRNR5qitJmewhveDSbmql9bIyJ9T+jNp vrZjxMwMO3dZW0op2r6VOPwFb9uRu2SDNUCCl8lCgYKjco+U26fepAXc79EnhWfZ3a6A xQ+8xBNM9sdW6Fikelon+mBeFOHrF0bnr64KIWbR56Hsw8SwB1WEIte7oFiYsHwVQ+Hj unX1vsq2LqutNwCtnA253MTVKR17RUJbPLdni7X9MU8LU4uAg4fKK6CNCI3CObeWccBw 6yb3flmEGYNFIlTLGWp3fU6mCSrga81+eJKUA3fuY7HqjGYBVkvDRZ8TMvWfNtRz+AFt JEvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732215201; x=1732820001; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=yX+GRl14cPObJa/kACzBQrLOUmiZNTxc+R8PcnYIGO8=; b=TyquSS5UhIrrQI72NK+olDFN85KOZFcbw1Q2gf48GPsJc/eIVlcDy6iAr+J998VfHH PqSUK/VHE275V1nI/7mMhuRf7fZJKoHO6QejtgeTRMdTKqZzFhOa9KnEPR7hKD1sKTML VgkgqMbqU/vKNA58cmkoIokNrBnVetPgoaP/S38bsgrwLo7/p5a8rZZVdrh1AJLawfqQ tkYiR8GeqGG3Lwtx+p+m8pavCDVeb3K61JUOzlU56vC+X7KhLNcAHo/NpLeJ4uK/z3iI EP2NTQKRBdSxTu+GxUUJ+Mzgh/UEBA0uHyI+2Yc379+3LcGnzpk01X9btfkxZ1XEDvLd kxnw== X-Forwarded-Encrypted: i=1; AJvYcCWMYfxGqzXzV96fcBz/ieVa/kWA7nzsW5hKEBmd8bRuT1YC1kSe4wclP0SDnBAs0F8IVVglwdKRAQ==@vger.kernel.org X-Gm-Message-State: AOJu0YyvFu8t8+MDcQMZ9Ek1IAwJBgY45pfeUer5aS5mpftoeaqmv3lP wYW1hN1hxFGQiy79efWIINXWlMj60WpqLf2HlG0ZHLrIOrszM7zJdPdi+mxOS/eCKzva8tkhixo Kp/ZREQ== X-Google-Smtp-Source: AGHT+IEaIdHhehjQ/cZzYbs1B5PHMTwy0M/hKHYmKCVWAh5XULvcYUBoSgtrQsU3NFy0g50qZrAVQfI3lmYy X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a05:690c:67c1:b0:6ea:1f5b:1f54 with SMTP id 00721157ae682-6eee07bb768mr3687b3.0.1732215200906; Thu, 21 Nov 2024 10:53:20 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:52:54 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-3-mizhang@google.com> Subject: [RFC PATCH 02/22] x86/aperfmperf: Introduce set_guest_[am]perf() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang From: Jim Mattson KVM guests need access to IA32_APERF and IA32_MPERF to observe their effective CPU frequency, but intercepting reads of these MSRs is too expensive since Linux guests read them every scheduler tick (250 Hz by default). Allow the guest to read these MSRs without interception by loading guest values into the hardware MSRs. When loading a guest value into IA32_APERF or IA32_MPERF: 1. Query the current host value 2. Record the offset between guest and host values in a per-CPU variable 3. Load the guest value into the MSR Modify get_host_[am]perf() to add the per-CPU offset to the raw MSR value, so that host kernel code can still obtain correct host values even when the MSRs contain guest values. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/topology.h | 5 +++++ arch/x86/kernel/cpu/aperfmperf.c | 31 +++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 2ef9903cf85d7..fef5846c01976 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -302,8 +302,13 @@ static inline void arch_set_max_freq_ratio(bool turbo_disabled) { } static inline void freq_invariance_set_perf_ratio(u64 ratio, bool turbo_disabled) { } #endif +DECLARE_PER_CPU(u64, host_aperf_offset); +DECLARE_PER_CPU(u64, host_mperf_offset); + extern u64 get_host_aperf(void); extern u64 get_host_mperf(void); +extern void set_guest_aperf(u64 aperf); +extern void set_guest_mperf(u64 mperf); extern void arch_scale_freq_tick(void); #define arch_scale_freq_tick arch_scale_freq_tick diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmperf.c index 3be5070ba3361..8b66872aa98c1 100644 --- a/arch/x86/kernel/cpu/aperfmperf.c +++ b/arch/x86/kernel/cpu/aperfmperf.c @@ -94,20 +94,47 @@ void arch_set_max_freq_ratio(bool turbo_disabled) } EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio); +DEFINE_PER_CPU(u64, host_aperf_offset); +DEFINE_PER_CPU(u64, host_mperf_offset); + u64 get_host_aperf(void) { WARN_ON_ONCE(!irqs_disabled()); - return native_read_msr(MSR_IA32_APERF); + return native_read_msr(MSR_IA32_APERF) + + this_cpu_read(host_aperf_offset); } EXPORT_SYMBOL_GPL(get_host_aperf); u64 get_host_mperf(void) { WARN_ON_ONCE(!irqs_disabled()); - return native_read_msr(MSR_IA32_MPERF); + return native_read_msr(MSR_IA32_MPERF) + + this_cpu_read(host_mperf_offset); } EXPORT_SYMBOL_GPL(get_host_mperf); +void set_guest_aperf(u64 guest_aperf) +{ + u64 host_aperf; + + WARN_ON_ONCE(!irqs_disabled()); + host_aperf = get_host_aperf(); + wrmsrl(MSR_IA32_APERF, guest_aperf); + this_cpu_write(host_aperf_offset, host_aperf - guest_aperf); +} +EXPORT_SYMBOL_GPL(set_guest_aperf); + +void set_guest_mperf(u64 guest_mperf) +{ + u64 host_mperf; + + WARN_ON_ONCE(!irqs_disabled()); + host_mperf = get_host_mperf(); + wrmsrl(MSR_IA32_MPERF, guest_mperf); + this_cpu_write(host_mperf_offset, host_mperf - guest_mperf); +} +EXPORT_SYMBOL_GPL(set_guest_mperf); + static bool __init turbo_disabled(void) { u64 misc_en; From patchwork Thu Nov 21 18:52:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844836 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66F9B1DE8A7 for ; Thu, 21 Nov 2024 18:53:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215207; cv=none; b=kAsKyETHXWj2exHm2uJajabTySkh4zy8bF3TAeE5ptyqSyfQBMeEciJKTY3wWjkTzUDgiFqjROASZfQ+OQmHxYPXAJSsmwa35YAGcVLP7u/mDPpJzdRNRJv3TZFWmD+c3TxrfVtKSfLDRgLZrM4ePBjJoyzRFDHOJX9dKRwqP0I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang From: Jim Mattson When reading IA32_APERF or IA32_MPERF remotely via /dev/cpu/*/msr, account for any offset between the hardware MSR value and the true host value. This ensures tools like turbostat get correct host values even when the hardware MSRs contain guest values. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/lib/msr-smp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index acd463d887e1c..43c5d21e840fb 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -4,6 +4,15 @@ #include #include #include +#include + +static void adjust_host_aperfmperf(u32 msr_no, struct msr *reg) +{ + if (msr_no == MSR_IA32_APERF) + reg->q += this_cpu_read(host_aperf_offset); + else if (msr_no == MSR_IA32_MPERF) + reg->q += this_cpu_read(host_mperf_offset); +} static void __rdmsr_on_cpu(void *info) { @@ -16,6 +25,7 @@ static void __rdmsr_on_cpu(void *info) reg = &rv->reg; rdmsr(rv->msr_no, reg->l, reg->h); + adjust_host_aperfmperf(rv->msr_no, reg); } static void __wrmsr_on_cpu(void *info) @@ -154,6 +164,7 @@ static void __rdmsr_safe_on_cpu(void *info) struct msr_info_completion *rv = info; rv->msr.err = rdmsr_safe(rv->msr.msr_no, &rv->msr.reg.l, &rv->msr.reg.h); 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang From: Jim Mattson Factor out common code that handles the transition from HALTED/AP_RESET_HOLD to RUNNABLE state. In addition to changing mp_state, this transition has side effects (clearing pv_unhalted, apf.halted) which must be handled consistently across all code paths. As future patches add more side effects to this state transition, this helper ensures they will be applied uniformly at all transition points. No functional change intended. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/x86.c | 16 +++++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 6d9f763a7bb9d..04ef56d10cbb1 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -2283,6 +2283,8 @@ static inline bool kvm_is_supported_user_return_msr(u32 msr) return kvm_find_user_return_msr(msr) >= 0; } +void kvm_vcpu_make_runnable(struct kvm_vcpu *vcpu); + u64 kvm_scale_tsc(u64 tsc, u64 ratio); u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 83fe0a78146fc..3c6b0ca91e5f5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11167,6 +11167,16 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); } +void kvm_vcpu_make_runnable(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED || + vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) + vcpu->arch.pv.pv_unhalted = false; + vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; + vcpu->arch.apf.halted = false; +} +EXPORT_SYMBOL_GPL(kvm_vcpu_make_runnable); + /* Called within kvm->srcu read side. */ static inline int vcpu_block(struct kvm_vcpu *vcpu) { @@ -11222,12 +11232,8 @@ static inline int vcpu_block(struct kvm_vcpu *vcpu) switch(vcpu->arch.mp_state) { case KVM_MP_STATE_HALTED: case KVM_MP_STATE_AP_RESET_HOLD: - vcpu->arch.pv.pv_unhalted = false; - vcpu->arch.mp_state = - KVM_MP_STATE_RUNNABLE; - fallthrough; case KVM_MP_STATE_RUNNABLE: - vcpu->arch.apf.halted = false; + kvm_vcpu_make_runnable(vcpu); break; case KVM_MP_STATE_INIT_RECEIVED: break; From patchwork Thu Nov 21 18:52:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844834 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7255B1DF731 for ; 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Thu, 21 Nov 2024 10:53:29 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:52:59 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-8-mizhang@google.com> Subject: [RFC PATCH 07/22] KVM: nSVM: Nested #VMEXIT may transition from HALTED to RUNNABLE From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang From: Jim Mattson When a halted vCPU is awakened by a nested event, it might have been the target of a previous KVM_HC_KICK_CPU hypercall, in which case pv_unhalted would be set. This flag should be cleared before the next HLT instruction, as kvm_vcpu_has_events() would otherwise return true and prevent the vCPU from entering the halt state. Use kvm_vcpu_make_runnable() to ensure consistent handling of the HALTED to RUNNABLE state transition. Fixes: 38c0b192bd6d ("KVM: SVM: leave halted state on vmexit") Signed-off-by: Jim Mattson --- arch/x86/kvm/svm/nested.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index cf84103ce38b9..49e6cdfeac4da 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -994,7 +994,7 @@ int nested_svm_vmexit(struct vcpu_svm *svm) kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); /* in case we halted in L2 */ - svm->vcpu.arch.mp_state = KVM_MP_STATE_RUNNABLE; + kvm_vcpu_make_runnable(vcpu); /* Give the current vmcb to the guest */ From patchwork Thu Nov 21 18:53:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844833 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FB591DFDB4 for ; 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Thu, 21 Nov 2024 10:53:32 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:01 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-10-mizhang@google.com> Subject: [RFC PATCH 09/22] KVM: x86: Introduce KVM_X86_FEATURE_APERFMPERF From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang The APERFMPERF feature bit appears in CPUID.6H:ECX[0], but is exposed to Linux via X86_FEATURE_APERFMPERF in a Linux-defined feature word. To enable KVM's reverse CPUID functionality for this feature, define a KVM feature word matching the hardware CPUID leaf that contains the APERFMPERF bit. This patch only adds the feature definition - enabling and advertising the feature to guests will be handled in later patches. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/reverse_cpuid.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 0d17d6b706396..d12e5d9ab2251 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -18,6 +18,7 @@ enum kvm_only_cpuid_leafs { CPUID_8000_0022_EAX, CPUID_7_2_EDX, CPUID_24_0_EBX, + CPUID_6_ECX, NR_KVM_CPU_CAPS, NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS, @@ -42,6 +43,9 @@ enum kvm_only_cpuid_leafs { #define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1) #define KVM_X86_FEATURE_SGX_EDECCSSA KVM_X86_FEATURE(CPUID_12_EAX, 11) +/* Intel-defined sub-features, CPUID level 0x00000006 (ECX) */ +#define KVM_X86_FEATURE_APERFMPERF KVM_X86_FEATURE(CPUID_6_ECX, 0) + /* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */ #define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4) #define X86_FEATURE_AVX_NE_CONVERT KVM_X86_FEATURE(CPUID_7_1_EDX, 5) @@ -98,6 +102,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX}, [CPUID_7_2_EDX] = { 7, 2, CPUID_EDX}, [CPUID_24_0_EBX] = { 0x24, 0, CPUID_EBX}, + [CPUID_6_ECX] = { 6, 0, CPUID_ECX}, }; /* @@ -135,6 +140,7 @@ static __always_inline u32 __feature_translate(int x86_feature) KVM_X86_TRANSLATE_FEATURE(SGX_EDECCSSA); KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC); KVM_X86_TRANSLATE_FEATURE(PERFMON_V2); + KVM_X86_TRANSLATE_FEATURE(APERFMPERF); KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL); KVM_X86_TRANSLATE_FEATURE(BHI_CTRL); default: From patchwork Thu Nov 21 18:53:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844832 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96D331E04B1 for ; Thu, 21 Nov 2024 18:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215219; cv=none; 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Thu, 21 Nov 2024 10:53:36 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:03 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-12-mizhang@google.com> Subject: [RFC PATCH 11/22] KVM: x86: Initialize guest [am]perf at vcpu power-on From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang From: Jim Mattson The guest's IA32_APERF and IA32_MPERF MSRs start at zero. However, IA32_MPERF should be incremented whenever the vCPU is in C0, just as the host's IA32_MPERF MSR is incremented by hardware. Record the host TSC at vcpu_reset() to start tracking time spent in C0. Later patches will add the host TSC delta to the guest's stored IA32_MPERF value at appropriate points. Signed-off-by: Jim Mattson --- arch/x86/include/asm/kvm_host.h | 9 +++++++++ arch/x86/kvm/x86.c | 7 +++++++ 2 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 04ef56d10cbb1..067e6ec7f7e9c 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -738,6 +738,13 @@ struct kvm_queued_exception { bool has_payload; }; +struct kvm_vcpu_aperfmperf { + u64 guest_aperf; + u64 guest_mperf; + u64 host_tsc; + bool loaded_while_running; +}; + struct kvm_vcpu_arch { /* * rip and regs accesses must go through @@ -1040,6 +1047,8 @@ struct kvm_vcpu_arch { #if IS_ENABLED(CONFIG_HYPERV) hpa_t hv_root_tdp; #endif + + struct kvm_vcpu_aperfmperf aperfmperf; }; struct kvm_lpage_info { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3c6b0ca91e5f5..d66cccff13347 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -12476,6 +12476,13 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); + + /* + * IA32_MPERF should start running now. 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang From: Jim Mattson When a vCPU transitions from HALTED to RUNNABLE, it resumes time keeping: its virtual IA32_MPERF MSR should start accumulating C0 cycles again. Load the guest values into the hardware MSRs for direct guest access. Background cycle accumulation is unnecessary at this point since the vCPU has been in C1, so the guest's IA32_MPERF has been stopped. Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b914578718d9c..acfa9ecc5bc36 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11204,9 +11204,16 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) void kvm_vcpu_make_runnable(struct kvm_vcpu *vcpu) { - if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED || - vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) + switch (vcpu->arch.mp_state) { + case KVM_MP_STATE_HALTED: + if (guest_can_use(vcpu, X86_FEATURE_APERFMPERF) && + vcpu->wants_to_run) + kvm_load_guest_aperfmperf(vcpu, false); + fallthrough; + case KVM_MP_STATE_AP_RESET_HOLD: vcpu->arch.pv.pv_unhalted = false; + break; + } vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; vcpu->arch.apf.halted = false; } From patchwork Thu Nov 21 18:53:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844830 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFFC61E0DD4 for ; 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Thu, 21 Nov 2024 10:53:44 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:07 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-16-mizhang@google.com> Subject: [RFC PATCH 15/22] KVM: x86: Restore host IA32_[AM]PERF on userspace return From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang From: Jim Mattson Add support for restoring host IA32_APERF and IA32_MPERF values when returning to userspace. While not strictly necessary since reads of /dev/cpu/*/msr now reconstruct host values, restoring the host values maintains cleaner system state. Leverage KVM's existing user return notifier infrastructure but add a separate flag since these MSRs require dynamic value restoration rather than static value restoration. Restoration is only performed when guest values have been loaded into the hardware MSRs. Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6df8f21b83eb1..ad5351673362c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -207,6 +207,7 @@ module_param(mitigate_smt_rsb, bool, 0444); struct kvm_user_return_msrs { struct user_return_notifier urn; bool registered; + bool restore_aperfmperf; struct kvm_user_return_msr_values { u64 host; u64 curr; @@ -571,6 +572,11 @@ static void kvm_on_user_return(struct user_return_notifier *urn) * interrupted and executed through kvm_arch_disable_virtualization_cpu() */ local_irq_save(flags); + if (msrs->restore_aperfmperf) { + restore_host_aperf(); + restore_host_mperf(); + msrs->restore_aperfmperf = false; + } if (msrs->registered) { msrs->registered = false; user_return_notifier_unregister(urn); @@ -5003,6 +5009,7 @@ static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) static void kvm_load_guest_aperfmperf(struct kvm_vcpu *vcpu, bool update_mperf) { + struct kvm_user_return_msrs *msrs; unsigned long flags; local_irq_save(flags); @@ -5011,6 +5018,9 @@ static void kvm_load_guest_aperfmperf(struct kvm_vcpu *vcpu, bool update_mperf) set_guest_aperf(vcpu->arch.aperfmperf.guest_aperf); set_guest_mperf(vcpu->arch.aperfmperf.guest_mperf); vcpu->arch.aperfmperf.loaded_while_running = true; + msrs = this_cpu_ptr(user_return_msrs); + kvm_user_return_notifier_register(msrs); + msrs->restore_aperfmperf = true; local_irq_restore(flags); } From patchwork Thu Nov 21 18:53:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844829 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FA5C1E2319 for ; Thu, 21 Nov 2024 18:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; 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Thu, 21 Nov 2024 10:53:47 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:09 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-18-mizhang@google.com> Subject: [RFC PATCH 17/22] KVM: x86: Save guest [am]perf checkpoint on vcpu_put() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang For vCPUs with APERFMPERF that are in KVM_RUN and not halted, checkpoint the current hardware MSR values along with the host TSC when unloading the vCPU. While still in virtual C0 state, the vCPU will no longer run on this physical CPU, requiring different handling for each counter: - IA32_APERF should stop accumulating since no actual CPU cycles are being spent on behalf of the guest - IA32_MPERF should continue accumulating cycles since the guest is still in C0 state Later when the vCPU is reloaded, we'll use this checkpoint and the host TSC delta to properly account for any "background" cycles that should be reflected in the guest's IA32_MPERF value. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 793f5d2afeb2b..7c22bda3b1f7b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5173,6 +5173,11 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) srcu_read_unlock(&vcpu->kvm->srcu, idx); } + if (vcpu->wants_to_run && + guest_can_use(vcpu, X86_FEATURE_APERFMPERF) && + vcpu->arch.aperfmperf.loaded_while_running) + kvm_put_guest_aperfmperf(vcpu); + kvm_x86_call(vcpu_put)(vcpu); vcpu->arch.last_host_tsc = rdtsc(); } From patchwork Thu Nov 21 18:53:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844828 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 840FC1E284D for ; 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Thu, 21 Nov 2024 10:53:50 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:11 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-20-mizhang@google.com> Subject: [RFC PATCH 19/22] KVM: x86: Allow host and guest access to IA32_[AM]PERF From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Implement MSR read/write handlers for IA32_APERF and IA32_MPERF to support both host and guest access: - Host userspace access via KVM_[GS]ET_MSRS only reads/writes the snapshot values in vcpu->arch.aperfmperf - Guest writes update both the hardware MSRs (via set_guest_[am]perf) and the snapshots - For host-initiated writes of IA32_MPERF, record the current TSC to establish a new baseline for background cycle accumulation - Guest reads don't reach these handlers as they access the MSRs directly Add both MSRs to msrs_to_save_base[] to ensure they are properly serialized during vCPU state save/restore operations. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index cd1f1ae86f83f..4394ecb291401 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -334,6 +334,7 @@ static const u32 msrs_to_save_base[] = { MSR_IA32_UMWAIT_CONTROL, MSR_IA32_XFD, MSR_IA32_XFD_ERR, + MSR_IA32_APERF, MSR_IA32_MPERF, }; static const u32 msrs_to_save_pmu[] = { @@ -4151,6 +4152,26 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 1; vcpu->arch.msr_misc_features_enables = data; break; + case MSR_IA32_APERF: + if ((data || !msr_info->host_initiated) && + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) + return 1; + + vcpu->arch.aperfmperf.guest_aperf = data; + if (unlikely(!msr_info->host_initiated)) + set_guest_aperf(data); + break; + case MSR_IA32_MPERF: + if ((data || !msr_info->host_initiated) && + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) + return 1; + + vcpu->arch.aperfmperf.guest_mperf = data; + if (likely(msr_info->host_initiated)) + vcpu->arch.aperfmperf.host_tsc = rdtsc(); + else + set_guest_mperf(data); + break; #ifdef CONFIG_X86_64 case MSR_IA32_XFD: if (!msr_info->host_initiated && @@ -4524,6 +4545,22 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) msr_info->data = vcpu->arch.guest_fpu.xfd_err; break; #endif + case MSR_IA32_APERF: + /* Guest read access should never reach here. */ + if (!msr_info->host_initiated) + return 1; + + msr_info->data = vcpu->arch.aperfmperf.guest_aperf; + break; + case MSR_IA32_MPERF: + /* Guest read access should never reach here. */ + if (!msr_info->host_initiated) + return 1; + + if (vcpu->arch.mp_state != KVM_MP_STATE_HALTED) + kvm_accumulate_background_guest_mperf(vcpu); + msr_info->data = vcpu->arch.aperfmperf.guest_mperf; + break; default: if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) return kvm_pmu_get_msr(vcpu, msr_info); @@ -7535,6 +7572,11 @@ static void kvm_probe_msr_to_save(u32 msr_index) if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) return; 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Allow direct guest rdmsr access to IA32_APERF and IA32_MPERF while continuing to intercept guest wrmsr. Direct read access reduces overhead for guests that poll these MSRs frequently (e.g. every scheduler tick), while write interception remains necessary to maintain proper host offset tracking. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/svm/svm.c | 7 +++++++ arch/x86/kvm/svm/svm.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9df3e1e5ae81a..332947e0e9670 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -142,6 +142,8 @@ static const struct svm_direct_access_msrs { { .index = X2APIC_MSR(APIC_TMICT), .always = false }, { .index = X2APIC_MSR(APIC_TMCCT), .always = false }, { .index = X2APIC_MSR(APIC_TDCR), .always = false }, + { .index = MSR_IA32_APERF, .always = false }, + { .index = MSR_IA32_MPERF, .always = false }, { .index = MSR_INVALID, .always = false }, }; @@ -1231,6 +1233,11 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); } + + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_APERF, + guest_can_use(vcpu, X86_FEATURE_APERFMPERF), 0); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_MPERF, + guest_can_use(vcpu, X86_FEATURE_APERFMPERF), 0); } static void init_vmcb(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 43fa6a16eb191..5ae5a13b9771a 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -44,7 +44,7 @@ static inline struct page *__sme_pa_to_page(unsigned long pa) #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 -#define MAX_DIRECT_ACCESS_MSRS 48 +#define MAX_DIRECT_ACCESS_MSRS 50 #define MSRPM_OFFSETS 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled;