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Mon, 25 Nov 2024 00:34:30 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825f98b3a4sm10013421f8f.0.2024.11.25.00.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2024 00:34:30 -0800 (PST) From: Neil Armstrong Date: Mon, 25 Nov 2024 09:34:26 +0100 Subject: [PATCH 1/4] clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock MIME-Version: 1.0 Message-Id: <20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org> References: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> In-Reply-To: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2239; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=g0FjaoqpfjI6frI33mzwzYPVRURIl7UqnNT+yHjBoio=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRDaT+K3wVPO02SpP+t0Pd6n+o9pk7xcXINgm2VIl 7tXrAtSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0Q2kwAKCRB33NvayMhJ0XTqD/ 45IA0o/uj35dAGlA3Jn6F2kdMMIZYReGVQX9r1hs/wo2Z4CHLQ5wIinhQ4rzE01FVZNzrFTF4TnqBO MUaOhVePDzrElio2aWBxKAlnYHb+xkTHlqVI1S7wCni7fGL/yFQKQwGCc+c5gn4twTQ1CelyqiA+Dl P3rzJnp6Cg505FL4nmTBTWPTbM0e+LXuyuzhDEtjCdmuan+1io8FV1m/oNtf8uwmT5ahicLPQwHkJB D/1fl7qKYwuyZ8ZGh/6DZLZA9AOzUjHlvdwOf8o8y57lCSSDF5YJU3RIAPiem2w5+hPjKcpUPToVqj k35RBf0LLeiTiRSw1aqhI9TbJ2qCKo84N+766t2mzdSMvxLAz5ZF2cHdk6inIdZe8QCBXJ/9EEXBzi ezhaWB1xqD75kbsNyOrhDV/JDnHcRSeccbL/vu6aQ7uyZVB+v693IHe/jod/5zgpd+61yFaWtnsLUf C9gR1pXVk66mXUK4kNWJkihh3DliPBJ5icaK0GnKZQK09q4OE2Lg1ApJtNkaDEe1f6BrOk6Z86sPA5 1FcZFlXCYavDGjL9zWagSNSdWjQrprGZfRX6thpv/cBG9g+tjSLLnnciP7HwzCFXQ8cciEyAZYADs3 ssnLyYj/v5m6PPswy3YjOfld6ieb+C7MmP5ljIoctWLZCLeqbYGI7x31GW/A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The PCIe PIPE clock requires a special setup function to mux & enable the clock from the PCIe PHY before the PHY has enabled the clock. Import the clk_phy_mux_enable() from the Linux driver to use the same implementation regarding the PIPE clock. Signed-off-by: Neil Armstrong --- drivers/clk/qcom/clock-qcom.c | 19 +++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 25ca67e537d112dda236837d3d3984f9b666365e..7687bbe6a23b436e4ddf3b29d1c910062961126d 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, clk_bcr_update(base + cmd_rcgr); } +#define PHY_MUX_MASK GENMASK(1, 0) +#define PHY_MUX_PHY_SRC 0 +#define PHY_MUX_REF_SRC 2 + +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + cmd_rcgr); + cfg &= ~(PHY_MUX_MASK); + if (enabled) + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC); + else + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC); + + writel(cfg, base + cmd_rcgr); +} + const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) { if (!f) diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 78d9b1d81ece1b3dd96b7bd0ab1a69fa016523b6..ff336dea39cf5cbe35f37f93669285897ba185a4 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -6,6 +6,7 @@ #define _CLOCK_QCOM_H #include +#include #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) @@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) { From patchwork Mon Nov 25 08:34:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 845302 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1055428wru; Mon, 25 Nov 2024 00:34:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUSg3DuyVQm5wLXl3Sx6jWzPt/99KeEwN0GBvbDYL2V1rEZR6ndVcys/F1txok58VALbb1nlQ==@linaro.org X-Google-Smtp-Source: AGHT+IFpdXjHyFuW3gxWumouQ3/rMPvYy4+ISITJ6EjqCjqwnxhv8Hpb4Xy80KUBMFUwO8ITxn37 X-Received: by 2002:a17:906:3096:b0:aa5:1d56:9c60 with SMTP id a640c23a62f3a-aa51d569ca6mr773564866b.20.1732523691507; Mon, 25 Nov 2024 00:34:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732523691; cv=none; d=google.com; s=arc-20240605; b=QKCwIq/Xz3cocE9/xuLPnMS7B+u3T1nfUWO5L+3Pubh5+OmxeKJ7WCGk7l9rttMGQE y4PMjmfSBH/ngaFEYzUgRDLgFHPCWj0NTrA2xH0s6EeyiZ4PCnzY7ryTx0tyzQ7v3CZR xqZQ86BnkbiX06xqXHxmLvPKchkwhFuZE9TRJuGH98tsKbMfKTA0GQ1lUk8bOftvk8v4 C/0SvpKtJqOmF2r86wLberY09dH9TQfUZwaftdpVJ+28FAbSODctgTAUND6oXGbTGpv9 cAZVsg6lDk5rtfKjFBA8c/zSxlhQtiCfjNfPXfycUY/42GUm2b3Ro6nCR3awQl5951fT BRrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=AEMFBLDOfj1lrbfwaS3o11j6YNe04Vv2+BAtjKZcbao=; fh=jbW+N6w391qRGzlHXkUUZhbPnocPJVwdef9WZQSvKHk=; b=L2btjEMKrL/2+karld+qHl2D+w9V43w5IyGOPpuRX5Z5NEnH8L6CVbM8/bXtkfrVIA 8wAQbUefBN+0CT04ho1yrwNpp7AIQY73VuF6RrVplPn9Tdiv1AaiflMoJIf7BwdAlp7g VQw8IkF0iAo0ZsfjgB9aIGzgl4HzypYgCODIgu68AqNz9DXfgS6VY8Qrc2Rr5JawAfr4 6hZ8L3PWVg6hKOJL6vSQZw4aqsi7EN09k/0a8fhVNrRKojZv/z2jR0VuUVRHsRmX0qJi 0LrRBfS+3nkwaJCSMpzMrv/qKT/bSs1lAPoYwXTA9DasFEys7b9lrSsXJGJaNel653K0 ZVuA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hRg8YQ9l; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the PCIe clocks for the SM8550 GCC. Signed-off-by: Neil Armstrong --- drivers/clk/qcom/clock-sm8550.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index c0249925cc7eb165faefea35ef29c5ff59faf07f..62b5a409e8e08243ad53a0bc58af1c7754a3d950 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -57,6 +57,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8550_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -84,6 +94,24 @@ static ulong sm8550_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -182,6 +210,14 @@ static int sm8550_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id); From patchwork Mon Nov 25 08:34:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 845303 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1055476wru; Mon, 25 Nov 2024 00:35:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUV0nkcka2nHpWEv/+OjYvtSu3Yenq8R30VyE9G8zEniDHHza5n0bqpUMZAILLV16E3kBFHMA==@linaro.org X-Google-Smtp-Source: AGHT+IGEgfL51vXIzjJwRVTmuVrVqM8Sb55++KDlhiHolGQdHqvscvX1uX64d05a4Z8Lsj0LNySQ X-Received: by 2002:a17:907:3689:b0:a99:fcbe:c96b with SMTP id a640c23a62f3a-aa4efea7a9emr1390682466b.25.1732523700582; Mon, 25 Nov 2024 00:35:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732523700; cv=none; d=google.com; s=arc-20240605; b=RUMkF3xFNk/lTXpM1lUeaxkuh3agHNe7ggqeAEHokB9nCEosbUarSJwZ7kgSqdT7HA RI0A+lluw/a9PkS/nRqHmXlBoEQ/vZhSLgWNTy2QlbN9wSoDbA3DSLyf3z2/XMzYJ2qQ R4uzbRKXl5d4ZK3bEVKPM1IG/wOOaDpn26E+HHWezoIf2eZVoxdIlieRM0Wsg+UNAxgv LNDemtyFXJVlI91CoBw5TLFzfQjH/DpOKN/GAO5J1Pek7ZGV0Net8FI632AYFW5dRK0n qBdGyK2DNHtSIUCWquwU0E+sxJejzZTGGgbPz6ZVrWYdK1ijuyFHElRbpCvB1VilBn1I VP9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=lKHBUoi7i9sL4zy2D4QZgFc+IVVVdBZyPOxJkJtUxdo=; fh=D8DrZP+qVW8UlbKbxlLcqkS32YszGWt91ym328rAsNs=; b=NknbGolLGAxHplRv1dxXzTCbsLMxkA8yEkdRD8UBFw1xlJPT9AhvRgrpyLC3WT+eeg 0cACm2IwsJCkHHiSYiL+GshOm7Xh2hLC1OljsK1dYFTczuLAsF93OM4ngba/8I3Zs3wr VucGhqP8H75qmgzEYOebs7EOUK4blqQIhbnBohMRzyGWMJ/nG0/ka+ASVM2fxTHPZhme 5New9kWhQSRQrQtUiSLaPdf87CtIwsT6rrL3KlilGZO+EB2FYEQTSdv0MjZqecRcAwiO AJAQ1jL03lR/K/yMQ1jzHzI7aHnUPOiOvgWts3BDvaY+wKuh0n24gVriS3iDbYcIrFYI EdQw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k5O5tje6; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the PCIe clocks for the SM8650 GCC. Signed-off-by: Neil Armstrong --- drivers/clk/qcom/clock-sm8650.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 0ce83e9b24375820016397c3c5491dd9d44edb4b..9baaecb571f6c575c0e7c48d66214c1331b6642f 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8650_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -81,6 +91,24 @@ static ulong sm8650_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -179,6 +207,14 @@ static int sm8650_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id); From patchwork Mon Nov 25 08:34:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 845304 Delivered-To: patch@linaro.org Received: by 2002:a5d:688e:0:b0:382:43a8:7b94 with SMTP id h14csp1055522wru; Mon, 25 Nov 2024 00:35:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUSA1CdPePB5HjWmpl83dkQMox5xIjiuyQCGYt/sPSgHmGhEcqLz9uyWajA6OYbIWGEVoCcnw==@linaro.org X-Google-Smtp-Source: AGHT+IHg0xBF4H41djwwKzwMqaxMw+LISTy4KyQdI9AKSkgeQx3Cq7eTZQW6NgcIQuVbuJta+qBQ X-Received: by 2002:a17:906:3111:b0:aa5:2f8a:b94f with SMTP id a640c23a62f3a-aa52f8ac9c8mr646465766b.54.1732523710139; Mon, 25 Nov 2024 00:35:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1732523710; cv=none; d=google.com; s=arc-20240605; b=b5FeMGturYyLElQJ45UXocZdrxSBMBen3ztZ0x+ncg0aAsP8EjBBMyt5hME53Zj6sN rQtDxDGbuIlofVBvoBN/Br/9LCoCaZ0GxvVp3kJPb+DDofbhca6shw4/+GYSZOasW/Xf Oym+bvla/QFd8UfxK8h18k3lN23hVn2K3L1Be0tUHAdV9Czw2nnRPZKvSwOXj8nJO/Fy mKeYyET3IjpSOFyOcGQvExxmtiPRI7CYYLVYhhNiWkx4lJuizgu3/3XS2v0lwmnBui9W AO5hSWcdl/wEMROILEQ1pAeTGMFsjpVZVkPXwFAZbxN47rFXaUV/5gv1LQMbFVXWyaU2 wYiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=03aTthycV3OdJLwgk9FJKu0Kw873OtZC5APpwUnuCII=; fh=orpPv6lcgZzfeUsrfQ/MEgWzEe4pK8lXQvm4kgTAzmU=; b=S0ziFqlbBBisaT5KyjVTeUkjzklmVsjLwjYredOn8BKEJSaImXPR9bAYLyK49M50PS yKfkHKZyA9u80zzuOZfj5IvDe+nLENRQFTDoC/qvfqr4/M7J+BrR1K8EjC6lh7JAgshM /+Vk/dxRAV9ZadZYGxf8MgDZU8uTWvOa6a9KIpsHfyRERbcvopHKyAog4V7Bxuw11s1O zdth1s2C1rHkhLXNDmgwPfNr5qfcq9P88DN/hTci77m/qAmlbX1qZ/glUz7KLu1GSJ1r jRjBHFUAGWNoDFeezx4qS0Hx1OMCtC1ZKw0tf18LeGzLGFR5lDgQFEK/+OdebQuau3NN NwtQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nZQWnqCk; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Mon, 25 Nov 2024 00:34:32 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825f98b3a4sm10013421f8f.0.2024.11.25.00.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2024 00:34:32 -0800 (PST) From: Neil Armstrong Date: Mon, 25 Nov 2024 09:34:29 +0100 Subject: [PATCH 4/4] clk: qcom: x1e80100: add support for PCIe clocks MIME-Version: 1.0 Message-Id: <20241125-topic-pcie-clk-v1-4-4315d1e4e164@linaro.org> References: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> In-Reply-To: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3997; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=inxIrxV+QhEnyAQS3kecKBNJRShDukKNPdrpi3g86RQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRDaUYyA9HHppQtnEywInIyebQXpJvscdFmBLxmRv B1XLXu+JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0Q2lAAKCRB33NvayMhJ0QBHEA ClCeJOyDk6KwO+vPn5RGU/DCKZxJ7RTkbj5545tzGYTdKSZTOvSgtOubHvnnGiL8g+x7rUKC/DKxsh JfgEDXaeQfVHymzFABp9gls/gK60Nx5AZSRwXH1pemW8SxekNYr4Gdzx/OaU1stDFbx7NeDt2R6JNl 1KdyxsmCQ5kmOCmQV4OuXMkBUL1FitJR4ogV4j/VkV0lPaxQp3sY907wTtqxJUUWboAqRN0NhkUkfH wJ0op2PJ/3hUxASkTupsZf0KBK5cQYID+EmDZB/WXjLFOz5hjDfZ6SDozcc7b1VpvJXwk/R9++7JyV xJbFPlPHOX4mow/Le1K9Zl2f2kx64Oe20dfBj77U5K+yQz55FDWSHiorUSlN9vL3tju422waw6fRKv 8osXoggYtLMlPZve8UCS5UVwB1YKK42xKdJVev/nh9RlcwlZYHx8qaxxtymagY4p559jxrcYP8nkdB uyOdiyfW77/9I0xxXsoFSE5AE5dsbGgGzJ0m3WSS84/vCKQZW+NWQ2k4fZscdBGg1GdyXUQU0voUQd vDiJYVx/mHUwCYwG79Yc8U4xGoD9GfTKhVp9vg2ayOH+gNw4pMYui0HzzfA+5BWt1w36FVVsvXc0BU D6xoxm07giJAvjIk5MUtgGd7l2yfuEBorvD1T+LBF102Td2ZXU6+jNYmfKJQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add the PCIe clocks for the x1e80100 GCC. Signed-off-by: Neil Armstrong --- drivers/clk/qcom/clock-x1e80100.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c index 6bcd705f6c8d40dc477c55fe1f594df70e1187ad..bd9c6ed1c8a0b4ca0b5164d849efa5c0755c1e2e 100644 --- a/drivers/clk/qcom/clock-x1e80100.c +++ b/drivers/clk/qcom/clock-x1e80100.c @@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong x1e80100_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -78,6 +88,24 @@ static ulong x1e80100_set_rate(struct clk *clk, ulong rate) case GCC_USB30_PRIM_MOCK_UTMI_CLK: clk_rcg_set_rate(priv->base, 0x39044, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_4_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b080, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_4_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b064, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_6A_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3108c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_6A_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x31070, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -86,6 +114,24 @@ static ulong x1e80100_set_rate(struct clk *clk, ulong rate) static const struct gate_clk x1e80100_clks[] = { GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK, 0x52000, BIT(20)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK, 0x52028, BIT(22)), + GATE_CLK(GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK, 0x52028, BIT(12)), + GATE_CLK(GCC_CNOC_PCIE_NORTH_SF_AXI_CLK, 0x52008, BIT(6)), + GATE_CLK(GCC_PCIE_4_AUX_CLK, 0x52008, BIT(3)), + GATE_CLK(GCC_PCIE_4_CFG_AHB_CLK, 0x52008, BIT(2)), + GATE_CLK(GCC_PCIE_4_MSTR_AXI_CLK, 0x52008, BIT(1)), + GATE_CLK(GCC_PCIE_4_PHY_RCHNG_CLK, 0x52000, BIT(22)), + GATE_CLK(GCC_PCIE_4_PIPE_CLK, 0x52008, BIT(4)), + GATE_CLK(GCC_PCIE_4_SLV_AXI_CLK, 0x52008, BIT(0)), + GATE_CLK(GCC_PCIE_4_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)), + GATE_CLK(GCC_PCIE_6A_AUX_CLK, 0x52018, BIT(24)), + GATE_CLK(GCC_PCIE_6A_CFG_AHB_CLK, 0x52018, BIT(23)), + GATE_CLK(GCC_PCIE_6A_MSTR_AXI_CLK, 0x52018, BIT(22)), + GATE_CLK(GCC_PCIE_6A_PHY_RCHNG_CLK, 0x52018, BIT(27)), + GATE_CLK(GCC_PCIE_6A_PIPE_CLK, 0x52018, BIT(26)), + GATE_CLK(GCC_PCIE_6A_SLV_AXI_CLK, 0x52018, BIT(21)), + GATE_CLK(GCC_PCIE_6A_SLV_Q2A_AXI_CLK, 0x52018, BIT(20)), GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)), GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)), GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)), @@ -118,6 +164,14 @@ static int x1e80100_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_4_PIPE_CLK: + // GCC_PCIE_4_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b07c, true); + break; + case GCC_PCIE_6A_PIPE_CLK: + // GCC_PCIE_6A_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x31088, true); + break; } qcom_gate_clk_en(priv, clk->id);