From patchwork Wed Dec 11 12:00:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 181200 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp428421ile; Wed, 11 Dec 2019 04:00:49 -0800 (PST) X-Google-Smtp-Source: APXvYqx4Ooq1HeW7o3+PrU06TFhr30JuWy4GbfJvsjgMNzltmLDCx8mtBljDYNVEZniIHNoaKZqa X-Received: by 2002:a9d:2028:: with SMTP id n37mr2066008ota.127.1576065649274; Wed, 11 Dec 2019 04:00:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576065649; cv=none; d=google.com; s=arc-20160816; b=XByfaZgRc6R30AxCmRyV9G9U2dvtAn/c1s+L42s2QhALaXYiLeNUEp8M1ssxmjXxI+ cu9TJxFi2ywDDJt+z4tzGCiCDEFG4UUyBcNS+9o6Rj6nDTfhqPNhJ+if6sUtgd7WWhr3 b6rDUQ6T811mqJk4pKeXn5iIeKUT9MQz8eN6RkJgso5XUX4kQU1WnU33p4AoEwLdIB/j ElY+NYyPYoqBIpHNXutzBSDn64PYqNFCQc1K8VQE0BXuOYffu1mIF6Bk4RsAubeAin7G 5A9VLAwd6lWCSNxjvg1wWiPdVDSKOS5EH5qWg+wD6nqI9x7/8UF2hMuHqxZialsfhCnw E3dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:date:message-id:subject:from:to :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature; bh=rw6qGjp+1XQ7LX6ulUeN2gQGh932mwffBPnyWzMw6Qc=; b=kwmpKvtG6nqASReNlOzxVssS3MxWns94Jkok7kom6XdGoekoJHBqoZhR1jXLnVYenw A8RDDE7jn6BKDNq6BfmEbCln0nBerZyyV9hhTONGmr1yr3oi3ig6pw9OX8V4LvN3y5yB rXQrPCTisbnAfqCuZkRQqt9HmuyCnKLtpw4o6OgnS7NM5t5VwlUKQiKf2N5N1xE4tMOo KstybYQEizdk5c/Rt2vhJ3/nMhU/MYDZSaAtmIwmPj+qD+kjl46v98y2eErsgsw7j4uU 5ZS+YgEC56qDRF4kqAt+kC6hKh0GbFnromPfCk6C52NOOFefJi9ZaMAF2ZgdnC4akne2 CNgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=kVGGWVmW; spf=pass (google.com: domain of gcc-patches-return-515689-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-515689-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id a26si928456oto.199.2019.12.11.04.00.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Dec 2019 04:00:49 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-515689-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=kVGGWVmW; spf=pass (google.com: domain of gcc-patches-return-515689-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-515689-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=MhtJGB6GK7Q6m2m+VlbFcinv+oLNQLJFlDerk1tipZjlzvQlQy qgdzjujyxFYVppR2KpbEA6hd/DJB8V+7ptBlWsW833ITxT6plIeKrLw9WQMKecv4 TJl4XIxa87XJRgN9f4G+UC5mCEY9mprHRR2zw+9qw5l9Yy5dOez2RhpZE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=q4a2FUIZWewJkSuZvR1DvY4Wyys=; b=kVGGWVmWSDEjGxWKe5Bj kVe4z2jhNHmWztgnQpQo+i6uvEAgjSYTHco49HUEDBV0/cXrzKq4SuTTpwBmU41Q Cux2wYtqmJYQlJLV2tNLfhMMKGy69GeEHRohrqUSHTrfmzmXPu40Exj3y86UXggX gWfozmy0eyruuCDa8KST2U4= Received: (qmail 41254 invoked by alias); 11 Dec 2019 12:00:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 41242 invoked by uid 89); 11 Dec 2019 12:00:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=housekeeping, issuing, 13707, implies X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 11 Dec 2019 12:00:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 070F81FB; Wed, 11 Dec 2019 04:00:33 -0800 (PST) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.78.81]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A00823F6CF; Wed, 11 Dec 2019 04:00:32 -0800 (PST) To: "gcc-patches@gcc.gnu.org" From: "Richard Earnshaw (lists)" Subject: arm: Fix an incorrect warning when -mcpu=cortex-a55 is used with -mfloat-abi=soft Message-ID: Date: Wed, 11 Dec 2019 12:00:31 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 When a CPU such as cortex-a55 is used with the soft-float ABI variant, the compiler is incorrectly issuing a warning about a mismatch between the architecture (generated internally) and the CPU. This is not expected or intended. The problem stems from the fact that we generate (correctly) an architecture for a soft-float compilation, but then try to compare it against the one recorded for the CPU. Normally we strip out the floating point information before doing that comparison, but we currently only do that for the features that can be affected by the -mfpu option. For a soft-float environment we also need to strip out any bits that depend on having floating-point present. So this patch implements that and does a bit of housekeeping at the same time: - in arm-cpus.in it is not necessary for a CPU to specify both +dotprod and +simd in its architecture specification, since +dotprod implies +simd. - I've refactored the ALL_SIMD fgroup in arm-cpus.in to create a new subgroup ALL_SIMD_EXTERNAL and containing the bits that were previously added directly to ALL_SIMD. Similarly, I've added an ALL_FPU_EXTERNAL subgroup. - in arm.c rename fpu_bitlist and all_fpubits to fpu_bitlist_internal and all_fpubits_internal for consistency with the fgroup bits which they contain. * config/arm/arm-cpus.in (ALL_SIMD_EXTERNAL): New fgroup. (ALL_SIMD): Use it. (ALL_FPU_EXTERNAL): New fgroup. (ALL_FP): Use it. (cortex-a55, cortex-a75, cortex-a76, cortex-a76ae): Remove redundant +simd from architecture specification. (cortex-a77, neoverse-n1, cortex-a75.cortex-a55): Likewise. * config/arm/arm.c (isa_all_fpubits, fpu_bitlist): Rename to ... (isa_all_fpubits_internal, fpu_bitlist_internal): ... these. (isa_all_fpbits): New bitmap. (arm_option_override): Initialize it. (arm_configure_build_target): If the target isa does not have any FP enabled, do not warn about mismatches in FP-related feature bits. Committed to trunk. diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 44e6cc6bdb6..7090775aa7e 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -213,15 +213,18 @@ define fgroup ALL_CRYPTO crypto # strip off 32 D-registers, but does not remove support for # double-precision FP. define fgroup ALL_SIMD_INTERNAL fp_d32 neon ALL_CRYPTO -define fgroup ALL_SIMD ALL_SIMD_INTERNAL dotprod fp16fml +define fgroup ALL_SIMD_EXTERNAL dotprod fp16fml +define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL # List of all FPU bits to strip out if -mfpu is used to override the # default. fp16 is deliberately missing from this list. define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL - # Similarly, but including fp16 and other extensions that aren't part of # -mfpu support. -define fgroup ALL_FP fp16 ALL_FPU_INTERNAL +define fgroup ALL_FPU_EXTERNAL fp16 + +# Everything related to the FPU extensions (FP or SIMD). +define fgroup ALL_FP ALL_FPU_EXTERNAL ALL_FPU_INTERNAL ALL_SIMD define fgroup ARMv4 armv4 notm define fgroup ARMv4t ARMv4 thumb @@ -1301,7 +1304,7 @@ begin cpu cortex-a55 cname cortexa55 tune for cortex-a53 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO option nofp remove ALL_FP costs cortex_a53 @@ -1313,7 +1316,7 @@ begin cpu cortex-a75 cname cortexa75 tune for cortex-a57 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO costs cortex_a73 vendor 41 @@ -1324,7 +1327,7 @@ begin cpu cortex-a76 cname cortexa76 tune for cortex-a57 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO costs cortex_a57 vendor 41 @@ -1335,7 +1338,7 @@ begin cpu cortex-a76ae cname cortexa76ae tune for cortex-a57 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO costs cortex_a57 vendor 41 @@ -1346,7 +1349,7 @@ begin cpu cortex-a77 cname cortexa77 tune for cortex-a57 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO costs cortex_a57 vendor 41 @@ -1358,7 +1361,7 @@ begin cpu neoverse-n1 alias !ares tune for cortex-a57 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO costs cortex_a57 vendor 41 @@ -1370,7 +1373,7 @@ begin cpu cortex-a75.cortex-a55 cname cortexa75cortexa55 tune for cortex-a53 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO costs cortex_a73 end cpu cortex-a75.cortex-a55 @@ -1379,7 +1382,7 @@ begin cpu cortex-a76.cortex-a55 cname cortexa76cortexa55 tune for cortex-a53 tune flags LDSCHED - architecture armv8.2-a+fp16+dotprod+simd + architecture armv8.2-a+fp16+dotprod option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a76.cortex-a55 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6eb2afbd85f..983852cc4e3 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3109,7 +3109,8 @@ arm_option_override_internal (struct gcc_options *opts, #endif } -static sbitmap isa_all_fpubits; +static sbitmap isa_all_fpubits_internal; +static sbitmap isa_all_fpbits; static sbitmap isa_quirkbits; /* Configure a build target TARGET from the user-specified options OPTS and @@ -3176,7 +3177,12 @@ arm_configure_build_target (struct arm_build_target *target, /* Ignore any bits that are quirk bits. */ bitmap_and_compl (isa_delta, isa_delta, isa_quirkbits); /* Ignore (for now) any bits that might be set by -mfpu. */ - bitmap_and_compl (isa_delta, isa_delta, isa_all_fpubits); + bitmap_and_compl (isa_delta, isa_delta, isa_all_fpubits_internal); + + /* And if the target ISA lacks floating point, ignore any + extensions that depend on that. */ + if (!bitmap_bit_p (target->isa, isa_bit_vfpv2)) + bitmap_and_compl (isa_delta, isa_delta, isa_all_fpbits); if (!bitmap_empty_p (isa_delta)) { @@ -3335,7 +3341,7 @@ arm_configure_build_target (struct arm_build_target *target, auto_sbitmap fpu_bits (isa_num_bits); arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits); - bitmap_and_compl (target->isa, target->isa, isa_all_fpubits); + bitmap_and_compl (target->isa, target->isa, isa_all_fpubits_internal); bitmap_ior (target->isa, target->isa, fpu_bits); } @@ -3361,16 +3367,20 @@ arm_configure_build_target (struct arm_build_target *target, static void arm_option_override (void) { - static const enum isa_feature fpu_bitlist[] + static const enum isa_feature fpu_bitlist_internal[] = { ISA_ALL_FPU_INTERNAL, isa_nobit }; + static const enum isa_feature fp_bitlist[] + = { ISA_ALL_FP, isa_nobit }; static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit}; cl_target_option opts; isa_quirkbits = sbitmap_alloc (isa_num_bits); arm_initialize_isa (isa_quirkbits, quirk_bitlist); - isa_all_fpubits = sbitmap_alloc (isa_num_bits); - arm_initialize_isa (isa_all_fpubits, fpu_bitlist); + isa_all_fpubits_internal = sbitmap_alloc (isa_num_bits); + isa_all_fpbits = sbitmap_alloc (isa_num_bits); + arm_initialize_isa (isa_all_fpubits_internal, fpu_bitlist_internal); + arm_initialize_isa (isa_all_fpbits, fp_bitlist); arm_active_target.isa = sbitmap_alloc (isa_num_bits); @@ -27258,7 +27268,7 @@ arm_print_asm_arch_directives () don't print anything if all the bits are part of the FPU specification. */ if (bitmap_subset_p (opt_bits, arm_active_target.isa) - && !bitmap_subset_p (opt_bits, isa_all_fpubits)) + && !bitmap_subset_p (opt_bits, isa_all_fpubits_internal)) asm_fprintf (asm_out_file, "\t.arch_extension %s\n", opt->name); } } @@ -31771,7 +31781,7 @@ arm_identify_fpu_from_isa (sbitmap isa) auto_sbitmap fpubits (isa_num_bits); auto_sbitmap cand_fpubits (isa_num_bits); - bitmap_and (fpubits, isa, isa_all_fpubits); + bitmap_and (fpubits, isa, isa_all_fpubits_internal); /* If there are no ISA feature bits relating to the FPU, we must be doing soft-float. */ @@ -31831,7 +31841,7 @@ arm_declare_function_name (FILE *stream, const char *name, tree decl) { arm_initialize_isa (opt_bits, opt->isa_bits); if (bitmap_subset_p (opt_bits, arm_active_target.isa) - && !bitmap_subset_p (opt_bits, isa_all_fpubits)) + && !bitmap_subset_p (opt_bits, isa_all_fpubits_internal)) asm_fprintf (asm_out_file, "\t.arch_extension %s\n", opt->name); } @@ -32504,28 +32514,28 @@ arm_test_cpu_arch_data (void) static void arm_test_fpu_data (void) { - auto_sbitmap isa_all_fpubits (isa_num_bits); + auto_sbitmap isa_all_fpubits_internal (isa_num_bits); auto_sbitmap fpubits (isa_num_bits); auto_sbitmap tmpset (isa_num_bits); - static const enum isa_feature fpu_bitlist[] + static const enum isa_feature fpu_bitlist_internal[] = { ISA_ALL_FPU_INTERNAL, isa_nobit }; - arm_initialize_isa (isa_all_fpubits, fpu_bitlist); + arm_initialize_isa (isa_all_fpubits_internal, fpu_bitlist_internal); for (unsigned int i = 0; i < TARGET_FPU_auto; i++) { arm_initialize_isa (fpubits, all_fpus[i].isa_bits); - bitmap_and_compl (tmpset, isa_all_fpubits, fpubits); - bitmap_clear (isa_all_fpubits); - bitmap_copy (isa_all_fpubits, tmpset); + bitmap_and_compl (tmpset, isa_all_fpubits_internal, fpubits); + bitmap_clear (isa_all_fpubits_internal); + bitmap_copy (isa_all_fpubits_internal, tmpset); } - if (!bitmap_empty_p (isa_all_fpubits)) + if (!bitmap_empty_p (isa_all_fpubits_internal)) { fprintf (stderr, "Error: found feature bits in the ALL_FPU_INTERAL" " group that are not defined by any FPU.\n" " Check your arm-cpus.in.\n"); - ASSERT_TRUE (bitmap_empty_p (isa_all_fpubits)); + ASSERT_TRUE (bitmap_empty_p (isa_all_fpubits_internal)); } }