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Mon, 25 Nov 2024 17:45:39 GMT Received: from 4215f72c9660.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 09:45:35 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Odelu Kukatla , Mike Tipton , Sibi Sankar , , , , Subject: [PATCH V6 2/4] interconnect: qcom: osm-l3: Add generic compatible for epss-l3-perf Date: Mon, 25 Nov 2024 17:45:09 +0000 Message-ID: <20241125174511.45-3-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241125174511.45-1-quic_rlaggysh@quicinc.com> References: <20241125174511.45-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5jvT9TmnsF1hF_Mo7FKYQrgE-E3ZdQz1 X-Proofpoint-ORIG-GUID: 5jvT9TmnsF1hF_Mo7FKYQrgE-E3ZdQz1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 spamscore=0 mlxscore=0 impostorscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250147 The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. Add new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based L3 scaling. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/osm-l3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index a9405b7d251b..7937e7c16c71 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -318,6 +318,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, + { .compatible = "qcom,epss-l3-perf", .data = &epss_l3_perf_state }, { .compatible = "qcom,osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, From patchwork Mon Nov 25 17:45:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 845515 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82AE01BD4FD; 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Mon, 25 Nov 2024 17:45:48 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4APHjlam032692 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 17:45:47 GMT Received: from 4215f72c9660.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 09:45:43 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Odelu Kukatla , Mike Tipton , Sibi Sankar , , , , Subject: [PATCH V6 4/4] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Date: Mon, 25 Nov 2024 17:45:11 +0000 Message-ID: <20241125174511.45-5-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241125174511.45-1-quic_rlaggysh@quicinc.com> References: <20241125174511.45-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tiVJRiTO2Yo-d2Mj8qI75TO8W2jBoYWi X-Proofpoint-ORIG-GUID: tiVJRiTO2Yo-d2Mj8qI75TO8W2jBoYWi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 spamscore=0 mlxscore=0 impostorscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250147 Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P SoCs. Update the generic compatible for SM8250 and SC7280 SoCs to "qcom,epss-l3-perf" as they use PERF_STATE register for L3 scaling. Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9f315a51a7c1..0c2bd15f9ef0 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,sm8250-epss-l3", + "qcom,epss-l3-perf"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sa8775p-cpufreq-epss", "qcom,cpufreq-epss"; @@ -4295,6 +4305,15 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,sm8250-epss-l3", + "qcom,epss-l3-perf"; + reg = <0x0 0x18592000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + remoteproc_gpdsp0: remoteproc@20c00000 { compatible = "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 55db1c83ef55..544c6d725764 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -6125,7 +6125,7 @@ rpmhcc: clock-controller { }; epss_l3: interconnect@18590000 { - compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; + compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3-perf"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 48318ed1ce98..f4a223bfe748 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -6230,7 +6230,7 @@ apps_bcm_voter: bcm-voter { }; epss_l3: interconnect@18590000 { - compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; + compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3-perf"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;