From patchwork Tue Nov 26 09:20:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 845716 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D718018E362 for ; Tue, 26 Nov 2024 09:21:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; cv=none; b=KQeLo1RRKN8Gk+N1peMSZni3f49M6x4g3ymOXhuUgS3To/kMLpehBbdEQQ+jEw/Q/J7f6/CdvfR46j0PxGXwjjfGzA5P+gRrkZqDUfxoVW+oqHEWC2oMn+yois2A2DVTqee1tYtM5trSE7gKDd/waa/M6vA8vDJUgsNKtfqvJ4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; c=relaxed/simple; bh=EqyCCrGqEJwg3+iLhcuJrpOwueTe8BY2KShqIIlG8ZY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F8HmXr6mAT1vYhop+IQibB/vgjZK45fzwTB9iAsUxovKzbgjaAfgTdiFEkfwzttBuiH/IwnVq18VYNIIVnC7LJjZJUWO16lpoDYKw9OFiCAWHMEm6daCbP245e8X2QWD2D2dvl8jbN+5xNxIGr9iaWHE8UlO2y/056aBFkXtNzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=WpmWgXyr; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="WpmWgXyr" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-434a752140eso2727615e9.3 for ; Tue, 26 Nov 2024 01:21:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612869; x=1733217669; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5vCamtieJ1Any0nEDdOYudZWF6ph91xcO8/i+h+/3r0=; b=WpmWgXyrfuIkNdGBirDiL0o9+2F5c/OS9QxGPfWXRN14eKKiLmwatebdp8nz/Nq1hk OyohD5xO9pkHRT7odfi4tx+HukktcrVdtHGQQAdH3HQP3SaeSy2B3ynG/nH/1CXe6IG7 WNgEHOhQzJn/cDHa7kS8zUo+PHqz05tblKrdgTJFguG/Xn4Bf4PfUo7KzLHmDhdQ87Yg 1ckjGVQmD+DniYnpUUUeBd8Rj6DmQaXRmc+MteZ4bKIuM0KWYgCfaPoDikTp75gZIF0/ 6bgHXEZ8WK/3KNo5mVKDpQLD2r8/9UYw1GE6grw07hpOb8pq1cqFIjC0OAAXnWTStyeC HxZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612869; x=1733217669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5vCamtieJ1Any0nEDdOYudZWF6ph91xcO8/i+h+/3r0=; b=Tp4c7E12LLn19TNA6BSIhsvCnG2LpIEDZgX9KFKelbeuWNoWuYXLuHA757edehI3i0 MPHRj/cy662MZBd3eE+CYdo1zdzye2C/OF0eOKclJ2nWIvZHC8HtvLDdhS5XBbaeQO4R nqwRcjdZda7Bc7PlKSbKzHebsZCRrYt89GJq6bIAGBRvTcKYQ8rfRo3EZ74uga3kBE6g XRrEmkOZESeHP6nb7coK9Iufx/Fl8QMw2WnFyjQckYfnf+cvXd1XXaw5AF9bd+8C3/cd eB4m0A8EMM+jQIuHAOY6GuV+Gzkr+mTrXooOcceAqwaLWaGho8KKjccKfCzqx7TBCSt4 20sw== X-Forwarded-Encrypted: i=1; AJvYcCWoFVGS7jq8Ajoj8CB5mNNVZXr8cnMlujO5NJS9HfFidmLxNXlB/Mx4H8+PJpvyBzKBvUggBRya3l4=@vger.kernel.org X-Gm-Message-State: AOJu0Yw21MqTgjd3TiQrAtWu81NlF89l9KkL8jwnDuaunJA7OD6RHkaN 4Pi2YLg2cNdlTxvNSYx0jopEW2Jo0kAeTARY65gL8Um0RKSj6R8VSGfs88MylDs= X-Gm-Gg: ASbGncv5M80R0e/VQDosAqU8QBSYj+sopx1D7Qp6GbFqiAnWeJHpmBX3Fr2p1pI8HyC wjhursNZECVml60FTarsOgC8C9GwCaTnKF8A+JR6+gIHSLLrel8vRE1lJ9lyDyCU/blAROD7OrM TMkL1sj/qgsiShiTQOvFPefpM/uNVfUtstq1lR+aXfL935QceBogXUM2xbuDGYY5xhCQw/Ww1JE op6Ncx370xgrqIp6DtjjC3aTkO3i9CYh2OAca0hKGjX9mNIOQUWSBZCwz7UxEpDL877R61ZyHH3 EZY= X-Google-Smtp-Source: AGHT+IHaYOnIDbCpLmYeLO1a6tWYrQIEozAksJelkAeI7VXpQtyjiqqF3I9/uKkLk0h0PGHL3GFAQQ== X-Received: by 2002:a05:6000:2ad:b0:382:4a4e:25bb with SMTP id ffacd0b85a97d-38260bcc4fdmr15091977f8f.46.1732612868973; Tue, 26 Nov 2024 01:21:08 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:08 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 02/15] soc: renesas: Add SYSC driver for Renesas RZ family Date: Tue, 26 Nov 2024 11:20:37 +0200 Message-Id: <20241126092050.1825607-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S system controller (SYSC) has various registers that control signals specific to individual IPs. IP drivers must control these signals at different configuration phases. Add SYSC driver that allows individual SYSC consumers to control these signals. The SYSC driver exports a syscon regmap enabling IP drivers to use a specific SYSC offset and mask from the device tree, which can then be accessed through regmap_update_bits(). Currently, the SYSC driver provides control to the USB PWRRDY signal, which is routed to the USB PHY. This signal needs to be managed before or after powering the USB PHY off or on. Other SYSC signals candidates (as exposed in the the hardware manual of the RZ/G3S SoC) include: * PCIe: - ALLOW_ENTER_L1 signal controlled through the SYS_PCIE_CFG register - PCIE_RST_RSM_B signal controlled through the SYS_PCIE_RST_RSM_B register - MODE_RXTERMINATION signal controlled through SYS_PCIE_PHY register * SPI: - SEL_SPI_OCTA signal controlled through SYS_IPCONT_SEL_SPI_OCTA register * I2C/I3C: - af_bypass I2C signals controlled through SYS_I2Cx_CFG registers (x=0..3) - af_bypass I3C signal controlled through SYS_I3C_CFG register * Ethernet: - FEC_GIGA_ENABLE Ethernet signals controlled through SYS_GETHx_CFG registers (x=0..1) As different Renesas RZ SoC shares most of the SYSC functionalities available on the RZ/G3S SoC, the driver if formed of a SYSC core part and a SoC specific part allowing individual SYSC SoC to provide functionalities to the SYSC core. Signed-off-by: Claudiu Beznea --- Change in v2: - this was patch 04/16 in v1 - dropped the initial approach proposed in v1 where a with a reset controller driver was proposed to handle the USB PWRRDY signal - implemented it with syscon regmap and the SYSC signal concept (introduced in this patch) drivers/soc/renesas/Kconfig | 7 + drivers/soc/renesas/Makefile | 2 + drivers/soc/renesas/r9a08g045-sysc.c | 31 +++ drivers/soc/renesas/rz-sysc.c | 286 +++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.h | 52 +++++ 5 files changed, 378 insertions(+) create mode 100644 drivers/soc/renesas/r9a08g045-sysc.c create mode 100644 drivers/soc/renesas/rz-sysc.c create mode 100644 drivers/soc/renesas/rz-sysc.h diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 9f7fe02310b9..0686c3ad9e27 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -378,4 +378,11 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST +config SYSC_RZ + bool "System controller for RZ SoCs" if COMPILE_TEST + +config SYSC_R9A08G045 + bool "Renesas RZ/G3S System controller support" if COMPILE_TEST + select SYSC_RZ + endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 734f8f8cefa4..8cd139b3dd0a 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -6,7 +6,9 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif +obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o +obj-$(CONFIG_SYSC_RZ) += rz-sysc.o diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c new file mode 100644 index 000000000000..ceea738aee72 --- /dev/null +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include + +#include "rz-sysc.h" + +#define SYS_USB_PWRRDY 0xd70 +#define SYS_USB_PWRRDY_PWRRDY_N BIT(0) +#define SYS_MAX_REG 0xe20 + +static const struct rz_sysc_signal_init_data rzg3s_sysc_signals_init_data[] __initconst = { + { + .name = "usb-pwrrdy", + .offset = SYS_USB_PWRRDY, + .mask = SYS_USB_PWRRDY_PWRRDY_N, + .refcnt_incr_val = 0 + } +}; + +const struct rz_sysc_init_data rzg3s_sysc_init_data = { + .signals_init_data = rzg3s_sysc_signals_init_data, + .num_signals = ARRAY_SIZE(rzg3s_sysc_signals_init_data), + .max_register_offset = SYS_MAX_REG, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c new file mode 100644 index 000000000000..dc0edacd7170 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rz-sysc.h" + +/** + * struct rz_sysc - RZ SYSC private data structure + * @base: SYSC base address + * @dev: SYSC device pointer + * @signals: SYSC signals + * @num_signals: number of SYSC signals + */ +struct rz_sysc { + void __iomem *base; + struct device *dev; + struct rz_sysc_signal *signals; + u8 num_signals; +}; + +static int rz_sysc_reg_read(void *context, unsigned int off, unsigned int *val) +{ + struct rz_sysc *sysc = context; + + *val = readl(sysc->base + off); + + return 0; +} + +static struct rz_sysc_signal *rz_sysc_off_to_signal(struct rz_sysc *sysc, unsigned int offset, + unsigned int mask) +{ + struct rz_sysc_signal *signals = sysc->signals; + + for (u32 i = 0; i < sysc->num_signals; i++) { + if (signals[i].init_data->offset != offset) + continue; + + /* + * In case mask == 0 we just return the signal data w/o checking the mask. + * This is useful when calling through rz_sysc_reg_write() to check + * if the requested setting is for a mapped signal or not. + */ + if (mask) { + if (signals[i].init_data->mask == mask) + return &signals[i]; + } else { + return &signals[i]; + } + } + + return NULL; +} + +static int rz_sysc_reg_update_bits(void *context, unsigned int off, + unsigned int mask, unsigned int val) +{ + struct rz_sysc *sysc = context; + struct rz_sysc_signal *signal; + bool update = false; + + signal = rz_sysc_off_to_signal(sysc, off, mask); + if (signal) { + if (signal->init_data->refcnt_incr_val == val) { + if (!refcount_read(&signal->refcnt)) { + refcount_set(&signal->refcnt, 1); + update = true; + } else { + refcount_inc(&signal->refcnt); + } + } else { + update = refcount_dec_and_test(&signal->refcnt); + } + } else { + update = true; + } + + if (update) { + u32 tmp; + + tmp = readl(sysc->base + off); + tmp &= ~mask; + tmp |= val & mask; + writel(tmp, sysc->base + off); + } + + return 0; +} + +static int rz_sysc_reg_write(void *context, unsigned int off, unsigned int val) +{ + struct rz_sysc *sysc = context; + struct rz_sysc_signal *signal; + + /* + * Force using regmap_update_bits() for signals to have reference counter + * per individual signal in case there are multiple signals controlled + * through the same register. + */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) { + dev_err(sysc->dev, + "regmap_write() not allowed on register controlling a signal. Use regmap_update_bits()!"); + return -EOPNOTSUPP; + } + + writel(val, sysc->base + off); + + return 0; +} + +static bool rz_sysc_writeable_reg(struct device *dev, unsigned int off) +{ + struct rz_sysc *sysc = dev_get_drvdata(dev); + struct rz_sysc_signal *signal; + + /* Any register containing a signal is writeable. */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) + return true; + + return false; +} + +static bool rz_sysc_readable_reg(struct device *dev, unsigned int off) +{ + struct rz_sysc *sysc = dev_get_drvdata(dev); + struct rz_sysc_signal *signal; + + /* Any register containing a signal is readable. */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) + return true; + + return false; +} + +static int rz_sysc_signals_show(struct seq_file *s, void *what) +{ + struct rz_sysc *sysc = s->private; + + seq_printf(s, "%-20s Enable count\n", "Signal"); + seq_printf(s, "%-20s ------------\n", "--------------------"); + + for (u8 i = 0; i < sysc->num_signals; i++) { + seq_printf(s, "%-20s %d\n", sysc->signals[i].init_data->name, + refcount_read(&sysc->signals[i].refcnt)); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(rz_sysc_signals); + +static void rz_sysc_debugfs_remove(void *data) +{ + debugfs_remove_recursive(data); +} + +static int rz_sysc_signals_init(struct rz_sysc *sysc, + const struct rz_sysc_signal_init_data *init_data, + u32 num_signals) +{ + struct dentry *root; + int ret; + + sysc->signals = devm_kcalloc(sysc->dev, num_signals, sizeof(*sysc->signals), + GFP_KERNEL); + if (!sysc->signals) + return -ENOMEM; + + for (u32 i = 0; i < num_signals; i++) { + struct rz_sysc_signal_init_data *id; + + id = devm_kzalloc(sysc->dev, sizeof(*id), GFP_KERNEL); + if (!id) + return -ENOMEM; + + id->name = devm_kstrdup(sysc->dev, init_data->name, GFP_KERNEL); + if (!id->name) + return -ENOMEM; + + id->offset = init_data->offset; + id->mask = init_data->mask; + id->refcnt_incr_val = init_data->refcnt_incr_val; + + sysc->signals[i].init_data = id; + refcount_set(&sysc->signals[i].refcnt, 0); + } + + sysc->num_signals = num_signals; + + root = debugfs_create_dir("renesas-rz-sysc", NULL); + ret = devm_add_action_or_reset(sysc->dev, rz_sysc_debugfs_remove, root); + if (ret) + return ret; + debugfs_create_file("signals", 0444, root, sysc, &rz_sysc_signals_fops); + + return 0; +} + +static struct regmap_config rz_sysc_regmap = { + .name = "rz_sysc_regs", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, + .reg_read = rz_sysc_reg_read, + .reg_write = rz_sysc_reg_write, + .reg_update_bits = rz_sysc_reg_update_bits, + .writeable_reg = rz_sysc_writeable_reg, + .readable_reg = rz_sysc_readable_reg, +}; + +static const struct of_device_id rz_sysc_match[] = { +#ifdef CONFIG_SYSC_R9A08G045 + { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data }, +#endif + { } +}; +MODULE_DEVICE_TABLE(of, rz_sysc_match); + +static int rz_sysc_probe(struct platform_device *pdev) +{ + const struct rz_sysc_init_data *data; + struct device *dev = &pdev->dev; + struct rz_sysc *sysc; + struct regmap *regmap; + int ret; + + data = device_get_match_data(dev); + if (!data || !data->max_register_offset) + return -EINVAL; + + sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); + if (!sysc) + return -ENOMEM; + + sysc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sysc->base)) + return PTR_ERR(sysc->base); + + sysc->dev = dev; + + ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals); + if (ret) + return ret; + + dev_set_drvdata(dev, sysc); + rz_sysc_regmap.max_register = data->max_register_offset; + regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); +} + +static struct platform_driver rz_sysc_driver = { + .driver = { + .name = "renesas-rz-sysc", + .of_match_table = rz_sysc_match + }, + .probe = rz_sysc_probe +}; + +static int __init rz_sysc_init(void) +{ + return platform_driver_register(&rz_sysc_driver); +} +subsys_initcall(rz_sysc_init); + +MODULE_DESCRIPTION("Renesas RZ System Controller Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h new file mode 100644 index 000000000000..bb850310c931 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ System Controller + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __SOC_RENESAS_RZ_SYSC_H__ +#define __SOC_RENESAS_RZ_SYSC_H__ + +#include +#include + +/** + * struct rz_sysc_signal_init_data - RZ SYSC signals init data + * @name: signal name + * @offset: register offset controling this signal + * @mask: bitmask in register specific to this signal + * @refcnt_incr_val: increment refcnt when setting this value + */ +struct rz_sysc_signal_init_data { + const char *name; + u32 offset; + u32 mask; + u32 refcnt_incr_val; +}; + +/** + * struct rz_sysc_signal - RZ SYSC signals + * @init_data: signals initialization data + * @refcnt: reference counter + */ +struct rz_sysc_signal { + const struct rz_sysc_signal_init_data *init_data; + refcount_t refcnt; +}; + +/** + * struct rz_sysc_init_data - RZ SYSC initialization data + * @signals_init_data: RZ SYSC signals initialization data + * @num_signals: number of SYSC signals + * @max_register_offset: Maximum SYSC register offset to be used by the regmap config + */ +struct rz_sysc_init_data { + const struct rz_sysc_signal_init_data *signals_init_data; + u32 num_signals; + u32 max_register_offset; +}; + +extern const struct rz_sysc_init_data rzg3s_sysc_init_data; + +#endif /* __SOC_RENESAS_RZ_SYSC_H__ */ From patchwork Tue Nov 26 09:20:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 845715 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE3771C303E for ; Tue, 26 Nov 2024 09:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612875; cv=none; b=Ce2XIuPUEGD0aBfAaZSRNNy2JkTYpCtJkk5wtwyZEOTo4U+Wx8srEmD0s9rV3lOimktdNZbhmzEpdw3gvYX4NyCRESWOon9nkvESyJzU4Jc57U+M6+DlpwmYcL5O4YBllWq+7G1k53XaZq39iiEi8aUJPG1nMleXHUIZdXAb32Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612875; c=relaxed/simple; bh=okZZML2tc4SYJzj0YGY5NcNIBGhTp8dqg/vTqnmY3SY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T+EN7X/vUCThaVmipDAk8z6SJTwnxtz4NzXFlCiUwaepTbDBP7i3rBSOUcu9mnDGuN6SJEJREs1vyS/O8ptA+B4dGDNcGcy+rN+WG0f6sd3SGZYUxTSdFO4UF86lJAGwL9NuulMqyQY5dHdImgHxdW6unwXPkUE9ZcFPq4bd35w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=bNOjl/S5; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="bNOjl/S5" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-434a752140eso2728135e9.3 for ; Tue, 26 Nov 2024 01:21:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612872; x=1733217672; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VDINqiI7eZIxSdpV6EMx/C3NNutYl7b6+j2YZ5M4Qvg=; b=bNOjl/S5uwPrg6QR9r4uvpJWWI/onLN+H2g5+ab6xGa7jvGAwqhfeW4LzMiewJbo15 boAuzeEnL353Hth/rk2rk3Hu7A5Jaz3I9yPDzy0d+Gj8wZSpNQ+1qo+++ZnJMPQ6R/J+ j3FcQnBaPbyd4/OD1QzY7DzDaWM5wa47YZUOtc+mnqYxAZhPdLrTm05A56/Wu6gG9Lxu HPGHABZJmxVeB96ztwfaPEfVKqkXedrvb77nFrAt+bcaZYzOUsx1SoW8rsxRwSwFNUrJ jx1+La3RJ3+eIzKd6dCEZCvX2aXPCT7a7So76dgSyVn9K8kwmCrf92IXtk8LcaQKr/Zk X2nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612872; x=1733217672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VDINqiI7eZIxSdpV6EMx/C3NNutYl7b6+j2YZ5M4Qvg=; b=ITDtY7x33/GwmdBA+zoC9oFVBP1a8ZFGYEzfciH4UnBvLY0mswPvE7x9h5IdP/UQDD Wb+gAPDDEPcSZrhDw6Ly5cTMcMQY/asisxzMwRX8h38yNwt39/mdGO6BbPUWtzY4zYe7 +H8Wl1QPeQdqDT3RD6S8npeK8K0Hf9mHL5h2b57lWqi6jjn1hiA5yLR+ZwEKDTvWScwz 0AHntbpyi/zsbXMdT2eGWNdxYDVRQvgL/RJZ9mtAd3nsdft063o3wYkhiag2IcePClug PM0HfFWsA3l9WjnF/zpCDzGO5aXxAUwnKEbTEpLIv4MiDDZOjjyrPz5k53Ehlz60pPCL VqDQ== X-Forwarded-Encrypted: i=1; AJvYcCXQC5kowPjKdC7Pp5Z104hcbEzHZ5FQTevw4hB7EN6cQMgpwLyQyaWTypf6tGwBcNb/MYLV8E8hp7s=@vger.kernel.org X-Gm-Message-State: AOJu0YwaxBqgBD7uJ32BSYxVdzxCofAzZRuOhUyTmQlO1Z5tFkqitwnS 3mCi5G7MAJgkl4C4PR3f2R8FE3iCr/cx7SSXXczsq4h1GSOcLj9kKuH/dzb9Enk= X-Gm-Gg: ASbGnctNsG/gAWDAcpnpFCikP1PwNf4IkDAbF+yXas2YsdJX6Yrtg/KndahHncqVYuT ifFIwWgzN7BIoNKy1V0EwqOW43Twe1jpg0ccgi2Ua+YeePSMrBTkAkVzgBKzSnmhrsJ0hdqUafl bE97Qoy9VRkgbB6zN8PLGa3AR+JzO7SvZO94Nm+HrhklNF6+P+/FlbK9uBVdEmnUk6M6CfCI+m4 5MV0xQFo/0Xu6UqMK6VBet7r2LqEUl/VgDliMDqGpUkX3oFEIpfZ690zjzcFEZkghFHjROuIqkQ GxM= X-Google-Smtp-Source: AGHT+IFiAn9ufP/2lxYbOVs5nw6bxrcqi6yQ6uQejelWxHdSz9crLVthGd227EDJ3fiqmZHYRLomqQ== X-Received: by 2002:a05:600c:1c23:b0:434:9e63:faff with SMTP id 5b1f17b1804b1-4349e63fe62mr73118195e9.2.1732612872339; Tue, 26 Nov 2024 01:21:12 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:11 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 04/15] soc: renesas: rz-sysc: Add SoC detection support Date: Tue, 26 Nov 2024 11:20:39 +0200 Message-Id: <20241126092050.1825607-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ SYSC controller has registers that keep the SoC ID data. Add driver support to retrieve the SoC ID and register a SoC driver. Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 05/16 in v1 - changed patch title and description - added SoC initialization code in its own function - addressed the review comments - introduced struct rz_sysc_soc_id_init_data and adjusted the code accordingly - dropped the RZ/G3S SoC detection code (it will be introduced in a separate patch) drivers/soc/renesas/rz-sysc.c | 72 +++++++++++++++++++++++++++++++++-- drivers/soc/renesas/rz-sysc.h | 18 +++++++++ 2 files changed, 86 insertions(+), 4 deletions(-) diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index dc0edacd7170..d34d295831b8 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -14,9 +14,12 @@ #include #include #include +#include #include "rz-sysc.h" +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + /** * struct rz_sysc - RZ SYSC private data structure * @base: SYSC base address @@ -211,6 +214,59 @@ static int rz_sysc_signals_init(struct rz_sysc *sysc, return 0; } +static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *match) +{ + const struct rz_sysc_init_data *sysc_data = match->data; + const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data; + struct soc_device_attribute *soc_dev_attr; + const char *soc_id_start, *soc_id_end; + u32 val, revision, specific_id; + struct soc_device *soc_dev; + char soc_id[32] = {0}; + u8 size; + + if (!soc_data || !soc_data->family || !soc_data->offset || + !soc_data->revision_mask) + return -EINVAL; + + soc_id_start = strchr(match->compatible, ',') + 1; + soc_id_end = strchr(match->compatible, '-'); + size = soc_id_end - soc_id_start; + if (size > 32) + size = 32; + strscpy(soc_id, soc_id_start, size); + + soc_dev_attr = devm_kzalloc(sysc->dev, sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = soc_data->family; + soc_dev_attr->soc_id = devm_kstrdup(sysc->dev, soc_id, GFP_KERNEL); + if (!soc_dev_attr->soc_id) + return -ENOMEM; + + val = readl(sysc->base + soc_data->offset); + revision = field_get(soc_data->revision_mask, val); + specific_id = field_get(soc_data->specific_id_mask, val); + soc_dev_attr->revision = devm_kasprintf(sysc->dev, GFP_KERNEL, "%u", revision); + if (!soc_dev_attr->revision) + return -ENOMEM; + + if (soc_data->id && specific_id != soc_data->id) { + dev_warn(sysc->dev, "SoC mismatch (product = 0x%x)\n", specific_id); + return -ENODEV; + } + + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, soc_dev_attr->revision); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + return 0; +} + static struct regmap_config rz_sysc_regmap = { .name = "rz_sysc_regs", .reg_bits = 32, @@ -235,14 +291,15 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); static int rz_sysc_probe(struct platform_device *pdev) { const struct rz_sysc_init_data *data; + const struct of_device_id *match; struct device *dev = &pdev->dev; - struct rz_sysc *sysc; struct regmap *regmap; + struct rz_sysc *sysc; int ret; - data = device_get_match_data(dev); - if (!data || !data->max_register_offset) - return -EINVAL; + match = of_match_node(rz_sysc_match, dev->of_node); + if (!match || !match->data) + return -ENODEV; sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) @@ -253,6 +310,13 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); sysc->dev = dev; + ret = rz_sysc_soc_init(sysc, match); + if (ret) + return ret; + + data = match->data; + if (!data->max_register_offset) + return -EINVAL; ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals); if (ret) diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index bb850310c931..babca9c743c7 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -35,13 +35,31 @@ struct rz_sysc_signal { refcount_t refcnt; }; +/** + * struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initialization data + * @family: RZ SoC family + * @id: RZ SoC expected ID + * @offset: SYSC SoC ID register offset + * @revision_mask: SYSC SoC ID revision mask + * @specific_id_mask: SYSC SoC ID specific ID mask + */ +struct rz_sysc_soc_id_init_data { + const char * const family; + u32 id; + u32 offset; + u32 revision_mask; + u32 specific_id_mask; +}; + /** * struct rz_sysc_init_data - RZ SYSC initialization data + * @soc_id_init_data: RZ SYSC SoC ID initialization data * @signals_init_data: RZ SYSC signals initialization data * @num_signals: number of SYSC signals * @max_register_offset: Maximum SYSC register offset to be used by the regmap config */ struct rz_sysc_init_data { + const struct rz_sysc_soc_id_init_data *soc_id_init_data; const struct rz_sysc_signal_init_data *signals_init_data; u32 num_signals; u32 max_register_offset; From patchwork Tue Nov 26 09:20:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 845714 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47ED71CEAB4 for ; Tue, 26 Nov 2024 09:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612879; cv=none; b=FYA4nCfB6nEQODHTYB2+ACH79wFwshjr4eRMym2RUiK+1nAMmRfR9REY1hb64pX+0WJY8dym+EUYNI3oOEJ/QEiykA/EjO0KCeom2J9FCmlAYhhSSiWBXpF2Du58lg+3cRNw/XHL1kiBzdjlGxGbVihNK26/2Sgtdeb1nkGGn1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612879; c=relaxed/simple; bh=peR4Vif7woHWK7GGXYa577M+2RIwJeK0uX7OsLiQUiU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=THtsa1FM3ORkZ1W6Bk17zQYDy6CLutr0Ds9FLXIDJqMknmYn+966pGCCrrd9VYbK2d/HqDNsyYr3bbkW4/d2wVKtV36DaHUyuLscV1cBfeN6ZApzZqxr68BYkosaw/DnHiuBUysMw9X+WE9iEMketiAWUwEG/MSgOHkpB+L2ndI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=k2w87Jjk; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="k2w87Jjk" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-382296631f1so4284791f8f.3 for ; Tue, 26 Nov 2024 01:21:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612876; x=1733217676; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sn4qpT/iGLCOuVRl/HhbV74eVKZi/FzZDWa4nL4zSFw=; b=k2w87JjkHiabvDLC4jaRhmjbfFPncA2OiY4Gaxwqmhc5ne188YaKHCRXNjLeianRqW 1493NnWQGtdSNN7Axs8Q3bg5IWUWBQcQm4koKNyZAfBQK5lP9tnG2IWpSf8ULwHhQK2p x+3wNDSM2BDkbdFDIqnl1mGB2g7zjbqy6FGGotYxIAHz90d/iw9dWV1N4U8w0wm+hvbt PrhPOrvOevVl+8ZO9I6tY6+yZDQ7vippzhKOM1YmjuuqY4X2HfkZ+rGlW2KcMSPbtR0Z q/iPzepPY3vNz1N5Ec4far7nRrhIgx3o5mpIdhRuY2o0EFGRlTT1+oGZwsyN6rN+GIlL aBhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612876; x=1733217676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sn4qpT/iGLCOuVRl/HhbV74eVKZi/FzZDWa4nL4zSFw=; b=U482NHv1VtoHHgj6Not6LgFV55RUb3GhaJ0xCXB8RuGW3CO4vmHm3XawjNj93woFst HevyYgiFf2u5z6UOtGDXr+2PR/shuTeIJiHogeJVpoYvqrZPCWB6R+XbevaT6gRddhuh eZ5skvteWhdSwcFtVaWQNYZTMhxXLoyiQIoNWyCzIeK5Zn526hxZ1HMBjIm54rwhdQGu yqZQMCq5QjccKJqwY8i3tJU5YEzI5GLPZud8rT2rfehZKjTT+KKiej1JXpiqV2xWRhUq BdsSJ6po5F/wN7Usli/c86/2AupGLvPPpTpOyls7SVeZboyaBYB7ES237b8Pr7HXKGdC eMNA== X-Forwarded-Encrypted: i=1; AJvYcCXjpKWk8kKwyJG7i6wC26gL8N8bbdqUfq+MY86W4Xdys+/f3t1SVt0sjGhN3E0JdnEbtki0Bu8vP1Y=@vger.kernel.org X-Gm-Message-State: AOJu0Yyhy62H0B4GHWJqr6BxNu0dqSMzw2sc2V32bDBLXm16c7+AfNKT 8FBOnB13sLIdH3b6lt/94lCTII32Z71VqHr9cytRQvQWEQuEQ3S9uuVqv22FH8U= X-Gm-Gg: ASbGncvIMkxuW7z4Fj1XBlMmVZ2B8M6Zh39WvY/FlFkEGgTmHAS5AqyeUEPOhS4vFim tKZSecJFu916j0Zr+dVFpXmrWMWpFFAOUTjq/2gyKIYhARGp+aj6hUOJ8XW1pMyG27jUTqvHE9B Ygzhj8wPofv/OAiV5Bm/6n3r+4fwavIUUDs3ZBK2v7pUcah7UO0HwgIGptTLaPzG7AytBuvY0pN sbxGP3qBore6ps35uQStceOYxE2GHZupKySM33Ps5xqx4CCwry7sTKaAxO+QCDVgeaI6ttvQQph rGY= X-Google-Smtp-Source: AGHT+IEownUh3zO6s9pCDV0Clvw+JlHntDQwx/j8qHfP92J8/y9dWvLESVOAtn+7QOc0lvgJXmcboQ== X-Received: by 2002:a5d:5f4b:0:b0:382:1831:f7db with SMTP id ffacd0b85a97d-38260b59bc9mr13021685f8f.19.1732612875617; Tue, 26 Nov 2024 01:21:15 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:15 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea , Conor Dooley Subject: [PATCH v2 06/15] dt-bindings: usb: renesas, usbhs: Document RZ/G3S SoC Date: Tue, 26 Nov 2024 11:20:41 +0200 Message-Id: <20241126092050.1825607-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The USBHS IP block on RZ/G3S SoC is identitcal to the one found on the RZ/G2L device. Document the RZ/G3S USBHS IP block. Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 09/16 in v1 - collected tags Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index b23ef29bf794..980f325341d4 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -26,6 +26,7 @@ properties: - renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five - renesas,usbhs-r9a07g044 # RZ/G2{L,LC} - renesas,usbhs-r9a07g054 # RZ/V2L + - renesas,usbhs-r9a08g045 # RZ/G3S - const: renesas,rzg2l-usbhs - items: @@ -130,6 +131,7 @@ allOf: - renesas,usbhs-r9a07g043 - renesas,usbhs-r9a07g044 - renesas,usbhs-r9a07g054 + - renesas,usbhs-r9a08g045 then: properties: interrupts: From patchwork Tue Nov 26 09:20:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 845713 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A514118E057 for ; Tue, 26 Nov 2024 09:21:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612883; cv=none; b=TDLJlbzr8Lgu8k+4MF2qRY/arK+u0ecPvYalT9gu5RCl/3MwSPEZabsCtgIqT76ikAMc3dTtWbBeRZwTP/PhN8kxKLGU17e5dWbA42fT+IStBA8DUZZYFc6xLBJrVYMnjUqWusiVkThBytVY9ouNw42j6lj2CsbUqXFtUYpN8wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612883; c=relaxed/simple; bh=oNWXU+YttETsW6YOLdXCM5FnMtFquAK1N6LvtZPkJkY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UuSXsiJRysI7Nd0LrX5edD1wrZ20ecXIy8ok4AkutXcMCsUXnozo/86NGO7YxERUMRV68ASzO4ufA+NlhYJ8oqKB6kpSYLZQ9iRX4EcZNvAEUWStNgaRgCR6cImiLGGN/ZlXJW/KFVXtzpO6pJzjvE8swxnjY/FFtmgmW2tRwnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=UdSqcXsp; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="UdSqcXsp" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-382433611d0so4488990f8f.3 for ; Tue, 26 Nov 2024 01:21:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612879; x=1733217679; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/jPyHfXjv1sKCq+VDx+r3KGfTA+9eZQsBfgYv3YFZiw=; b=UdSqcXspX4GlVVQ9ykeNkVCt1X+Jj/LfbN9xD/pmohjLFZrU8SIiOVFdfAqhU6jGu9 JZ+GNbfv3X5aPU8YWnehhC0HTItYCE9ZdHtmzNJ3TASEVVg15zM5UfKc+NaGYpgO75ze 0vEC0f6dcALONwYLOHbUmQl/78LTYeEA6ClBTI8On0/dYUr1gnsrjrj3TNfSc+5Dq5NQ e6TUy+XjsODNZ/0g08nZiCmro+mWP9Y7nhf8YjGuL+pp45FCXcAMypVC1GNG5VKCPbWd m3UEO4KValOWTdgC/HRl1F2BxIVluJhiJSNXFJdhf7VqtWX3QgqxFT9wB40kffi7dQad 5+LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612879; x=1733217679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/jPyHfXjv1sKCq+VDx+r3KGfTA+9eZQsBfgYv3YFZiw=; b=Xz5JEC5WMkqXXXFbqw3p3D0v8ZV1ucmrsRVi2vdcZWGLXQPqL7gHqlyO7oirHCLZja xjNuYCIkyS4EfwQQoN+QGfhT6c+RDnCuT58W1EA8CEve2LkYa/yCkOi6Emd0JmJb7HMi 5VSmCRPY/oWW+oRbF2qurgJyN1zZKXQ/OGEGbAGgmFXFpq8o+mzDwBim6KUfdmEfp0CE pYClveBrJ+BwHry4aZSZ/cMqZC3AhKWxGnBg2c+J2lwoaKGR/ETADjNsPMMmDm0qilnm P/l22Zo7p4DyS4BDu/RXssvSTjtMkyWl7zUT7VkCKsxWM36ct0LoP5NibBLhlRi2SVcl /LEA== X-Forwarded-Encrypted: i=1; AJvYcCUq0uV+0WUv5MCAK3SAELBTVNcsG/4bsQX58c7/KmyRTo0sipVHCzVeT0GZpxyOqkvi7UXQSXTTRW8=@vger.kernel.org X-Gm-Message-State: AOJu0YzA7TEYKSq1mNQ+Ul+iV0OfaHDubCGLCbeqE987TCDs/tRSmY5w QR9sf0Ba1hhTau/llgmakj6f/3J5Wuc3gLyTmHwdaTKVll3xAzc70q1lkYm+xUk= X-Gm-Gg: ASbGnctaYOx4sDwr80/KNmBiesHVguNWc6R/gl+Zqr/KpiBZOw7stnSud87+3ORPiUU /YwhAVOGa9nzcUMN8pdN5ZiDl8aS8MBofr9Ya6rz9SJGbvLpp4NLeCy+3plvpGMRluMZvWrSxMx mFM2ZlkKJlz6vfyHmi68jw/pSeV5b+sXDkzBBs3z6ief/F2RYFQ8ZWNQ3FC51qA6yG0D2rZgRMv zCV//hCzh+upO6qDT5D/tGq+LOC6AcJ1zn5otS3ZqqzFz8JX8FE60lUyNvnI6yYpxkQdTYZVIFO MOk= X-Google-Smtp-Source: AGHT+IEp0nHr3rTgVabZUcIb7+yLYE3qyOs/bjCx+FjVzVqxsxe18o0APHGg56PeptK8REX7Zr/0Jw== X-Received: by 2002:a5d:64a9:0:b0:382:4fa4:e544 with SMTP id ffacd0b85a97d-38260b3caf5mr16113423f8f.6.1732612879055; Tue, 26 Nov 2024 01:21:19 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:18 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 08/15] dt-bindings: phy: renesas,usb2-phy: Add renesas,sysc-signal Date: Tue, 26 Nov 2024 11:20:43 +0200 Message-Id: <20241126092050.1825607-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY receives a signal from the system controller that need to be de-asserted/asserted when power is turned on/off. This signal, called PWRRDY, is controlled through a specific register in the system controller memory space. Add the renesas,sysc-signal DT property to describe the relation b/w the system controller and the USB PHY on the Renesas RZ/G3S. This property provides a phandle to the system controller, along with the offset within the system controller memory space that manages the signal and a bitmask that indicates the specific bits required to control the signal. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new .../bindings/phy/renesas,usb2-phy.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 2babd200bd98..3b8dcacc3740 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -85,6 +85,16 @@ properties: dr_mode: true + renesas,sysc-signal: + description: System controller phandle, specifying the register + offset and bitmask associated with a specific system controller signal + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: system controller phandle + - description: register offset associated with a signal + - description: register bitmask associated with a signal + if: properties: compatible: @@ -112,6 +122,18 @@ allOf: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,usb2-phy-r9a08g045 + then: + required: + - renesas,sysc-signal + else: + properties: + renesas,sysc-signal: false + additionalProperties: false examples: From patchwork Tue Nov 26 09:20:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 845712 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B9DA1D5140 for ; Tue, 26 Nov 2024 09:21:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612886; cv=none; b=UPNKXmvI6W6LZvbbXRdNDfivRoROOeRuj4RBh1nhFxaKOE9WW4C1ej+pooMxyK2cx3aWRjJcSepofV3G3M2WLW/a60oL2veB/QrUPzNq/mex2Xc+TfDU8+BkROoXNOLRwUTv8LlgBdLdOU2l45SQli65ctnqC2zZMYfwNwWQDMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612886; c=relaxed/simple; bh=M5ukcPKgKAfKHyOFRejl++X5XYltOB0VkZUniY5CCHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YAYCI++SHjfIiG3TfrlmUa335Jo7Y5aTTf/shv6vq0kvagoVUMPaLOJizb6GJ+YbYB5DbMYNLkFm+cNe6ZlDEWWhloFzONsQlZgIDXZrgHJg2mZsi0MD8EXcEkqCBgrK9Cq0TpJGRZ17XxAbSzYPdu1OsqXkB7c4FRzb1uGFOyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=m4pWcI94; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="m4pWcI94" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4315abed18aso47743595e9.2 for ; Tue, 26 Nov 2024 01:21:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612883; x=1733217683; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GaBexvzYFyRAvmFf5CNX0T/OFU5Y8NOKhiyYn5h/HqM=; b=m4pWcI94uKuc0Xmc6HVPbZp8l38puM95OFw0TWlvjptLypGHVqNdKvSaiOnw5ofqqv DyMF3h31akudE2xSvjUhDCb92Fj2+CtEXLITUhSXzmjmngxnBp0lFFfZIOT+P09U5MLc /Zm5NjMO+kDT8ORny/HxNQ/nZI99yTa8jAqqc165ey2XMHJvcSkOCwr6u9P+wMAOBpHD XJKuFcMjLUr3JN1x8YkXT6rORWr9dCqpfQ8XFB7wPhEilDBEKrHHnN9zKN51SCYDVac5 +cdnTMa+lmnY341dpeo69+vRvDbYIrEyd+lOoBqU95pJO9lTNjOXf1kMbz3tojCdefi4 LrGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612883; x=1733217683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GaBexvzYFyRAvmFf5CNX0T/OFU5Y8NOKhiyYn5h/HqM=; b=a1hMYGmOLAtU6TAzAqeujAAmixVg+c9uA0z7cla7bUi7dXQBNeO9FiG9Du91ETnnNT +78DTmwofcw+NR3i+JR51q4fVYizCKLh7aG534foVnqlS9xhQxmAZQp52QdAm1VlCAvS fu4nKP/7UrWrmQT0tIji4EgsE99RVs+txQwdztxbxznQDyrHZ0zAFzcHpHI1qALyBC3K F7kR6J6QZ5YSf8g6El0BqfrVvc6uDw5wkDcwj5dsXQ2ZURzAmTiLppz8Ffjmj5pbEmGy NPpZYCHBNg7syq9WFN0a69G+A4riOtVTaK2oK5WZKnn+12yDh7rXtRHrBJyvjkO0NvYg 2aJQ== X-Forwarded-Encrypted: i=1; AJvYcCUFOMPMwCGlqR6BBW5rWO+nS0cMcbLez2p/mggIdozjHchlFhDQAbggyvdAG7k7jB5/605N7VGh92I=@vger.kernel.org X-Gm-Message-State: AOJu0YyClTeVrPJV0hh1vxfRqWZZFWIWt2RuENeS2EIxSzlQPH44u6Lg 5+UMlECnqy+HNyloYUAVpTy0TK0VJ2/tqRJv2ynTaef+v+N+BfXzbzxtmmN4GNM= X-Gm-Gg: ASbGncv/yLYQQyZWSCw5XKzRm2ikYM0g9mqml736x9BVGSMIHp60T7of/lwlQNznUDr wv0IcDTBh8YbEj4AoildKp/kr60eJN5xo8VaTAJsGTkm01UrLMQ/t/juTVtDA0GDdZDpfkqkaR0 +8H5uu9UUZGyUv3bZLSVdFYdBly84CgcaEVPOKFspaJzjjlfIb6Od+8wb1QK4crvLzRfGL2TR6p yWZhRwKKgdY+zM3UpeF8fNqbO6f0T1050GduWWMI6jlIF+on9ci7ZxEqtOAHD9T0wNO4g69gmwg RPg= X-Google-Smtp-Source: AGHT+IGx29P8JteJsbR7aMf1tNqIx4rHFyFlQRbqnmSPeJkN3FtdMhddq6elNPOMjEa7BoKccqaeCw== X-Received: by 2002:a05:6000:1f8c:b0:382:4378:462a with SMTP id ffacd0b85a97d-38260b759c0mr13201703f8f.24.1732612882831; Tue, 26 Nov 2024 01:21:22 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:22 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 10/15] phy: renesas: rcar-gen3-usb2: Add support for PWRRDY Date: Tue, 26 Nov 2024 11:20:45 +0200 Message-Id: <20241126092050.1825607-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. The connection b/w the system controller and the USB PHY is implemented through the renesas,sysc-signal device tree property. This property specifies the register offset and the bitmask required to control the signal. The system controller exports the syscon regmap, and the read/write access to the memory area of the PWRRDY signal is reference-counted, as the same system controller signal is connected to both RZ/G3S USB PHYs. Add support for the PWRRDY signal control. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new drivers/phy/renesas/phy-rcar-gen3-usb2.c | 66 ++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 59f74aa993ac..84459755adf5 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -12,12 +12,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -111,6 +113,12 @@ struct rcar_gen3_phy { bool powered; }; +struct rcar_gen3_pwrrdy { + struct regmap *regmap; + u32 offset; + u32 mask; +}; + struct rcar_gen3_chan { void __iomem *base; struct device *dev; /* platform_device's device */ @@ -118,6 +126,7 @@ struct rcar_gen3_chan { struct rcar_gen3_phy rphys[NUM_OF_PHYS]; struct regulator *vbus; struct reset_control *rstc; + struct rcar_gen3_pwrrdy *pwrrdy; struct work_struct work; struct mutex lock; /* protects rphys[...].powered */ enum usb_dr_mode dr_mode; @@ -133,6 +142,7 @@ struct rcar_gen3_phy_drv_data { const struct phy_ops *phy_usb2_ops; bool no_adp_ctrl; bool init_bus; + bool pwrrdy; }; /* @@ -587,6 +597,7 @@ static const struct rcar_gen3_phy_drv_data rz_g3s_phy_usb2_data = { .phy_usb2_ops = &rcar_gen3_phy_usb2_ops, .no_adp_ctrl = true, .init_bus = true, + .pwrrdy = true, }; static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { @@ -707,6 +718,55 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) return ret; } +static void rcar_gen3_phy_usb2_set_pwrrdy(struct rcar_gen3_chan *channel, bool power_on) +{ + struct rcar_gen3_pwrrdy *pwrrdy = channel->pwrrdy; + + /* N/A on this platform. */ + if (!pwrrdy) + return; + + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, !power_on); +} + +static void rcar_gen3_phy_usb2_pwrrdy_off(void *data) +{ + rcar_gen3_phy_usb2_set_pwrrdy(data, false); +} + +static int rcar_gen3_phy_usb2_init_pwrrdy(struct rcar_gen3_chan *channel) +{ + struct device *dev = channel->dev; + struct rcar_gen3_pwrrdy *pwrrdy; + struct of_phandle_args args; + int ret; + + pwrrdy = devm_kzalloc(dev, sizeof(*pwrrdy), GFP_KERNEL); + if (!pwrrdy) + return -ENOMEM; + + ret = of_parse_phandle_with_args(dev->of_node, "renesas,sysc-signal", + "#renesas,sysc-signal-cells", 0, &args); + if (ret) + return ret; + + pwrrdy->regmap = syscon_node_to_regmap(args.np); + pwrrdy->offset = args.args[0]; + pwrrdy->mask = args.args[1]; + + of_node_put(args.np); + + if (IS_ERR(pwrrdy->regmap)) + return PTR_ERR(pwrrdy->regmap); + + channel->pwrrdy = pwrrdy; + + /* Power it ON. */ + rcar_gen3_phy_usb2_set_pwrrdy(channel, true); + + return devm_add_action_or_reset(dev, rcar_gen3_phy_usb2_pwrrdy_off, channel); +} + static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) { const struct rcar_gen3_phy_drv_data *phy_data; @@ -763,6 +823,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) platform_set_drvdata(pdev, channel); channel->dev = dev; + if (phy_data->pwrrdy) { + ret = rcar_gen3_phy_usb2_init_pwrrdy(channel); + if (ret) + goto error; + } + if (phy_data->init_bus) { ret = rcar_gen3_phy_usb2_init_bus(channel); if (ret) From patchwork Tue Nov 26 09:20:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 845711 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E48931BA86C for ; Tue, 26 Nov 2024 09:21:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612889; cv=none; b=uJkPLePSN5R4aztZBi3GN0wuDjGuQPyXgO17WcfOW4qdhN+04LpBQo38dd0Zgc8mdP7Ehm/jOQrV4KMJw0KQdy+pSw6YuT5swOcf9KR0Sw+APGCpeGNPZBMuFdcyN4QGCte8wzT5jRpAAN3MN7oL2n3y1wt57u0ymb0UtP7r0vI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612889; c=relaxed/simple; bh=pvmXne3/GLaL56C23pmxfpzVcVguFUnVL4SSDyD6KWQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RuUWj8NJEPjfC1Sfoqcjr8hb0bNXFle352fzPYuMI2U3XPJtNyuwb4P6XbFFLj7TDKSr7Pee5K1rI5Dc8U+zC1hlN3VrT01m1wxgfzGkWUejTaAZSBsVICV2o95yadb39yNk+hYv4PuBggUDvrIXgiwpKB4MAE8VgtYJL8p35qY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=ghPR0LO2; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="ghPR0LO2" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-434a83c6b01so928025e9.0 for ; Tue, 26 Nov 2024 01:21:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612886; x=1733217686; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E4M5g4cOSJdZAIQtrKw1Bn/YMzw7ikJ/cpvkoOSwCx8=; b=ghPR0LO2pC6YkkfzaTqUNsLDZUcp9bERyEyb9YOZEMdOiWVbT9ZUFiF4YmBxMB+D0h Oub/hGH9PTI18stx8oUicM9Zv//kTIHFTaJtBABe/I3aRfGmPoLTemuM3YvtiS+7KenF 4etSN6/T1d+xHmpNRl2gQ2wJflLDShKIhTM8DEsq3IEBl+VW2rNNIJ6/mP5pXZ7lH5k3 lWbWjKdZZaU3XAhS2/3vObsoLDHHN/fZ+64m0/8cHOgfGUhrCaE+r/ZFB9lpkc6CP6c0 OGv6geeuXZTSrY93GlZvKwdyTt3Hn4StKrUnGsFGMOsPjmoCujOlRkDXis81DAb8yqy0 s1TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612886; x=1733217686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E4M5g4cOSJdZAIQtrKw1Bn/YMzw7ikJ/cpvkoOSwCx8=; b=GiQlV2PahP9I3xVFALmzkaIyZbenU30wjAqM01GUbfeoOvzVQvv60asFjWzcJWv9sy +6LrG7PQ5XVJY0Zr/lciTsiRlqikoAC4slfu9Z7w8JFBIRDGJY7DSMmANunjhsPMn5OZ slbrV2r01js33mrpCyNl6Ovy+qVjhY8QTvXOU4FNCqTtNKMXHEaKqik0pbcvIpDL1F1m 2p4435PyNfoeFLCeh+H3+OEPRwsLkROSDFCOda2/cpeMDdK9bSbbhLB3GibvsG5dnJ3y 8+6BRRM6ky5/v6iFmcwbD0HkH9wC1Ory8cz4y8o82zM2OKaUpyY8vJJOaJkYk3XahROX s3XA== X-Forwarded-Encrypted: i=1; AJvYcCUN2ErPEtwLhTDemXFTjt6DljVV2/KIBgG9FCB6Feq/hOKU5oYnDLQBgu9eXFsOBwboqyJQNmJmAjM=@vger.kernel.org X-Gm-Message-State: AOJu0YyyXF12T9hegSONpGQdJ96teNAHPEPkzZr6tolrrK5I93Jcze4/ X4j/iWVuPtY3ELaKQR0x4vietvXOwpPTuNnuhxEhNf4L+inem6yN4Sj1done988= X-Gm-Gg: ASbGncuDSmNRAbdow+vnNVmt+siuXYigOTl7B75+L4wtcm0c+tig7hgAuvCs+BljuA4 IAWfwUJzEgnywqtX3xafOfCSE9GP2zbD2CUU9pW0HPKNxeWgO1jZDY0Knsi2PAb3A8eCL4q+56H CCTL5mexvgAvxMRJFzsQdID9Ktm/Za9Awpe0dpz6Zn+eFEWo7UBXvKHJVcKAx6l1ntVlh2hhb5k ofWVTbhyiP8uyFW67BBWrnykgb97ZUslxB2MyM3Gsg4R38G9Maxm1fHQ7gqoGqNlDVkdYzbmCzN eq0= X-Google-Smtp-Source: AGHT+IFFCuS7xBS3otNkuGr2IzoMyH/CTvsuJMT+O34OiuKVD91ks7D0BrVopsaLaBF4QZUasDuXXQ== X-Received: by 2002:a05:6000:18ac:b0:37c:d1bc:2666 with SMTP id ffacd0b85a97d-38260b502dcmr12951812f8f.4.1732612885919; Tue, 26 Nov 2024 01:21:25 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:25 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 12/15] arm64: dts: renesas: Add #renesas, sysc-signal-cells to system controller node Date: Tue, 26 Nov 2024 11:20:47 +0200 Message-Id: <20241126092050.1825607-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The system controller on RZ/G3S can provide control access to its signals. To enable this, add the #renesas,sysc-signal-cells DT property. Consumers can use the renesas,sysc-signal DT property to reference the specific SYSC signal that needs to be controlled. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 593c66b27ad1..2ebb951e6a39 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -585,8 +585,9 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g043-sysc"; + compatible = "renesas,r9a07g043-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6b1c77cd8261..9dd229cbf288 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -877,7 +877,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g044-sysc"; + compatible = "renesas,r9a07g044-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -885,6 +885,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 01f59914dd09..31550b8c3143 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -884,7 +884,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g054-sysc"; + compatible = "renesas,r9a07g054-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -892,6 +892,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index be8a0a768c65..169561386f35 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -198,7 +198,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a08g045-sysc"; + compatible = "renesas,r9a08g045-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -206,6 +206,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; From patchwork Tue Nov 26 09:20:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 845710 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D6031D5CEE for ; Tue, 26 Nov 2024 09:21:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612893; cv=none; b=dHeenpO5k++h/HuBuPL+uI4BjSNt/kk03kjOu6ANMKxne1VKdwLK4WDQExR+QR/0yKbHZnKuHPgj8nTn1tk5cmTJSPej5UA6fFxnFEgaAWoxkbe46QebVpHjmfiHfXBbmGYb6SM/mslS9Pwa/F/UoTH5tu2DwfHUCT/T1yDEBAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612893; c=relaxed/simple; bh=2DMTJUAMbvgwMO6a642uq7ua8fsNBEbd1Oxy7nZyQa8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hQcta+ZPYlvOMWuTohqx6AVJYEhdTNypXNR5EYhaXNF4jJstrAJuQq4lOdLGOc2/DlyzPHRbjRFmaYiYDVAlOOn/FHCR1lZ8BaEfuKiOXjZMyTIg1Zob3CBBA3Y/D9ikhZVuFo0QYGdelDEbPgWimvSPpTf6je2T7mO7lspHhXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=GHKxhmxe; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="GHKxhmxe" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43169902057so47396675e9.0 for ; Tue, 26 Nov 2024 01:21:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612889; x=1733217689; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qLdnHZoveqIvO5Hl0Ml7DeyDrz+2Vaoq4NvOVCNrZ/A=; b=GHKxhmxesIrI/tdCGHSbmOfQHu6ELwNJAb70ipA17qFwm1GMQH19ccoVbHToRt9Csd 8ZMaa8o9HGLQMySu7g+3G35vE56oMEIkRSZwp/gwiUQTNyOb6Zv0y+J85OrZfkT4K9KD On+9M8MDYDVrBBmofSaeo+X6YOUyTX4PIKCxqhKrNeQPoKffc+oATZ1anrOorshIcM00 d9icarOpmzQNPzRMOOC/h+Ae6rtjfLsOlzBvmmm6QiJ+8cZroT13MoZiWwIytjRS26kY TTZgblhCkoouhIJmS3cglEKtKdQbv38tWxcK9L/teWhzlrUDatIygv/HU1BWOQpP/TnV ZPTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612889; x=1733217689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qLdnHZoveqIvO5Hl0Ml7DeyDrz+2Vaoq4NvOVCNrZ/A=; b=o9oDP95mIw58Fam/gEezAaUzk7P7tIciDHX56+rFx/oeCY78CLGbyLaqpJk7T0q7z+ 7QGHFjalzLx4Q9JCpMNQ0X3PHYRGsB87Ci9fKgnGah2dAxnCabrSriCL68JnhbPlXbrJ Jxn91vvn3VuIQR12u8E15dd+ga44Y7a9FqfanrsBecRfgw1CGKuubVWdHqs6i7t3aknq Zt9Z+A193mmdBWQPli/ZwgZC9r5hza39+9ZOfetfZs2W0D9O5MA7TrvqguKvhUuQnZUd fqRofJuJxwQENHB/HwvlZ1g4XMunkicV5AGFqEdD8KyhS0mbp1u5TDEuxQUoOBVewJIS lcVA== X-Forwarded-Encrypted: i=1; AJvYcCWJ48rWfW0CdEPVa969AlL60jrDnbOuVPeAd7Nl/WqDxuXw+WlXaP9G9ft0gcnerzv5AC4pUoYSz4A=@vger.kernel.org X-Gm-Message-State: AOJu0YxQ0N8+fHxGT2dh+MYbNwpkPNxvHzBx5hCmZTXwD3vBeigUY+XN 4YN+lqgsDVSuKiOcLGyktFKFJnIhf/F7r9OYbWL+aZbjUhkUu6BoTlbPbAf0KmM= X-Gm-Gg: ASbGncvYmODrC1x8qfTYMpksGTgSi6xYOfuw8knyWsqp9FEHoN8CLptkcHq2b+BrKaa DfmwP0/3P/9cylVCB8Uyspi9GQfVdYpwoPH0S49MTckmSP0M8/u/kycu8tkDgkHaoZD94Q2c363 jtzXZKjKhy9B8gr8SoemJYWqv5AFOEOi3NGIqOM0LCismBHfOoljcRzLKletZ/y53KrbzCxm/Aq wEKYCTj1gZnnHpmmiOF+1kyNJ3sC04+FOJr0iklm8dzY5uy7OLqS7u4pjajwyGFiIzAuI4qM1jj S7E= X-Google-Smtp-Source: AGHT+IFJiTv231Q0pA7mNGDg8+ehro7YZHPIBfZNFr1G9xSWhy4hE646eb2huz0yqoJ24h09vlKStA== X-Received: by 2002:a05:6000:1acc:b0:382:450c:2601 with SMTP id ffacd0b85a97d-38260b6b632mr11281224f8f.24.1732612889501; Tue, 26 Nov 2024 01:21:29 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:28 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 14/15] arm64: dts: renesas: r9a08g045: Add USB support Date: Tue, 26 Nov 2024 11:20:49 +0200 Message-Id: <20241126092050.1825607-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 14/16 in v1 - added renesas,sysc-signal properties to USB PHYs - collected tags - Geert: I kept your tag; please let me know if you consider otherwise arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 89cf57eb8389..6ce94bbecfa6 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -417,6 +417,125 @@ eth1: ethernet@11c40000 { status = "disabled"; }; + phyrst: usbphy-ctrl@11e00000 { + compatible = "renesas,r9a08g045-usbphy-ctrl", "renesas,rzg2l-usbphy-ctrl"; + reg = <0 0x11e00000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets = <&cpg R9A08G045_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible = "generic-ohci"; + reg = <0 0x11e10000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11e10100 { + compatible = "generic-ehci"; + reg = <0 0x11e10100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e10200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + renesas,sysc-signal = <&sysc 0xd70 0x1>; + status = "disabled"; + }; + + hsusb: usb@11e20000 { + compatible = "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg = <0 0x11e20000 0 0x10000>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11e30000 { + compatible = "generic-ohci"; + reg = <0 0x11e30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11e30100 { + compatible = "generic-ehci"; + reg = <0 0x11e30100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e30200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + renesas,sysc-signal = <&sysc 0xd70 0x1>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;