From patchwork Thu Dec 12 12:51:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 181467 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp844258ile; Thu, 12 Dec 2019 04:51:42 -0800 (PST) X-Google-Smtp-Source: APXvYqw/J1/lIZK1uYQF5FyMMNgp92T5M8WNHdKGKSxGfgJCKSrD5LT3x3dxoGMVnmaKcY9bxqQR X-Received: by 2002:a05:6830:1415:: with SMTP id v21mr8325271otp.188.1576155102909; Thu, 12 Dec 2019 04:51:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576155102; cv=none; d=google.com; s=arc-20160816; b=aiVJagazMY9ElZYktU+NGCx/lKyNFxFPrmEGaiDB/h0TSEMadlrmzFzBM6fCg9d2+c VjQWGdAp9Rp3Jdy+in0r0Ui2hm1ZNwCwQHXDr7AukNJsHQimCKE4s8JSJSi5xZ9Fopue uqJYy8hB9OifkznPl4BV0pfYtyD5yIvk/D+r4fQRckHmA3ZROv3HMqmihwYMWpm70NzM N51B7SvjL0+uOYX16LiKu6xroWvQOp7TGtC/88BIU01pJNOu/HHMpg4NkYTMKvdH4uQE +vrQ2ntP4jUvbOla6K4rsVkZaRxiT9VMtg+Z12ZhC2iekkL9zN6sX4tujf2OmNH5rfAD 2vcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=gdGNt8Bd4D3tOazg61iqzY4jL5JivnDdetottPmFFxY=; b=KEnxQsPXHXbo2IC8clFQ4Fis+YBocACvMafF9oXoJliA74kaby2CzQ3qdNLNzXJ685 jGC/pJSlHc8zqKsat9YbxH7seUYbPpoOdvEvTFXM9bxuKlqlrJ71elt02nj1dUPaFNJh ZhLGQQW82CYjW+f6SREPNlntzZwV+MVSBF/20BV45bolO9WvhRDuZ51VZjV4JnJONZho CYlJPb4syaDt8Rjr7YoJWHbEjVz7TRq5eG8ld8d4LjfmxcUFC1KhnSiD1Dbz6viGs1gj SQTUDVIJYoj6iVr1tBQZDc6WLj+erL/zccrTcH7ybSTGFfQ4p8Wf9M/VkAuLi+3CyC2e 6s0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QQioPlm4; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l9si2788631otn.301.2019.12.12.04.51.42; Thu, 12 Dec 2019 04:51:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QQioPlm4; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729207AbfLLMvl (ORCPT + 8 others); Thu, 12 Dec 2019 07:51:41 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33150 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729244AbfLLMvl (ORCPT ); Thu, 12 Dec 2019 07:51:41 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpcik042262; Thu, 12 Dec 2019 06:51:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576155098; bh=gdGNt8Bd4D3tOazg61iqzY4jL5JivnDdetottPmFFxY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QQioPlm4nrA3Zp3Oa39HxQmO7w766wFe4UECAGDEJwzxV0wgOUyVC6Uv3KoJy0WOs jnF3ONRE4dY/4n782cZT3dJmaJUM7dV/kiechDhGNS2Nbf5wekkFo3M1wwG2GEoJCD IvEIPazpB90t0ahbjaGvN/PNVDfJywwDW8lJP+V0= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBCCpclk078393 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Dec 2019 06:51:38 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 12 Dec 2019 06:51:37 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 12 Dec 2019 06:51:37 -0600 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpWNe045158; Thu, 12 Dec 2019 06:51:36 -0600 From: Tero Kristo To: , CC: , Subject: [PATCH 2/6] ARM: dts: dra74x: convert IOMMUs to use ti-sysc Date: Thu, 12 Dec 2019 14:51:19 +0200 Message-ID: <20191212125123.3465-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191212125123.3465-1-t-kristo@ti.com> References: <20191212125123.3465-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert dra74x IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra74x.dtsi | 71 +++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 16 deletions(-) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index d1b5b76bc5a8..c5abc436ca1f 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -66,24 +66,63 @@ }; }; - mmu0_dsp2: mmu@41501000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41501000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - status = "disabled"; + target-module@41501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x41501000 0x4>, + <0x41501010 0x4>, + <0x41501014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp2 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x41501000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu0_dsp2: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x0>; + }; }; - mmu1_dsp2: mmu@41502000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41502000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - status = "disabled"; + target-module@41502000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x41502000 0x4>, + <0x41502010 0x4>, + <0x41502014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp2 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x41502000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu1_dsp2: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x1>; + }; }; }; }; From patchwork Thu Dec 12 12:51:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 181466 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp844251ile; Thu, 12 Dec 2019 04:51:42 -0800 (PST) X-Google-Smtp-Source: APXvYqyY2KlPBWLbPFy8NKBPA82npjDeIIGWoV1UENTsmFjdPmhvGuDfsmqsw9+SHs3CxLAD2Pwr X-Received: by 2002:a9d:7e99:: with SMTP id m25mr7673152otp.212.1576155102367; Thu, 12 Dec 2019 04:51:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576155102; cv=none; d=google.com; s=arc-20160816; b=EOpCe4y6/qMiUH97YclvABLoqf5hQ3zqAiub5WHcvqojIzpvNUaj7SDSqDNKJAVqAi VYgQBUy1RhJaIJfknql5XZpWgnyFsoXV5MAdJGEOpMa/Q+thOkKCZNrhYuaezjbg71b7 LRM1xpOnQDMDB8Qz5KGE6X0uTFRQ2DfDbdev3lxX+4tPSQWZQ7BHjgl/Bn4B1r7F1H5w NAfn9ju5UKh0v+ARVvTZKjYPwFqt1rJHDGbz4vuRBtM73rEB+oSod9Lyp7nmFfUKmDW4 zgejFSB52tPeHZK95scTcqxj9iJVeYnSjqdO+W3IjJcGa8exjMzZCEAw6aIWeinvbGvI Ke6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TEr6SScWfvJ0lJeE6Waov2g8ftJ41ES/0yvum08aSVs=; b=wiV5oPVjDU463U3L4DUPE/lOwQyxBJwACLhgtQltfLVI7oewosBa7Oohksg+KZ5wSR aUXVN7UbZN7DpIAgumQEWDQoIL6rf1z7lez9hl55PO5AHv3RLa1uKeYYbXfa5k/lBHZU gHSZNQLWlUIaFiKJLAHEV4gTKl3XiLW1dbWR0jTPo+z9AIyNV/iiNJvadAcZ1fZyIUvs 248yXjlPFz3V39yvCa+EmtVY5GCx+R74mwCDdy9cKUoW8k2PPSCPN8qEvz5dAOlAYkq5 /ZRliPyFwmvOFZBHdFljaQy5UrRT3A5cbFDnzlZYcxcvSWq/kQzmldRpqd+n+EiZuF+d bvHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EXWxqrNt; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l9si2788631otn.301.2019.12.12.04.51.42; Thu, 12 Dec 2019 04:51:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EXWxqrNt; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729272AbfLLMvl (ORCPT + 8 others); Thu, 12 Dec 2019 07:51:41 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49186 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729252AbfLLMvl (ORCPT ); Thu, 12 Dec 2019 07:51:41 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpdoa109099; Thu, 12 Dec 2019 06:51:39 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576155099; bh=TEr6SScWfvJ0lJeE6Waov2g8ftJ41ES/0yvum08aSVs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EXWxqrNt40U3Tu9Fw8Q7ee8LR76D69WKe04YQu2DHZMpXHbN1MvKzHvzK8vIN3Nwl 6IJrCUdJxt1NbBO0gWyN29C9dWoTQfUZeHhnI75vRyV4w3I0Y3Kgzlj/t7HUi4NFaI 1t3LR284ji750+SQTzWKumX2RvbkiCdOmiZMJq7U= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBCCpdno078400 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Dec 2019 06:51:39 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 12 Dec 2019 06:51:38 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 12 Dec 2019 06:51:38 -0600 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpWNf045158; Thu, 12 Dec 2019 06:51:37 -0600 From: Tero Kristo To: , CC: , Subject: [PATCH 3/6] ARM: dts: omap4: convert IOMMUs to use ti-sysc Date: Thu, 12 Dec 2019 14:51:20 +0200 Message-ID: <20191212125123.3465-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191212125123.3465-1-t-kristo@ti.com> References: <20191212125123.3465-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert omap4 IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap4-l4.dtsi | 11 ++++++--- arch/arm/boot/dts/omap4.dtsi | 43 +++++++++++++++++++++------------ 2 files changed, 36 insertions(+), 18 deletions(-) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 83f803be8ee2..8a76b6b86a97 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -321,7 +321,6 @@ target-module@66000 { /* 0x4a066000, ap 25 26.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmu_dsp"; reg = <0x66000 0x4>, <0x66010 0x4>, <0x66014 0x4>; @@ -335,12 +334,18 @@ /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; clock-names = "fck"; + resets = <&prm_tesla 1>; + reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; - /* mmu_dsp cannot be moved before reset driver */ - status = "disabled"; + mmu_dsp: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + }; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2de8a6b53de9..af901fc6e909 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -173,14 +173,6 @@ #gpio-cells = <2>; }; - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; - target-module@52000000 { compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "iss"; @@ -206,14 +198,35 @@ /* No child device binding, driver in staging */ }; - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + ranges = <0x0 0x55082000 0x100>; + #size-cells = <1>; + #address-cells = <1>; + + mmu_ipu: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; + target-module@4012c000 { compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "slimbus1"; From patchwork Thu Dec 12 12:51:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 181468 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp844275ile; Thu, 12 Dec 2019 04:51:44 -0800 (PST) X-Google-Smtp-Source: APXvYqyzsVcTmmtwYo7uUXwBd7Asa5i3kMXklhJgr3SARAQkTJQlL/tq84LvBmDoSBLivcLNZZg6 X-Received: by 2002:a05:6830:18ce:: with SMTP id v14mr7412822ote.254.1576155104152; Thu, 12 Dec 2019 04:51:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576155104; cv=none; d=google.com; s=arc-20160816; b=Z6ET9B4vxfqMNeJolRJ0grlmff0xcDaS4JFqhsysf5Q/Ig1mcYm4I4BXZoSBoindJJ yw2idTd2b+Yu06wY2UDD19tWKXPjb058amlvVTs+uvriRTwss6EqxW0GMECCzKxHFyuK 9pB7Nyo9bxSxc/YGpx/R1yH0ZDa69YKb+hI2B29fzpPzebuLsQfiU/j52NLJQyzmJQQy Jv85SlKtb3S9CT1Rq6x0Zhkzwpo5vTW8qQnjXQcz4Te5vpTe3P0pJBhu4GwirDIu9exU gLcl4jI4BqsT7wNcXtYf4FvpkMqP0XOwuIJmB3yc4sjfkeVvhD39RXB98JOMWqdmLqeS W+BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0eKKUKb1+FCo4Bz8Ve5JRVMU/HQLBZnzbJ1HqqzcI/A=; b=X2vw/FSlL+sqcPIUT87Nhh1sZtZe8Oh0Y15zcTPRVKlqNRl9uWW458Ry27gi3byWSU ivQE1kXj4LG+7i3DdKuYuHAgroyC5Jkr1XkD1ed3xORPVI53FOfR0S5Dw7OvblZmz1MJ 55F8d3pcIr0gzRC4K7N1NpjOAjVmNxxO9yqAGvaVEu+9vOeBlv4tpm31QeY0//GtBTC6 wMyD0NMWtMJ63IGB+g6SUyBaUvNOoKj0RttYpHybI0fR6JEZhANP1pVjPPHlAWuRhIUZ +Rk6sbPbpTfpAf0jOO35kfaoMjsEwA60d3KaPN7nKF9WSq5zjBzT6a4B7Fl4IZ5iZgcz T0/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FxcX5Lpp; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l9si2788631otn.301.2019.12.12.04.51.43; Thu, 12 Dec 2019 04:51:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FxcX5Lpp; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729285AbfLLMvn (ORCPT + 8 others); Thu, 12 Dec 2019 07:51:43 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33158 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729244AbfLLMvn (ORCPT ); Thu, 12 Dec 2019 07:51:43 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpe0a042272; Thu, 12 Dec 2019 06:51:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576155100; bh=0eKKUKb1+FCo4Bz8Ve5JRVMU/HQLBZnzbJ1HqqzcI/A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FxcX5LppZlvT1fJE1djKQ03g406Dp3pFJZ9fir9vNMAba8BzoTSwRb8bOlLVNyE5i h78LM1UGlZsSjn6QLaCRgkJGJBbv+CzijXkyV47HfUHoLBDQUT7dBoHhEOco3LZ+vA GXvCWnkNRoeLYuWhkCWY7iWyJg/DBeWDYf0RuBbY= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBCCpeU8033980 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Dec 2019 06:51:40 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 12 Dec 2019 06:51:40 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 12 Dec 2019 06:51:40 -0600 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpWNg045158; Thu, 12 Dec 2019 06:51:39 -0600 From: Tero Kristo To: , CC: , Subject: [PATCH 4/6] ARM: dts: omap5: convert IOMMUs to use ti-sysc Date: Thu, 12 Dec 2019 14:51:21 +0200 Message-ID: <20191212125123.3465-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191212125123.3465-1-t-kristo@ti.com> References: <20191212125123.3465-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert omap5 IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5-l4.dtsi | 11 ++++++--- arch/arm/boot/dts/omap5.dtsi | 40 +++++++++++++++++++++------------ 2 files changed, 34 insertions(+), 17 deletions(-) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 25aacf1ba708..a29261dea3e2 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -349,7 +349,6 @@ target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmu_dsp"; reg = <0x66000 0x4>, <0x66010 0x4>, <0x66014 0x4>; @@ -364,12 +363,18 @@ /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; clock-names = "fck"; + resets = <&prm_dsp 1>; + reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; - /* mmu_dsp cannot be moved before reset driver */ - status = "disabled"; + mmu_dsp: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + }; }; target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 1f6ad1debc90..d0ecf54d5a23 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -186,21 +186,33 @@ #gpio-cells = <2>; }; - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + ranges = <0x0 0x55082000 0x100>; + #size-cells = <1>; + #address-cells = <1>; - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; + mmu_ipu: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; dmm@4e000000 { From patchwork Thu Dec 12 12:51:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 181469 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp844353ile; Thu, 12 Dec 2019 04:51:48 -0800 (PST) X-Google-Smtp-Source: APXvYqz0QATZGDHOoW5SR9761gqCc3LPD2y4xq/4LTC9fU+OfGzGwifyWvwMaMhXPto0QQDXCCML X-Received: by 2002:a9d:600e:: with SMTP id h14mr7661739otj.113.1576155108628; Thu, 12 Dec 2019 04:51:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576155108; cv=none; d=google.com; s=arc-20160816; b=pYrk4xV6DWsYf3b+Slw2QhwAQjOx4UB1NEmXdttgB/EF3HyNa9C5rZkFGmQXFCy1El tUjDscOtWOL681bUno5m0WageQe/VlSYe+VPatHFOS68w4zpFhZO+AQ0Zww6cqCZtCs7 nWg3XRI3/EH0r6U4SxgGEIRxZuLl0n6ChRtksECgNwNczPwPfBsK3LmIKSMZp+zfLHOu vxoEdQFCtvgOUs0loaqEKus2o3SIuqyZJu6WdkSZYJXuRD9MAQd8d+42RWEWiEyGe996 bl4tgfkJe8bpAx0rSUkS1cD5avWMhmJseOqo20LtT/5IusAgQ918IWAmg/bsBMIuH3J2 c+yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7Pu2Rw8bMwPn39DS0Vo9UroAA0vBhw1LWwnqjEokdtg=; b=usRIymRIzCVV/7Va7UW2QN9w6ECdFTCxuBEw/TnqiG1CF9Y/4GJIHOPVU607HDJCP+ FxH8SF3lUPxYY8JtiXKtFM7cMIfRSQKUpyvpiv1naiLN+CIrdBSfiFdD/qk6b0L7nDDC VU/f3ZlvyP5I1d9PC2wZGK/G/Mxs5ey+/O5ox0r1F1x2gskb+HAF3lnsc7nGzV24UrdN M5Ac4aUSH2ISDVGn43ijpXQmWZranq68F1l9b77Q1BGGDT5uB4dCT5xWQIWbZZ+uUuSc pNDdubX8GbbrYBqrcCpW7fMvx8iusj3KJFEjOZZevlBSMlXmLzGcaTTLnbauZnRCdSXk aW3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RhsyYoUs; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h139si2970746oib.85.2019.12.12.04.51.48; Thu, 12 Dec 2019 04:51:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RhsyYoUs; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729311AbfLLMvq (ORCPT + 8 others); Thu, 12 Dec 2019 07:51:46 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33162 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729244AbfLLMvo (ORCPT ); Thu, 12 Dec 2019 07:51:44 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpgJ4042292; Thu, 12 Dec 2019 06:51:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576155102; bh=7Pu2Rw8bMwPn39DS0Vo9UroAA0vBhw1LWwnqjEokdtg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RhsyYoUs25VsJPUKtrvAk/uEOpob4xn0Py4JnP+BwoRuVTGIrC0tJpG97Q5yqePVp 1e+qct8vCGYalvu4pDuXjQfBkQgg+H4psDgq2fuDkp5nWuhJHbbUJaoTiKHdhvSxu2 iV6gK6icHoqJKsBZ83LSsyHIi7zavKw001jSyxfE= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpgxP017628; Thu, 12 Dec 2019 06:51:42 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 12 Dec 2019 06:51:41 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 12 Dec 2019 06:51:41 -0600 Received: from sokoban.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBCCpWNh045158; Thu, 12 Dec 2019 06:51:40 -0600 From: Tero Kristo To: , CC: , Subject: [PATCH 5/6] ARM: OMAP4: hwmod-data: remove OMAP4 IOMMU hwmod data Date: Thu, 12 Dec 2019 14:51:22 +0200 Message-ID: <20191212125123.3465-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191212125123.3465-1-t-kristo@ti.com> References: <20191212125123.3465-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IOMMUs are now supported via ti-sysc, so the legacy hwmod data can be removed. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 87 ---------------------- 1 file changed, 87 deletions(-) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 292f544bd62d..8196c5b3e736 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1303,91 +1303,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { }, }; -/* - * 'mmu' class - * The memory management unit performs virtual to physical address translation - * for its requestors. - */ - -static struct omap_hwmod_class_sysconfig mmu_sysc = { - .rev_offs = 0x000, - .sysc_offs = 0x010, - .syss_offs = 0x014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { - .name = "mmu", - .sysc = &mmu_sysc, -}; - -/* mmu ipu */ - -static struct omap_hwmod omap44xx_mmu_ipu_hwmod; -static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { - { .name = "mmu_cache", .rst_shift = 2 }, -}; - -/* l3_main_2 -> mmu_ipu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_mmu_ipu_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { - .name = "mmu_ipu", - .class = &omap44xx_mmu_hwmod_class, - .clkdm_name = "ducati_clkdm", - .rst_lines = omap44xx_mmu_ipu_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), - .main_clk = "ducati_clk_mux_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, - .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* mmu dsp */ - -static struct omap_hwmod omap44xx_mmu_dsp_hwmod; -static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; - -/* l4_cfg -> dsp */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_mmu_dsp_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { - .name = "mmu_dsp", - .class = &omap44xx_mmu_hwmod_class, - .clkdm_name = "tesla_clkdm", - .rst_lines = omap44xx_mmu_dsp_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), - .main_clk = "dpll_iva_m4x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, - .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - /* * 'mpu' class * mpu sub-system @@ -3012,8 +2927,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_2__iva, &omap44xx_l4_wkup__kbd, &omap44xx_l4_abe__mcpdm, - &omap44xx_l3_main_2__mmu_ipu, - &omap44xx_l4_cfg__mmu_dsp, &omap44xx_l3_main_2__ocmc_ram, &omap44xx_l4_cfg__ocp2scp_usb_phy, &omap44xx_mpu_private__prcm_mpu,