From patchwork Wed Dec 4 11:33:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 847401 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFE431B3949; Wed, 4 Dec 2024 11:34:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733312065; cv=none; b=jXPmeKvZNZfG+7+Etrirk/BpcgvdHPxzCOxn7YgQfBmoYYiVEWF25Djk/u/yMvQna+g3zWDdhlRg3sjXg+GGo0MDA4CuVixFbCPAfgZHntluEsWx6QVC+xV9Lxk4tx8i0BWcXHpHtgaRaJUn51Y9q8+H99nDj1/RiivU1WC+YEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733312065; c=relaxed/simple; bh=88R3oZpZD2GGre1fQgu5Hm7bLT5jQHV+juSUuD/h95M=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Y9TOE5+JSfXCCGCW0oVtq6CfXT7CydflKZpUtm44Mdgw44IJu7vMqVJNVaVFDaBSHXkMB+WEiojxVX9IHbZ1NjaOJjsXqf84LUnJlt9QAdxE3/MFkXCV1yKglV+N+Eg4h7+PSZ/2pKZt9lTTfVLrOuWhLya+2/m9pm65/xlJ3pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ViRJLWhq; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ViRJLWhq" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B46VUdf027853; Wed, 4 Dec 2024 11:34:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= N8CUwHXxrU17uvgVXAnoIjuNWJ3qOKuQzRThwkLdcs8=; b=ViRJLWhqzsJLxGVE QuUCyq/YaX+b+p59UB7wf+ZljaJmKqig6VIvOgJ5duGM7wxhCJI+uBBsSRT4AsgH 1xkAMM/PzFniVtM+TsGZr40GIcDxighzq2GQyes7Xi4Uae4wFmJxOQ8lGAwYlAL8 Pt5kY6fEytOY8g3KqFrb6NjtIJ9KH/Khjwbp9mzSTP3g4TmPAtwkCYRngPcKrVp8 1CINJiA/L5Fch4Bmw5aIaO+9NOv0giulWXTcY2o7VSYFM6Tv5V1PJIsdgQy4gCAZ KPpjGLbe3JDK+XYCeBaq6dtkmK10UU87qGKja71oMu2hKXvSFPpDinGdVqmHy8NT lQSb1A== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 439vcem6p9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 11:34:10 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B4BYAQs013129 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Dec 2024 11:34:10 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 03:34:04 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 1/6] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy Date: Wed, 4 Dec 2024 17:03:24 +0530 Message-ID: <20241204113329.3195627-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204113329.3195627-1-quic_varada@quicinc.com> References: <20241204113329.3195627-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7BVsC1c6Q3mq0Rd6uvdh0O7ul90mENF4 X-Proofpoint-ORIG-GUID: 7BVsC1c6Q3mq0Rd6uvdh0O7ul90mENF4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 phishscore=0 mlxscore=0 malwarescore=0 clxscore=1011 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040090 From: Nitheesh Sekar Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. Signed-off-by: Nitheesh Sekar Signed-off-by: Varadarajan Narayanan --- v2: Rename the file to match the compatible Drop 'driver' from title Dropped 'clock-names' Fixed 'reset-names' -- .../bindings/phy/qcom,uniphy-pcie.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml new file mode 100644 index 000000000000..e0ad98a9f324 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,uniphy-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY + +maintainers: + - Nitheesh Sekar + - Varadarajan Narayanan + +description: + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + +properties: + compatible: + enum: + - qcom,ipq5332-uniphy-pcie-gen3x1 + - qcom,ipq5332-uniphy-pcie-gen3x2 + + reg: + maxItems: 1 + + clocks: + minItems: 2 + + resets: + minItems: 2 + maxItems: 3 + + reset-names: + minItems: 2 + items: + - const: phy + - const: phy_ahb + - const: phy_cfg + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - resets + - reset-names + - clocks + - "#phy-cells" + - "#clock-cells" + - clock-output-names + +additionalProperties: false + +examples: + - | + #include + + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-pcie-gen3x1"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + reset-names = "phy", + "phy_ahb", + "phy_cfg"; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk_src"; + + #phy-cells = <0>; + }; From patchwork Wed Dec 4 11:33:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 847400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C6201B3929; Wed, 4 Dec 2024 11:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v2: Use ipq9574 clock & reset details instead of a new one for ipq5332 --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index bd87f6b49d68..a7c5d0ce7de8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -163,6 +164,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 - qcom,pcie-ipq9574 @@ -407,6 +409,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq9574 then: properties: @@ -555,6 +558,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 From patchwork Wed Dec 4 11:33:28 2024 Content-Type: text/plain; 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Wed, 4 Dec 2024 11:34:34 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 03:34:28 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , CC: Praveenkumar I Subject: [PATCH v2 5/6] arm64: dts: qcom: ipq5332: Add PCIe related nodes Date: Wed, 4 Dec 2024 17:03:28 +0530 Message-ID: <20241204113329.3195627-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204113329.3195627-1-quic_varada@quicinc.com> References: <20241204113329.3195627-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: i-yFGzdANQFUr5MH-PTOt9SMfLlni_6w X-Proofpoint-GUID: i-yFGzdANQFUr5MH-PTOt9SMfLlni_6w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 mlxscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040090 From: Praveenkumar I Add phy and controller nodes for pcie0_x1 and pcie1_x2. Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v2: Fix nodes' location per address --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 214 +++++++++++++++++++++++++- 1 file changed, 212 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index d3c3e215a15c..bf87f44461fa 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -186,6 +186,46 @@ rng: rng@e3000 { clock-names = "core"; }; + pcie0_phy: phy@4b0000{ + compatible = "qcom,ipq5332-uniphy-pcie-gen3x1"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + reset-names = "phy", + "phy_ahb", + "phy_cfg"; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie1_phy: phy@4b1000 { + compatible = "qcom,ipq5332-uniphy-pcie-gen3x2"; + reg = <0x004b1000 0x1000>; + + clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X2_PHY_BCR>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>; + reset-names = "phy", + "phy_ahb"; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; @@ -212,8 +252,8 @@ gcc: clock-controller@1800000 { #interconnect-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, - <0>, - <0>, + <&pcie1_phy>, + <&pcie0_phy>, <0>; }; @@ -364,6 +404,176 @@ usb_dwc: usb@8a00000 { }; }; + pcie0: pcie@20000000 { + compatible = "qcom,pcie-ipq5332"; + reg = <0x20000000 0xf1d>, + <0x20000F20 0xa8>, + <0x20001000 0x1000>, + <0x00080000 0x3000>, + <0x20100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>, /* I/O */ + <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>; /* MEM */ + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X1_0_RCHG_CLK>, + <&gcc GCC_PCIE3X1_0_AHB_CLK>, + <&gcc GCC_PCIE3X1_0_AUX_CLK>; + + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>, + <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>; + + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>, + <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + msi-map = <0x0 &v2m0 0x0 0xffd>; + status = "disabled"; + }; + + pcie1: pcie@18000000 { + compatible = "qcom,pcie-ipq5332"; + reg = <0x18000000 0xf1d>, + <0x18000F20 0xa8>, + <0x18001000 0x1000>, + <0x00088000 0x3000>, + <0x18100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0 0x18200000 0x18200000 0 0x00100000>, /* I/O */ + <0x02000000 0 0x18300000 0x18300000 0 0x07d00000>; /* MEM */ + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X2_RCHG_CLK>, + <&gcc GCC_PCIE3X2_AHB_CLK>, + <&gcc GCC_PCIE3X2_AUX_CLK>; + + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE3X2_PIPE_ARES>, + <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X2_AUX_CLK_ARES>, + <&gcc GCC_PCIE3X2_AHB_CLK_ARES>; + + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, + <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + msi-map = <0x0 &v2m0 0x0 0xffd>; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */