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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260e8af8sm257710266b.191.2024.12.06.08.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2024 08:31:02 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 06 Dec 2024 16:31:02 +0000 Subject: [PATCH v4 2/7] dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241206-gs101-phy-lanes-orientation-phy-v4-2-f5961268b149@linaro.org> References: <20241206-gs101-phy-lanes-orientation-phy-v4-0-f5961268b149@linaro.org> In-Reply-To: <20241206-gs101-phy-lanes-orientation-phy-v4-0-f5961268b149@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 orientation-switch is the standard declaration to inform the Type-C mux layer that a remote-endpoint is capable of processing orientation change messages. The USB PHY on gs101 needs to be configured based on the orientation of the connector. For that the DTS needs a link between the phy's port and a TCPCi, and we'll need to inform the phy driver that it should handle the orientation (register a handler). Update the schema to enforce that by requiring the orientation-switch and port properties on gs101 (only). We disallow orientation-switch on all other supported platforms, since other versions of this phy (or its system integration) don't currently support or even need it. Even though this new required gs101 property is an ABI break, the intention for the driver is to behave as before if it's missing (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected. Reviewed-by: Peter Griffin Signed-off-by: André Draszik --- v3: * update as per Rob's suggestion (I hope :-) v2: * squash original patches #2 and #3 * actually disallow orientation-switch on !gs101 (not just optional) (Conor) * update commit message to clarify that the intention for the driver is to work with old and new DTS (Conor) * collect tags foo --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 1f8b35917b11..27295acbba76 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -114,6 +114,8 @@ allOf: contains: const: google,gs101-usb31drd-phy then: + $ref: /schemas/usb/usb-switch.yaml# + properties: clocks: items: @@ -139,6 +141,8 @@ allOf: required: - reg-names + - orientation-switch + - port - pll-supply - dvdd-usb20-supply - vddh-usb20-supply @@ -198,7 +202,7 @@ allOf: reg-names: maxItems: 1 -additionalProperties: false +unevaluatedProperties: false examples: - | From patchwork Fri Dec 6 16:31:04 2024 Content-Type: text/plain; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260e8af8sm257710266b.191.2024.12.06.08.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2024 08:31:03 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 06 Dec 2024 16:31:04 +0000 Subject: [PATCH v4 4/7] phy: exynos5-usbdrd: fix EDS distribution tuning (gs101) Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241206-gs101-phy-lanes-orientation-phy-v4-4-f5961268b149@linaro.org> References: <20241206-gs101-phy-lanes-orientation-phy-v4-0-f5961268b149@linaro.org> In-Reply-To: <20241206-gs101-phy-lanes-orientation-phy-v4-0-f5961268b149@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 This code's intention is to configure lane0 and lane2 tunings, but for lane2 there is a typo and it ends up tuning something else. Fix the typo, as it doesn't appear to make sense to apply different tunings for lane0 vs lane2. The same typo appears to exist in the bootloader, hence we restore the original value in the typo'd registers as well. This can be removed once / if the bootloader is updated. Note that this is incorrect in the downstream driver as well - the values had been copied from there. Reviewed-by: Peter Griffin Tested-by: Peter Griffin Signed-off-by: André Draszik --- v2: * collect tags --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index ceae4b47cece..2a724d362c2d 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1510,8 +1510,11 @@ static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_preinit[] = { PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00), PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36), PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06), - PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x00), - PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x36), + PHY_TUNING_ENTRY_PMA(0x19e0, -1, 0x00), + PHY_TUNING_ENTRY_PMA(0x19e4, -1, 0x36), + /* fix bootloader bug */ + PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x02), + PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x0b), /* improve LVCC */ PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30), PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30), From patchwork Fri Dec 6 16:31:06 2024 Content-Type: text/plain; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260e8af8sm257710266b.191.2024.12.06.08.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2024 08:31:04 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 06 Dec 2024 16:31:06 +0000 Subject: [PATCH v4 6/7] phy: exynos5-usbdrd: subscribe to orientation notifier if required Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241206-gs101-phy-lanes-orientation-phy-v4-6-f5961268b149@linaro.org> References: <20241206-gs101-phy-lanes-orientation-phy-v4-0-f5961268b149@linaro.org> In-Reply-To: <20241206-gs101-phy-lanes-orientation-phy-v4-0-f5961268b149@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 gs101's SS phy needs to be configured differently based on the connector orientation, as the SS link can only be established if the mux is configured correctly. The code to handle programming of the mux is in place already, this commit now adds the missing pieces to subscribe to the Type-C orientation switch event. Note that for this all to work we rely on the USB controller re-initialising us. It should invoke our .exit() upon cable unplug, and during cable plug we'll receive the orientation event after which we expect our .init() to be called. Above reinitialisation happens if the DWC3 controller can enter runtime suspend automatically. For the DWC3 driver, this is an opt-in: echo auto > /sys/devices/.../11110000.usb/power/control Once done, things work as long as the UDC is not bound as otherwise it stays busy because it doesn't cancel / stop outstanding TRBs. For now we have to manually unbind the UDC in that case: echo "" > sys/kernel/config/usb_gadget/.../UDC Note that if the orientation-switch property is missing from the DT, the code will behave as before this commit (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected either way. Signed-off-by: André Draszik Reviewed-by: Peter Griffin Tested-by: Peter Griffin --- v3: * drop init to -1 of phy_drd->orientation (Vinod) * avoid #ifdef and switch to normal conditional IS_ENABLED() for CONFIG_TYPEC v2: * move #include typec_mux.h from parent patch into this one (Peter) --- drivers/phy/samsung/Kconfig | 1 + drivers/phy/samsung/phy-exynos5-usbdrd.c | 56 ++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig index f10afa3d7ff5..fc7bd1088576 100644 --- a/drivers/phy/samsung/Kconfig +++ b/drivers/phy/samsung/Kconfig @@ -80,6 +80,7 @@ config PHY_EXYNOS5_USBDRD tristate "Exynos5 SoC series USB DRD PHY driver" depends on (ARCH_EXYNOS && OF) || COMPILE_TEST depends on HAS_IOMEM + depends on TYPEC || (TYPEC=n && COMPILE_TEST) depends on USB_DWC3_EXYNOS select GENERIC_PHY select MFD_SYSCON diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 61e0de4b3d4b..8fc15847cfd8 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -24,6 +24,7 @@ #include #include #include +#include /* Exynos USB PHY registers */ #define EXYNOS5_FSEL_9MHZ6 0x0 @@ -394,6 +395,7 @@ struct exynos5_usbdrd_phy_drvdata { * @extrefclk: frequency select settings when using 'separate * reference clocks' for SS and HS operations * @regulators: regulators for phy + * @sw: TypeC orientation switch handle * @orientation: TypeC connector orientation - normal or flipped */ struct exynos5_usbdrd_phy { @@ -415,6 +417,7 @@ struct exynos5_usbdrd_phy { u32 extrefclk; struct regulator_bulk_data *regulators; + struct typec_switch_dev *sw; enum typec_orientation orientation; }; @@ -1397,6 +1400,55 @@ static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd) return 0; } +static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct exynos5_usbdrd_phy *phy_drd = typec_switch_get_drvdata(sw); + + scoped_guard(mutex, &phy_drd->phy_mutex) + phy_drd->orientation = orientation; + + return 0; +} + +static void exynos5_usbdrd_orien_switch_unregister(void *data) +{ + struct exynos5_usbdrd_phy *phy_drd = data; + + typec_switch_unregister(phy_drd->sw); +} + +static int exynos5_usbdrd_setup_notifiers(struct exynos5_usbdrd_phy *phy_drd) +{ + int ret; + + if (!IS_ENABLED(CONFIG_TYPEC)) + return 0; + + if (device_property_present(phy_drd->dev, "orientation-switch")) { + struct typec_switch_desc sw_desc = { }; + + sw_desc.drvdata = phy_drd; + sw_desc.fwnode = dev_fwnode(phy_drd->dev); + sw_desc.set = exynos5_usbdrd_orien_sw_set; + + phy_drd->sw = typec_switch_register(phy_drd->dev, &sw_desc); + if (IS_ERR(phy_drd->sw)) + return dev_err_probe(phy_drd->dev, + PTR_ERR(phy_drd->sw), + "Failed to register TypeC orientation switch\n"); + + ret = devm_add_action_or_reset(phy_drd->dev, + exynos5_usbdrd_orien_switch_unregister, + phy_drd); + if (ret) + return dev_err_probe(phy_drd->dev, ret, + "Failed to register TypeC orientation devm action\n"); + } + + return 0; +} + static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { { .id = EXYNOS5_DRDPHY_UTMI, @@ -1786,6 +1838,10 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to get regulators\n"); + ret = exynos5_usbdrd_setup_notifiers(phy_drd); + if (ret) + return ret; + dev_vdbg(dev, "Creating usbdrd_phy phy\n"); for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {