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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/72] hw/net/lan9118: Extract lan9118_phy Date: Wed, 11 Dec 2024 16:18:53 +0000 Message-Id: <20241211162004.2795499-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow A very similar implementation of the same device exists in imx_fec. Prepare for a common implementation by extracting a device model into its own files. Some migration state has been moved into the new device model which breaks migration compatibility for the following machines: * smdkc210 * realview-* * vexpress-* * kzm * mps2-* While breaking migration ABI, fix the size of the MII registers to be 16 bit, as defined by IEEE 802.3u. Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Reviewed-by: Peter Maydell Message-id: 20241102125724.532843-2-shentey@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/lan9118_phy.h | 37 ++++++++ hw/net/lan9118.c | 137 +++++----------------------- hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++ hw/net/Kconfig | 4 + hw/net/meson.build | 1 + 5 files changed, 233 insertions(+), 115 deletions(-) create mode 100644 include/hw/net/lan9118_phy.h create mode 100644 hw/net/lan9118_phy.c diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h new file mode 100644 index 00000000000..af12fc33d5f --- /dev/null +++ b/include/hw/net/lan9118_phy.h @@ -0,0 +1,37 @@ +/* + * SMSC LAN9118 PHY emulation + * + * Copyright (c) 2009 CodeSourcery, LLC. + * Written by Paul Brook + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_NET_LAN9118_PHY_H +#define HW_NET_LAN9118_PHY_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +#define TYPE_LAN9118_PHY "lan9118-phy" +OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY) + +typedef struct Lan9118PhyState { + SysBusDevice parent_obj; + + uint16_t status; + uint16_t control; + uint16_t advertise; + uint16_t ints; + uint16_t int_mask; + qemu_irq irq; + bool link_down; +} Lan9118PhyState; + +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down); +void lan9118_phy_reset(Lan9118PhyState *s); +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg); +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val); + +#endif diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index db28a0ef306..99e87b7178c 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -16,6 +16,7 @@ #include "net/net.h" #include "net/eth.h" #include "hw/irq.h" +#include "hw/net/lan9118_phy.h" #include "hw/net/lan9118.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" @@ -139,14 +140,6 @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) #define MAC_CR_RXEN 0x00000004 #define MAC_CR_RESERVED 0x7f404213 -#define PHY_INT_ENERGYON 0x80 -#define PHY_INT_AUTONEG_COMPLETE 0x40 -#define PHY_INT_FAULT 0x20 -#define PHY_INT_DOWN 0x10 -#define PHY_INT_AUTONEG_LP 0x08 -#define PHY_INT_PARFAULT 0x04 -#define PHY_INT_AUTONEG_PAGE 0x02 - #define GPT_TIMER_EN 0x20000000 /* @@ -228,11 +221,8 @@ struct lan9118_state { uint32_t mac_mii_data; uint32_t mac_flow; - uint32_t phy_status; - uint32_t phy_control; - uint32_t phy_advertise; - uint32_t phy_int; - uint32_t phy_int_mask; + Lan9118PhyState mii; + IRQState mii_irq; int32_t eeprom_writable; uint8_t eeprom[128]; @@ -274,8 +264,8 @@ struct lan9118_state { static const VMStateDescription vmstate_lan9118 = { .name = "lan9118", - .version_id = 2, - .minimum_version_id = 1, + .version_id = 3, + .minimum_version_id = 3, .fields = (const VMStateField[]) { VMSTATE_PTIMER(timer, lan9118_state), VMSTATE_UINT32(irq_cfg, lan9118_state), @@ -301,11 +291,6 @@ static const VMStateDescription vmstate_lan9118 = { VMSTATE_UINT32(mac_mii_acc, lan9118_state), VMSTATE_UINT32(mac_mii_data, lan9118_state), VMSTATE_UINT32(mac_flow, lan9118_state), - VMSTATE_UINT32(phy_status, lan9118_state), - VMSTATE_UINT32(phy_control, lan9118_state), - VMSTATE_UINT32(phy_advertise, lan9118_state), - VMSTATE_UINT32(phy_int, lan9118_state), - VMSTATE_UINT32(phy_int_mask, lan9118_state), VMSTATE_INT32(eeprom_writable, lan9118_state), VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), VMSTATE_INT32(tx_fifo_size, lan9118_state), @@ -385,9 +370,11 @@ static void lan9118_reload_eeprom(lan9118_state *s) lan9118_mac_changed(s); } -static void phy_update_irq(lan9118_state *s) +static void lan9118_update_irq(void *opaque, int n, int level) { - if (s->phy_int & s->phy_int_mask) { + lan9118_state *s = opaque; + + if (level) { s->int_sts |= PHY_INT; } else { s->int_sts &= ~PHY_INT; @@ -395,33 +382,10 @@ static void phy_update_irq(lan9118_state *s) lan9118_update(s); } -static void phy_update_link(lan9118_state *s) -{ - /* Autonegotiation status mirrors link status. */ - if (qemu_get_queue(s->nic)->link_down) { - s->phy_status &= ~0x0024; - s->phy_int |= PHY_INT_DOWN; - } else { - s->phy_status |= 0x0024; - s->phy_int |= PHY_INT_ENERGYON; - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; - } - phy_update_irq(s); -} - static void lan9118_set_link(NetClientState *nc) { - phy_update_link(qemu_get_nic_opaque(nc)); -} - -static void phy_reset(lan9118_state *s) -{ - s->phy_status = 0x7809; - s->phy_control = 0x3000; - s->phy_advertise = 0x01e1; - s->phy_int_mask = 0; - s->phy_int = 0; - phy_update_link(s); + lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, + nc->link_down); } static void lan9118_reset(DeviceState *d) @@ -478,8 +442,6 @@ static void lan9118_reset(DeviceState *d) s->read_word_n = 0; s->write_word_n = 0; - phy_reset(s); - s->eeprom_writable = 0; lan9118_reload_eeprom(s); } @@ -678,7 +640,7 @@ static void do_tx_packet(lan9118_state *s) uint32_t status; /* FIXME: Honor TX disable, and allow queueing of packets. */ - if (s->phy_control & 0x4000) { + if (s->mii.control & 0x4000) { /* This assumes the receive routine doesn't touch the VLANClient. */ qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); } else { @@ -834,68 +796,6 @@ static void tx_fifo_push(lan9118_state *s, uint32_t val) } } -static uint32_t do_phy_read(lan9118_state *s, int reg) -{ - uint32_t val; - - switch (reg) { - case 0: /* Basic Control */ - return s->phy_control; - case 1: /* Basic Status */ - return s->phy_status; - case 2: /* ID1 */ - return 0x0007; - case 3: /* ID2 */ - return 0xc0d1; - case 4: /* Auto-neg advertisement */ - return s->phy_advertise; - case 5: /* Auto-neg Link Partner Ability */ - return 0x0f71; - case 6: /* Auto-neg Expansion */ - return 1; - /* TODO 17, 18, 27, 29, 30, 31 */ - case 29: /* Interrupt source. */ - val = s->phy_int; - s->phy_int = 0; - phy_update_irq(s); - return val; - case 30: /* Interrupt mask */ - return s->phy_int_mask; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "do_phy_read: PHY read reg %d\n", reg); - return 0; - } -} - -static void do_phy_write(lan9118_state *s, int reg, uint32_t val) -{ - switch (reg) { - case 0: /* Basic Control */ - if (val & 0x8000) { - phy_reset(s); - break; - } - s->phy_control = val & 0x7980; - /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->phy_status |= 0x0020; - } - break; - case 4: /* Auto-neg advertisement */ - s->phy_advertise = (val & 0x2d7f) | 0x80; - break; - /* TODO 17, 18, 27, 31 */ - case 30: /* Interrupt mask */ - s->phy_int_mask = val & 0xff; - phy_update_irq(s); - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val); - } -} - static void do_mac_write(lan9118_state *s, int reg, uint32_t val) { switch (reg) { @@ -929,9 +829,9 @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val) if (val & 2) { DPRINTF("PHY write %d = 0x%04x\n", (val >> 6) & 0x1f, s->mac_mii_data); - do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); + lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); } else { - s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); + s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); DPRINTF("PHY read %d = 0x%04x\n", (val >> 6) & 0x1f, s->mac_mii_data); } @@ -1126,7 +1026,7 @@ static void lan9118_writel(void *opaque, hwaddr offset, break; case CSR_PMT_CTRL: if (val & 0x400) { - phy_reset(s); + lan9118_phy_reset(&s->mii); } s->pmt_ctrl &= ~0x34e; s->pmt_ctrl |= (val & 0x34e); @@ -1373,6 +1273,13 @@ static void lan9118_realize(DeviceState *dev, Error **errp) const MemoryRegionOps *mem_ops = s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; + qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0); + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); + memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, "lan9118-mmio", 0x100); sysbus_init_mmio(sbd, &s->mmio); diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c new file mode 100644 index 00000000000..b22c3c28556 --- /dev/null +++ b/hw/net/lan9118_phy.c @@ -0,0 +1,169 @@ +/* + * SMSC LAN9118 PHY emulation + * + * Copyright (c) 2009 CodeSourcery, LLC. + * Written by Paul Brook + * + * This code is licensed under the GNU GPL v2 + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "hw/net/lan9118_phy.h" +#include "hw/irq.h" +#include "hw/resettable.h" +#include "migration/vmstate.h" +#include "qemu/log.h" + +#define PHY_INT_ENERGYON (1 << 7) +#define PHY_INT_AUTONEG_COMPLETE (1 << 6) +#define PHY_INT_FAULT (1 << 5) +#define PHY_INT_DOWN (1 << 4) +#define PHY_INT_AUTONEG_LP (1 << 3) +#define PHY_INT_PARFAULT (1 << 2) +#define PHY_INT_AUTONEG_PAGE (1 << 1) + +static void lan9118_phy_update_irq(Lan9118PhyState *s) +{ + qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); +} + +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) +{ + uint16_t val; + + switch (reg) { + case 0: /* Basic Control */ + return s->control; + case 1: /* Basic Status */ + return s->status; + case 2: /* ID1 */ + return 0x0007; + case 3: /* ID2 */ + return 0xc0d1; + case 4: /* Auto-neg advertisement */ + return s->advertise; + case 5: /* Auto-neg Link Partner Ability */ + return 0x0f71; + case 6: /* Auto-neg Expansion */ + return 1; + /* TODO 17, 18, 27, 29, 30, 31 */ + case 29: /* Interrupt source. */ + val = s->ints; + s->ints = 0; + lan9118_phy_update_irq(s); + return val; + case 30: /* Interrupt mask */ + return s->int_mask; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "lan9118_phy_read: PHY read reg %d\n", reg); + return 0; + } +} + +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) +{ + switch (reg) { + case 0: /* Basic Control */ + if (val & 0x8000) { + lan9118_phy_reset(s); + break; + } + s->control = val & 0x7980; + /* Complete autonegotiation immediately. */ + if (val & 0x1000) { + s->status |= 0x0020; + } + break; + case 4: /* Auto-neg advertisement */ + s->advertise = (val & 0x2d7f) | 0x80; + break; + /* TODO 17, 18, 27, 31 */ + case 30: /* Interrupt mask */ + s->int_mask = val & 0xff; + lan9118_phy_update_irq(s); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); + } +} + +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) +{ + s->link_down = link_down; + + /* Autonegotiation status mirrors link status. */ + if (link_down) { + s->status &= ~0x0024; + s->ints |= PHY_INT_DOWN; + } else { + s->status |= 0x0024; + s->ints |= PHY_INT_ENERGYON; + s->ints |= PHY_INT_AUTONEG_COMPLETE; + } + lan9118_phy_update_irq(s); +} + +void lan9118_phy_reset(Lan9118PhyState *s) +{ + s->control = 0x3000; + s->status = 0x7809; + s->advertise = 0x01e1; + s->int_mask = 0; + s->ints = 0; + lan9118_phy_update_link(s, s->link_down); +} + +static void lan9118_phy_reset_hold(Object *obj, ResetType type) +{ + Lan9118PhyState *s = LAN9118_PHY(obj); + + lan9118_phy_reset(s); +} + +static void lan9118_phy_init(Object *obj) +{ + Lan9118PhyState *s = LAN9118_PHY(obj); + + qdev_init_gpio_out(DEVICE(s), &s->irq, 1); +} + +static const VMStateDescription vmstate_lan9118_phy = { + .name = "lan9118-phy", + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_UINT16(control, Lan9118PhyState), + VMSTATE_UINT16(status, Lan9118PhyState), + VMSTATE_UINT16(advertise, Lan9118PhyState), + VMSTATE_UINT16(ints, Lan9118PhyState), + VMSTATE_UINT16(int_mask, Lan9118PhyState), + VMSTATE_BOOL(link_down, Lan9118PhyState), + VMSTATE_END_OF_LIST() + } +}; + +static void lan9118_phy_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + rc->phases.hold = lan9118_phy_reset_hold; + dc->vmsd = &vmstate_lan9118_phy; +} + +static const TypeInfo types[] = { + { + .name = TYPE_LAN9118_PHY, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Lan9118PhyState), + .instance_init = lan9118_phy_init, + .class_init = lan9118_phy_class_init, + } +}; + +DEFINE_TYPES(types) diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 7fcc0d7faa2..6b2ff2f937a 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -62,8 +62,12 @@ config VMXNET3_PCI config SMC91C111 bool +config LAN9118_PHY + bool + config LAN9118 bool + select LAN9118_PHY select PTIMER config NE2000_ISA diff --git a/hw/net/meson.build b/hw/net/meson.build index 00a9e9dd515..3bb5d749a83 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -19,6 +19,7 @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) +system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c')) system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) From patchwork Wed Dec 11 16:18:54 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations Date: Wed, 11 Dec 2024 16:18:54 +0000 Message-Id: <20241211162004.2795499-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow imx_fec models the same PHY as lan9118_phy. The code is almost the same with imx_fec having more logging and tracing. Merge these improvements into lan9118_phy and reuse in imx_fec to fix the code duplication. Some migration state how resides in the new device model which breaks migration compatibility for the following machines: * imx25-pdk * sabrelite * mcimx7d-sabre * mcimx6ul-evk Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Reviewed-by: Peter Maydell Message-id: 20241102125724.532843-3-shentey@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/imx_fec.h | 9 ++- hw/net/imx_fec.c | 146 ++++----------------------------------- hw/net/lan9118_phy.c | 82 ++++++++++++++++------ hw/net/Kconfig | 1 + hw/net/trace-events | 10 +-- 5 files changed, 85 insertions(+), 163 deletions(-) diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 2d13290c787..83b21637eeb 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -31,6 +31,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC) #define TYPE_IMX_ENET "imx.enet" #include "hw/sysbus.h" +#include "hw/net/lan9118_phy.h" +#include "hw/irq.h" #include "net/net.h" #define ENET_EIR 1 @@ -264,11 +266,8 @@ struct IMXFECState { uint32_t tx_descriptor[ENET_TX_RING_NUM]; uint32_t tx_ring_num; - uint32_t phy_status; - uint32_t phy_control; - uint32_t phy_advertise; - uint32_t phy_int; - uint32_t phy_int_mask; + Lan9118PhyState mii; + IRQState mii_irq; uint32_t phy_num; bool phy_connected; struct IMXFECState *phy_consumer; diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 6294d292023..4ee6f742063 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -203,17 +203,12 @@ static const VMStateDescription vmstate_imx_eth_txdescs = { static const VMStateDescription vmstate_imx_eth = { .name = TYPE_IMX_FEC, - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), VMSTATE_UINT32(rx_descriptor, IMXFECState), VMSTATE_UINT32(tx_descriptor[0], IMXFECState), - VMSTATE_UINT32(phy_status, IMXFECState), - VMSTATE_UINT32(phy_control, IMXFECState), - VMSTATE_UINT32(phy_advertise, IMXFECState), - VMSTATE_UINT32(phy_int, IMXFECState), - VMSTATE_UINT32(phy_int_mask, IMXFECState), VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription * const []) { @@ -222,14 +217,6 @@ static const VMStateDescription vmstate_imx_eth = { }, }; -#define PHY_INT_ENERGYON (1 << 7) -#define PHY_INT_AUTONEG_COMPLETE (1 << 6) -#define PHY_INT_FAULT (1 << 5) -#define PHY_INT_DOWN (1 << 4) -#define PHY_INT_AUTONEG_LP (1 << 3) -#define PHY_INT_PARFAULT (1 << 2) -#define PHY_INT_AUTONEG_PAGE (1 << 1) - static void imx_eth_update(IMXFECState *s); /* @@ -238,47 +225,19 @@ static void imx_eth_update(IMXFECState *s); * For now we don't handle any GPIO/interrupt line, so the OS will * have to poll for the PHY status. */ -static void imx_phy_update_irq(IMXFECState *s) +static void imx_phy_update_irq(void *opaque, int n, int level) { - imx_eth_update(s); -} - -static void imx_phy_update_link(IMXFECState *s) -{ - /* Autonegotiation status mirrors link status. */ - if (qemu_get_queue(s->nic)->link_down) { - trace_imx_phy_update_link("down"); - s->phy_status &= ~0x0024; - s->phy_int |= PHY_INT_DOWN; - } else { - trace_imx_phy_update_link("up"); - s->phy_status |= 0x0024; - s->phy_int |= PHY_INT_ENERGYON; - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; - } - imx_phy_update_irq(s); + imx_eth_update(opaque); } static void imx_eth_set_link(NetClientState *nc) { - imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); -} - -static void imx_phy_reset(IMXFECState *s) -{ - trace_imx_phy_reset(); - - s->phy_status = 0x7809; - s->phy_control = 0x3000; - s->phy_advertise = 0x01e1; - s->phy_int_mask = 0; - s->phy_int = 0; - imx_phy_update_link(s); + lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, + nc->link_down); } static uint32_t imx_phy_read(IMXFECState *s, int reg) { - uint32_t val; uint32_t phy = reg / 32; if (!s->phy_connected) { @@ -296,54 +255,7 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) reg %= 32; - switch (reg) { - case 0: /* Basic Control */ - val = s->phy_control; - break; - case 1: /* Basic Status */ - val = s->phy_status; - break; - case 2: /* ID1 */ - val = 0x0007; - break; - case 3: /* ID2 */ - val = 0xc0d1; - break; - case 4: /* Auto-neg advertisement */ - val = s->phy_advertise; - break; - case 5: /* Auto-neg Link Partner Ability */ - val = 0x0f71; - break; - case 6: /* Auto-neg Expansion */ - val = 1; - break; - case 29: /* Interrupt source. */ - val = s->phy_int; - s->phy_int = 0; - imx_phy_update_irq(s); - break; - case 30: /* Interrupt mask */ - val = s->phy_int_mask; - break; - case 17: - case 18: - case 27: - case 31: - qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", - TYPE_IMX_FEC, __func__, reg); - val = 0; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", - TYPE_IMX_FEC, __func__, reg); - val = 0; - break; - } - - trace_imx_phy_read(val, phy, reg); - - return val; + return lan9118_phy_read(&s->mii, reg); } static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) @@ -365,39 +277,7 @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) reg %= 32; - trace_imx_phy_write(val, phy, reg); - - switch (reg) { - case 0: /* Basic Control */ - if (val & 0x8000) { - imx_phy_reset(s); - } else { - s->phy_control = val & 0x7980; - /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->phy_status |= 0x0020; - } - } - break; - case 4: /* Auto-neg advertisement */ - s->phy_advertise = (val & 0x2d7f) | 0x80; - break; - case 30: /* Interrupt mask */ - s->phy_int_mask = val & 0xff; - imx_phy_update_irq(s); - break; - case 17: - case 18: - case 27: - case 31: - qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", - TYPE_IMX_FEC, __func__, reg); - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", - TYPE_IMX_FEC, __func__, reg); - break; - } + lan9118_phy_write(&s->mii, reg, val); } static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) @@ -682,9 +562,6 @@ static void imx_eth_reset(DeviceState *d) s->rx_descriptor = 0; memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); - - /* We also reset the PHY */ - imx_phy_reset(s); } static uint32_t imx_default_read(IMXFECState *s, uint32_t index) @@ -1329,6 +1206,13 @@ static void imx_eth_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->irq[0]); sysbus_init_irq(sbd, &s->irq[1]); + qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0); + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); + qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index b22c3c28556..d2dcd732ac1 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -4,6 +4,8 @@ * Copyright (c) 2009 CodeSourcery, LLC. * Written by Paul Brook * + * Copyright (c) 2013 Jean-Christophe Dubois. + * * This code is licensed under the GNU GPL v2 * * Contributions after 2012-01-13 are licensed under the terms of the @@ -16,6 +18,7 @@ #include "hw/resettable.h" #include "migration/vmstate.h" #include "qemu/log.h" +#include "trace.h" #define PHY_INT_ENERGYON (1 << 7) #define PHY_INT_AUTONEG_COMPLETE (1 << 6) @@ -36,59 +39,88 @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) switch (reg) { case 0: /* Basic Control */ - return s->control; + val = s->control; + break; case 1: /* Basic Status */ - return s->status; + val = s->status; + break; case 2: /* ID1 */ - return 0x0007; + val = 0x0007; + break; case 3: /* ID2 */ - return 0xc0d1; + val = 0xc0d1; + break; case 4: /* Auto-neg advertisement */ - return s->advertise; + val = s->advertise; + break; case 5: /* Auto-neg Link Partner Ability */ - return 0x0f71; + val = 0x0f71; + break; case 6: /* Auto-neg Expansion */ - return 1; - /* TODO 17, 18, 27, 29, 30, 31 */ + val = 1; + break; case 29: /* Interrupt source. */ val = s->ints; s->ints = 0; lan9118_phy_update_irq(s); - return val; + break; case 30: /* Interrupt mask */ - return s->int_mask; + val = s->int_mask; + break; + case 17: + case 18: + case 27: + case 31: + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", + __func__, reg); + val = 0; + break; default: - qemu_log_mask(LOG_GUEST_ERROR, - "lan9118_phy_read: PHY read reg %d\n", reg); - return 0; + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", + __func__, reg); + val = 0; + break; } + + trace_lan9118_phy_read(val, reg); + + return val; } void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) { + trace_lan9118_phy_write(val, reg); + switch (reg) { case 0: /* Basic Control */ if (val & 0x8000) { lan9118_phy_reset(s); - break; - } - s->control = val & 0x7980; - /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->status |= 0x0020; + } else { + s->control = val & 0x7980; + /* Complete autonegotiation immediately. */ + if (val & 0x1000) { + s->status |= 0x0020; + } } break; case 4: /* Auto-neg advertisement */ s->advertise = (val & 0x2d7f) | 0x80; break; - /* TODO 17, 18, 27, 31 */ case 30: /* Interrupt mask */ s->int_mask = val & 0xff; lan9118_phy_update_irq(s); break; + case 17: + case 18: + case 27: + case 31: + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", + __func__, reg); + break; default: - qemu_log_mask(LOG_GUEST_ERROR, - "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", + __func__, reg); + break; } } @@ -98,9 +130,11 @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) /* Autonegotiation status mirrors link status. */ if (link_down) { + trace_lan9118_phy_update_link("down"); s->status &= ~0x0024; s->ints |= PHY_INT_DOWN; } else { + trace_lan9118_phy_update_link("up"); s->status |= 0x0024; s->ints |= PHY_INT_ENERGYON; s->ints |= PHY_INT_AUTONEG_COMPLETE; @@ -110,6 +144,8 @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) void lan9118_phy_reset(Lan9118PhyState *s) { + trace_lan9118_phy_reset(); + s->control = 0x3000; s->status = 0x7809; s->advertise = 0x01e1; @@ -137,8 +173,8 @@ static const VMStateDescription vmstate_lan9118_phy = { .version_id = 1, .minimum_version_id = 1, .fields = (const VMStateField[]) { - VMSTATE_UINT16(control, Lan9118PhyState), VMSTATE_UINT16(status, Lan9118PhyState), + VMSTATE_UINT16(control, Lan9118PhyState), VMSTATE_UINT16(advertise, Lan9118PhyState), VMSTATE_UINT16(ints, Lan9118PhyState), VMSTATE_UINT16(int_mask, Lan9118PhyState), diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 6b2ff2f937a..7f80218d10f 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -93,6 +93,7 @@ config ALLWINNER_SUN8I_EMAC config IMX_FEC bool + select LAN9118_PHY config CADENCE bool diff --git a/hw/net/trace-events b/hw/net/trace-events index d0f1d8c0fbe..6100ec324a7 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -10,6 +10,12 @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 +# lan9118_phy.c +lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 +lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 +lan9118_phy_update_link(const char *s) "%s" +lan9118_phy_reset(void) "" + # lance.c lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" @@ -428,12 +434,8 @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" # imx_fec.c -imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" -imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" -imx_phy_update_link(const char *s) "%s" -imx_phy_reset(void) "" imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" From patchwork Wed Dec 11 16:18:55 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register Date: Wed, 11 Dec 2024 16:18:55 +0000 Message-Id: <20241211162004.2795499-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and fixes the MSB of selector field to be zero, as specified in the datasheet. Fixes: 2a424990170b "LAN9118 emulation" Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Reviewed-by: Peter Maydell Message-id: 20241102125724.532843-4-shentey@gmail.com Signed-off-by: Peter Maydell --- hw/net/lan9118_phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index d2dcd732ac1..d8fc9ddd3ac 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -54,7 +54,7 @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) val = s->advertise; break; case 5: /* Auto-neg Link Partner Ability */ - val = 0x0f71; + val = 0x0fe1; break; case 6: /* Auto-neg Expansion */ val = 1; From patchwork Wed Dec 11 16:18:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849172 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414648wry; Wed, 11 Dec 2024 08:23:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXVy4wzJCtXZsyhUv/A1rDmvYY/wvqC/4ZV13NZPBTnuRFnU0fZ3Dz7xjtJAMe/PvIFCWNvDQ==@linaro.org X-Google-Smtp-Source: AGHT+IFr1Yra+M0UfZ21CIh8FvzgLQCJWHbxbAM85FxrUFfMakpLP88lvQJTByFDKlDYMaf+M1c1 X-Received: by 2002:a05:6214:2628:b0:6d8:821d:7370 with SMTP id 6a1803df08f44-6dae2b7b322mr3949826d6.49.1733934179880; Wed, 11 Dec 2024 08:22:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934179; cv=none; d=google.com; s=arc-20240605; b=ffWt/UmcVDZsCCedVTgsVS8gex/9POYNMquIgLJXk/j9PR/cn/AHzz52A0LoXy4zst zfZK6vu/gmpxgu1JWPUGYzB4/JV364FEzrvNK7eazIEdNsVLyj0dAsX8htOrp3fLp7wN qYmUxos12boKU9AM9DnpPlJD8zZ9zmGVYb4Fojpv9ns9qGtwCRIIrRUhUIyu+GFmkEmz 8deTjWvWItvYJ7U9l7EDUpu7BTYhjoRh0coChnXfTWbMovmlCb/m+wFYB05CdHMTrR0S 2K/PfrHoJ8VM6C0GSidKGPgTZUbbhI+VMuGBnVFxxGFXRyggegprL5nkWkkEDuc2fn8q bOMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0WGriA4LS3QsH5lw3Ak1RT7ziiVmWhZi2ZbsQKrrgFY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=gbU5ESBfIAMwHFIeVJmw/GE4EDx2dc8cQl8sQQbrtssgzHVqpa3QWWL4dCFgSlr5sr /uEo18bvP0ogysyBtrQbjY1CdnuxDjcv1KT0/7ml/dmlxjdCOzH1Lu2vLBd0oZ3Cwxou Cwk6mbciYMDqYOvqxUrBXCH5mxwZh83turBFoCYOtqi7DBFL8UOZIphWfcmLcmKNiAq9 KlqOomuOQsK4JNwNjHmO0kRIQS2B98pmDZVpxmhTD6k3ywnYyjXqZnxp87w7Iq+fdl42 7t2b47kdoj2Jvay75G2TP5V6hN/6LvXIbr6+dixVaggXN7gboAts97CDfZrrqbnegbGd c7mA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xd2sH6bJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/72] hw/net/lan9118_phy: Reuse MII constants Date: Wed, 11 Dec 2024 16:18:56 +0000 Message-Id: <20241211162004.2795499-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow Prefer named constants over magic values for better readability. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Message-id: 20241102125724.532843-5-shentey@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/mii.h | 6 +++++ hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++---------------- 2 files changed, 46 insertions(+), 23 deletions(-) diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index f7feddac9bd..55bf7c92a1c 100644 --- a/include/hw/net/mii.h +++ b/include/hw/net/mii.h @@ -71,6 +71,7 @@ #define MII_BMSR_JABBER (1 << 1) /* Jabber detected */ #define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */ +#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */ #define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */ #define MII_ANAR_PAUSE (1 << 10) /* Try for pause */ #define MII_ANAR_TXFD (1 << 8) @@ -78,6 +79,7 @@ #define MII_ANAR_10FD (1 << 6) #define MII_ANAR_10 (1 << 5) #define MII_ANAR_CSMACD (1 << 0) +#define MII_ANAR_SELECT (0x001f) /* Selector bits */ #define MII_ANLPAR_ACK (1 << 14) #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ @@ -112,6 +114,10 @@ #define RTL8201CP_PHYID1 0x0000 #define RTL8201CP_PHYID2 0x8201 +/* SMSC LAN9118 */ +#define SMSCLAN9118_PHYID1 0x0007 +#define SMSCLAN9118_PHYID2 0xc0d1 + /* RealTek 8211E */ #define RTL8211E_PHYID1 0x001c #define RTL8211E_PHYID2 0xc915 diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index d8fc9ddd3ac..874dae4155a 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -14,6 +14,7 @@ #include "qemu/osdep.h" #include "hw/net/lan9118_phy.h" +#include "hw/net/mii.h" #include "hw/irq.h" #include "hw/resettable.h" #include "migration/vmstate.h" @@ -38,26 +39,28 @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) uint16_t val; switch (reg) { - case 0: /* Basic Control */ + case MII_BMCR: val = s->control; break; - case 1: /* Basic Status */ + case MII_BMSR: val = s->status; break; - case 2: /* ID1 */ - val = 0x0007; + case MII_PHYID1: + val = SMSCLAN9118_PHYID1; break; - case 3: /* ID2 */ - val = 0xc0d1; + case MII_PHYID2: + val = SMSCLAN9118_PHYID2; break; - case 4: /* Auto-neg advertisement */ + case MII_ANAR: val = s->advertise; break; - case 5: /* Auto-neg Link Partner Ability */ - val = 0x0fe1; + case MII_ANLPAR: + val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD; break; - case 6: /* Auto-neg Expansion */ - val = 1; + case MII_ANER: + val = MII_ANER_NWAY; break; case 29: /* Interrupt source. */ val = s->ints; @@ -92,19 +95,24 @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) trace_lan9118_phy_write(val, reg); switch (reg) { - case 0: /* Basic Control */ - if (val & 0x8000) { + case MII_BMCR: + if (val & MII_BMCR_RESET) { lan9118_phy_reset(s); } else { - s->control = val & 0x7980; + s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD | + MII_BMCR_CTST); /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->status |= 0x0020; + if (val & MII_BMCR_AUTOEN) { + s->status |= MII_BMSR_AN_COMP; } } break; - case 4: /* Auto-neg advertisement */ - s->advertise = (val & 0x2d7f) | 0x80; + case MII_ANAR: + s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | + MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | + MII_ANAR_SELECT)) + | MII_ANAR_TX; break; case 30: /* Interrupt mask */ s->int_mask = val & 0xff; @@ -131,11 +139,11 @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) /* Autonegotiation status mirrors link status. */ if (link_down) { trace_lan9118_phy_update_link("down"); - s->status &= ~0x0024; + s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST); s->ints |= PHY_INT_DOWN; } else { trace_lan9118_phy_update_link("up"); - s->status |= 0x0024; + s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST; s->ints |= PHY_INT_ENERGYON; s->ints |= PHY_INT_AUTONEG_COMPLETE; } @@ -146,9 +154,18 @@ void lan9118_phy_reset(Lan9118PhyState *s) { trace_lan9118_phy_reset(); - s->control = 0x3000; - s->status = 0x7809; - s->advertise = 0x01e1; + s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; + s->status = MII_BMSR_100TX_FD + | MII_BMSR_100TX_HD + | MII_BMSR_10T_FD + | MII_BMSR_10T_HD + | MII_BMSR_AUTONEG + | MII_BMSR_EXTCAP; + s->advertise = MII_ANAR_TXFD + | MII_ANAR_TX + | MII_ANAR_10FD + | MII_ANAR_10 + | MII_ANAR_CSMACD; s->int_mask = 0; s->ints = 0; lan9118_phy_update_link(s, s->link_down); From patchwork Wed Dec 11 16:18:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849163 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414209wry; Wed, 11 Dec 2024 08:22:11 -0800 (PST) X-Forwarded-Encrypted: i=2; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement Date: Wed, 11 Dec 2024 16:18:57 +0000 Message-Id: <20241211162004.2795499-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow The real device advertises this mode and the device model already advertises 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to make the model more realistic. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Message-id: 20241102125724.532843-6-shentey@gmail.com Signed-off-by: Peter Maydell --- hw/net/lan9118_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index 874dae4155a..5c53a4a1e3f 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -110,8 +110,8 @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) break; case MII_ANAR: s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | - MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | - MII_ANAR_SELECT)) + MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD | + MII_ANAR_10 | MII_ANAR_SELECT)) | MII_ANAR_TX; break; case 30: /* Interrupt mask */ From patchwork Wed Dec 11 16:18:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849161 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414155wry; Wed, 11 Dec 2024 08:22:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW8M6HobkKudXZM/fwyU+Sxqu3q3X3ewQ0noHlQgkC6PJKjaaL//uO/AvVHwyvVeaYin87QgA==@linaro.org X-Google-Smtp-Source: AGHT+IHTJ0+mbr/eHjzNAj4C+6tL9WFzg7od8qBK2Oyw9RYp1Q0uTVQ8PM7HQ7o3ghLjQQNrFgXb X-Received: by 2002:ac8:594e:0:b0:467:864b:dd6f with SMTP id d75a77b69052e-46789399949mr48720011cf.54.1733934124550; Wed, 11 Dec 2024 08:22:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934124; cv=none; d=google.com; s=arc-20240605; b=QgUV6nW6RwV9UTZa0nxjBuygbjDdThM46+JUTxycWKSmPFcD7d1RJhPXHyc9fz8L05 l4kBmj6LyE9h+Nw6pcWabSwjEtlrY+4kW36kLYQIBcWm+4Y6XIG0gGk4sCAtzOqHAR4/ K+jsZBv/Zgv6XOWZMdxnIAJvAgGMOD5da37UbqTBRK844BDiAmSQ5ehtJFXWRJqeESpO aKVkLUWIG1NqF64QIBWjPVbcWxOIsRxRddJawOLMB27lph1bCK48n9VCQmEvqNU946W7 fTLphMNaCAYmasZOR+Va7NBbPN0lhW6n8OL3ZDVifZt9iRO72ak9wfMi3iJeMIezzOZW k3IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jjHu6tm+33f5za7B2UGWHozRv7iZoKjmmA7yl7uJ0xo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=KuttCqfsSajzOCW230Ad4Xzed0llkjzREvs/Iw+VGPmx5TRP63WJJ9AViGRz9unxWM GPyWkf89KMVvLM3eb5x2Ym3SQgixorMwTHp7lYV1ePZzXdJxSa7uvMU0RdU2p/gY1eI+ BiSDabwpvPeZO6LGdbN3eCojRiQTz1pUMsQngSDXniur6kDydWzHRPxtZMaddL5OAqzV VB8Z3zkSHrs09v8Xd21Uob168OzsbyQwZ5LIoZ8rGn6PtSXGSNtBtMzSWZvD1gIOE8aP 6TsOpYkYIl0PwIuVgjIaNei83w0twmw4Y5vSPG4RBL6k9nFbDSAWmY4Hm0iN78QoC5FU Jhrg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tAMPGuUW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd Date: Wed, 11 Dec 2024 16:18:58 +0000 Message-Id: <20241211162004.2795499-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For IEEE fused multiply-add, the (0 * inf) + NaN case should raise Invalid for the multiplication of 0 by infinity. Currently we handle this in the per-architecture ifdef ladder in pickNaNMulAdd(). However, since this isn't really architecture specific we can hoist it up to the generic code. For the cases where the infzero test in pickNaNMulAdd was returning 2, we can delete the check entirely and allow the code to fall into the normal pick-a-NaN handling, because this will return 2 anyway (input 'c' being the only NaN in this case). For the cases where infzero was returning 3 to indicate "return the default NaN", we must retain that "return 3". For Arm, this looks like it might be a behaviour change because we used to set float_flag_invalid | float_flag_invalid_imz only if C is a quiet NaN. However, it is not, because Arm target code never looks at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we already raised float_flag_invalid via the "abc_mask & float_cmask_snan" check in pick_nan_muladd. For any target architecture using the "default implementation" at the bottom of the ifdef, this is a behaviour change but will be fixing a bug (where we failed to raise the Invalid exception for (0 * inf + QNaN). The architectures using the default case are: * hppa * i386 * sh4 * tricore The x86, Tricore and SH4 CPU architecture manuals are clear that this should have raised Invalid; HPPA is a bit vaguer but still seems clear enough. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-2-peter.maydell@linaro.org --- fpu/softfloat-parts.c.inc | 13 +++++++------ fpu/softfloat-specialize.c.inc | 29 +---------------------------- 2 files changed, 8 insertions(+), 34 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cc6e06b9761..d63cd957a19 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -66,19 +66,20 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, int ab_mask, int abc_mask) { int which; + bool infzero = (ab_mask == float_cmask_infzero); if (unlikely(abc_mask & float_cmask_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, - ab_mask == float_cmask_infzero, s); + if (infzero) { + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ + float_raise(float_flag_invalid | float_flag_invalid_imz, s); + } + + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); if (s->default_nan_mode || which == 3) { - /* - * Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag for infzero. - */ parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9bca03c4aed..c557c41b2af 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -480,7 +480,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * the default NaN */ if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -507,7 +506,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the default NaN */ if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } /* Prefer sNaN over qNaN, in the a, b, c order. */ @@ -529,10 +527,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -553,10 +547,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } + /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -576,10 +567,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * to return an input NaN if we have one (ie c) rather than generating * a default NaN */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB @@ -592,14 +579,9 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_RISCV) - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - } return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -617,11 +599,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } #elif defined(TARGET_SPARC) - /* For (inf,0,nan) return c. */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer SNaN over QNaN, order C, B, A. */ if (is_snan(c_cls)) { return 2; @@ -641,10 +618,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns * an input NaN if we have one (ie c). */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } if (status->use_first_nan) { if (is_nan(a_cls)) { return 0; From patchwork Wed Dec 11 16:18:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849189 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415894wry; Wed, 11 Dec 2024 08:25:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVDy2Fr4WZx80TOWbfGN+AJruPEPqoE0rcB8TeFrFGSjTWFX/2+unE9YOPdlAk90t9HLzhDKw==@linaro.org X-Google-Smtp-Source: AGHT+IER22kwp6tPgQCIdgWlyFCbzwpWyGlCRZuDY+onswV8cah0WSl7DRcn/PFj4Yyck98JCSmN X-Received: by 2002:ad4:5aee:0:b0:6d8:7a7d:1e6b with SMTP id 6a1803df08f44-6d9348d33e2mr62323226d6.10.1733934317066; Wed, 11 Dec 2024 08:25:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934317; cv=none; d=google.com; s=arc-20240605; b=AxsXCND9xoFyxhjCoF4nbWIdxuk+RvLH17q3sbyBUWe7qR2tbWusSTnlBkKRErcOPr PyxZ31+N4A+UepRJxMCPs0iwRt8tqlB/iZw/lWyV4W0KyRD8z001eVmmLCBytbMoVdF5 VwWVksWsKOoURbv97nUcvyDYZkDjBUEnFIaeVfB0ym9CbIPyueWYXrm7XLMFP2PU11CJ g4SY8y6aBN33J/WFrnf84LYA0MxbzYBVuKaZDDZEE0DrNsHiMYgF6cv+ARpdo1eGzKrW VwazZOV9qv9u5d1S257lTb+Y6mwbcR9Wwd1JPFJG6PZZBg0Jkv9bbDFZoCLYFpBFwPp9 WuIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JXAkJPzlbPpI9TBbDQ7RCzmNVKijs33Nwl+I0eteC5M=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=VK1yKxjKdW58/VsKweTSYnGfyGPVeMUu2ifYF7gsIyzbLqV3lWEDVYBB7MxBSMbMkn JbzUvApI9aM4R1/GKqH887z9h1dVLbTGZTmZffEqYdu6X4RV+cojJn9pSY6bMGDDy4vV 0t112s7oG5ElZVDRO3eQ+WWSXUmMZnBMFrrS2OXBlaRNM7nDFJ47dNTH4DB3W9+gQLOB n4VbWSLAV5jR/Ib0axkorIbA9BJqlsOX+a3IMfVvPaiQ0x+UEtwvILOmdfsQxEDaF2iS 5vyL6kiojWPA7Q4h+qsRJ27eVgjR30zP0TyRG1oc/8OJkJhTxisPSdh5ZToO3jG84hw+ Jv8A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J15HBVqo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd Date: Wed, 11 Dec 2024 16:18:59 +0000 Message-Id: <20241211162004.2795499-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If the target sets default_nan_mode then we're always going to return the default NaN, and pickNaNMulAdd() no longer has any side effects. For consistency with pickNaN(), check for default_nan_mode before calling pickNaNMulAdd(). When we convert pickNaNMulAdd() to allow runtime selection of the NaN propagation rule, this means we won't have to make the targets which use default_nan_mode also set a propagation rule. Since RiscV always uses default_nan_mode, this allows us to remove its ifdef case from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-3-peter.maydell@linaro.org --- fpu/softfloat-parts.c.inc | 8 ++++++-- fpu/softfloat-specialize.c.inc | 9 +++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index d63cd957a19..aac1f9cd28c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -77,9 +77,13 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_invalid | float_flag_invalid_imz, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + if (s->default_nan_mode) { + which = 3; + } else { + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + } - if (s->default_nan_mode || which == 3) { + if (which == 3) { parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c557c41b2af..81a67eb67b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,13 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + /* + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify. + */ + assert(!status->default_nan_mode); #if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN @@ -578,8 +585,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } -#elif defined(TARGET_RISCV) - return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { return 3; From patchwork Wed Dec 11 16:19:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849215 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417246wry; Wed, 11 Dec 2024 08:27:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUg5JbvuMEEBXBiYDgUk4v7VbqZAMp29+M/nBiKSpbzCufHLGOarEZnElADH2B9XhbDXkaaXQ==@linaro.org X-Google-Smtp-Source: AGHT+IElPiT6bITxavIBfiv7OyJMGHWskV7XTks/LfYJrP1RiOqPzEIGbC+EAw6Lxxps2hvKNWd3 X-Received: by 2002:a05:6214:f0a:b0:6d8:a967:8387 with SMTP id 6a1803df08f44-6d9348d32d0mr67200836d6.1.1733934463664; Wed, 11 Dec 2024 08:27:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934463; cv=none; d=google.com; s=arc-20240605; b=aw2a8z1L7GUNR4d7FJ98xw8zPvmBVmPDvRHAJ92oKdH2Ci0BBU69m/vvATOVkONv4b UNjHBp0r0Rb0o7AW9otZ+uF5uQwKoNQUqe8XgaA1b1yr1vYdHUpQXA4Luk6CU/Z/YXd+ fPGR2zitY6A6gJuK2d+Wg45FX6ublVIXpSIIjgMS3t62X/WeO25sGe4c0ISlBh7u8zM+ KzZ/phzHeSxjgv5nreUhX7UnIrgnCzRopF4IEtUZ4/hnhJo3X8PcyC+fspBry3krdCV7 WPtOLmZZdIeZuWjdYdGU74GG6SiRMNXlzXZDhoi7OlUuSpxzwBDMFwbVRpbfJ9gzMdww Sqjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+CHwXU6NrYplvrjpWt53iqb0JmQm6zXDsQafUaRrA+g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GSs/TrPS6VOZUQ8n56bO7xklasuL5TJ09Ai8rlYaU0ZUObDxTd4Nkw+bV3gkjyKVc6 MNPkPVDam5szVel/unGQySb89GlAZ0Y3ZxArR6uaD+QK9bkJ9dU+091cdueZ8y8POQDI +thTIA6TOSacoZlp2kMNjqR0lcLZsJKazf04Z8MhQNGbKw+VMU2FKtt+CoXER5saC28X PvTgCEQngLmY/+CaLCZ2hLPRu6XlaOP/3BaS+ZzDMfM+U39SEjUsQymfQwxiOVgQPXU+ Uw9OFnLR5Ia9sNhKUOUs9khknYtq64jAG9g3qJtMI9kmt3ixykVXFyiabMPfmGIuuXkb Q+Rw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IV6zNZ0l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result Date: Wed, 11 Dec 2024 16:19:00 +0000 Message-Id: <20241211162004.2795499-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org IEEE 758 does not define a fixed rule for what NaN to return in the case of a fused multiply-add of inf * 0 + NaN. Different architectures thus do different things: * some return the default NaN * some return the input NaN * Arm returns the default NaN if the input NaN is quiet, and the input NaN if it is signalling We want to make this logic be runtime selected rather than hardcoded into the binary, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. Note that four architectures both use the muladd softfloat functions and did not have a branch of the ifdef ladder to specify their behaviour (and so were ending up with the "default" case, probably wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set default_nan_mode, and so will never get into pickNaNMulAdd(). For HPPA and i386 we retain the same behaviour as the old default-case, which is to not ever return the default NaN. This might not be correct but it is not a behaviour change. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-4-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 11 ++++ include/fpu/softfloat-types.h | 23 +++++++++ fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- 3 files changed, 95 insertions(+), 30 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 453188de70b..0bf44dc6087 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, + float_status *status) +{ + status->float_infzeronan_rule = rule; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -137,6 +143,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) +{ + return status->float_infzeronan_rule; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8f39691dfd0..47bb22c4e25 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -207,6 +207,28 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * Rule for result of fused multiply-add 0 * Inf + NaN. + * This must be a NaN, but implementations differ on whether this + * is the input NaN or the default NaN. + * + * You don't need to set this if default_nan_mode is enabled. + * When not in default-NaN mode, it is an error for the target + * not to set the rule in float_status if it uses muladd, and we + * will assert if we need to handle an input NaN and no rule was + * selected. + */ +typedef enum __attribute__((__packed__)) { + /* No propagation rule specified */ + float_infzeronan_none = 0, + /* Result is never the default NaN (so always the input NaN) */ + float_infzeronan_dnan_never, + /* Result is always the default NaN */ + float_infzeronan_dnan_always, + /* Result is the default NaN if the input NaN is quiet */ + float_infzeronan_dnan_if_qnan, +} FloatInfZeroNaNRule; + /* * Floating Point Status. Individual architectures may maintain * several versions of float_status for different functions. The @@ -219,6 +241,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 81a67eb67b5..f5b422e07b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -482,14 +484,68 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * specify. */ assert(!status->default_nan_mode); + + if (rule == float_infzeronan_none) { + /* + * Temporarily fall back to ifdef ladder + */ #if defined(TARGET_ARM) - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns - * the default NaN - */ - if (infzero && is_qnan(c_cls)) { - return 3; + /* + * For ARM, the (inf,zero,qnan) case returns the default NaN, + * but (inf,zero,snan) returns the input NaN. + */ + rule = float_infzeronan_dnan_if_qnan; +#elif defined(TARGET_MIPS) + if (snan_bit_is_one(status)) { + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN + */ + rule = float_infzeronan_dnan_always; + } else { + /* + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + rule = float_infzeronan_dnan_never; + } +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ + defined(TARGET_I386) || defined(TARGET_LOONGARCH) + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + rule = float_infzeronan_dnan_never; +#elif defined(TARGET_S390X) + rule = float_infzeronan_dnan_always; +#endif } + if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the default NaN here, + * and some return the input NaN. + */ + switch (rule) { + case float_infzeronan_dnan_never: + return 2; + case float_infzeronan_dnan_always: + return 3; + case float_infzeronan_dnan_if_qnan: + return is_qnan(c_cls) ? 3 : 2; + default: + g_assert_not_reached(); + } + } + +#if defined(TARGET_ARM) + /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ @@ -508,13 +564,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } #elif defined(TARGET_MIPS) if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - if (infzero) { - return 3; - } /* Prefer sNaN over qNaN, in the a, b, c order. */ if (is_snan(a_cls)) { return 0; @@ -530,10 +579,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -550,11 +595,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } #elif defined(TARGET_LOONGARCH64) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -570,11 +610,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_PPC) - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule Date: Wed, 11 Dec 2024 16:19:01 +0000 Message-Id: <20241211162004.2795499-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Explicitly set a rule in the softfloat tests for the inf-zero-nan muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_infzeronan_dnan_if_qnan. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20241202131347.498124-5-peter.maydell@linaro.org --- tests/fp/fp-bench.c | 5 +++++ tests/fp/fp-test.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 75c07d5d1f1..fde64836194 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -488,7 +488,12 @@ static void run_bench(void) { bench_func_t f; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 5f6f25c8821..251c278ede9 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -935,7 +935,12 @@ void run_test(void) { unsigned int i; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); verCases_maxErrorCount = n_max_errors; From patchwork Wed Dec 11 16:19:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849214 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417206wry; Wed, 11 Dec 2024 08:27:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUM1h/aFt32cPRy1SHjCzfWWXnNkpQkYzdI6JouzN+To4dnpg3rdEell3CJxZiDYycdj4XG1g==@linaro.org X-Google-Smtp-Source: AGHT+IEkATM9eR3pBFyzbWraNs9UYd2kwmUKOt0PQJ/1kAYPHAn9XEKKwc2IcPN4pBzpS3m0gitg X-Received: by 2002:a05:6214:1bc8:b0:6d8:99cf:d2eb with SMTP id 6a1803df08f44-6dae2a306d0mr5100426d6.21.1733934457453; Wed, 11 Dec 2024 08:27:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934457; cv=none; d=google.com; s=arc-20240605; b=B6xARWTeq6BHMg0j8GKjwtEXQJ7V1GWwuVwch+KHlWZbY4h3TTiZnIPh/BVgK+h0+M k7f9kXZpLHcT01iq47iVrrYeNYqRKiNIBmEbAbyqbtDVQi/L00p9kVtuNQQUBhaQaHGq 5jNi/WKAKGOshzaC0m737rapJvidkplj8L8rMTYPLTxHzkH4YTeeTOxBoAdUYSbsfhmI 5N3enigDtFmJQYKoD8o4IGQ767D/S3ExcPvFaGSDVV1/wcVryWXryBl1Ystae9QivDfd xn0IqEI13kNmXHiXgxpb3posRdtzVF84J3M193L5okeM0pwbRptslAxkkq5PCmgEsOft cYng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HwP8TsYkVd3ug07uHGZQT6C7fkoiKCntvbbFB7VRiRM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=NqIjGKyz16ds7ugwDNZ6RYhB5gj6rWZWx9EPUiEJaRO77sKgWkopxL4hp2pm/ZXIFr oB2zsAw0dUDo/IVm4LctM+wdpfYtsZhEEi2ld/8TKt4xQUnlNBbVH/aQ2KW9vHeylkdl CRhsAhOlaPSpZmH7tTwiKFL1jGKTLB0iTusO7i9N2nXbb8NOfmvUxhgw6FXz3ncXUZL+ S+oq8cZkzkho2425RpeLlhYivSKtiE8l4DXBnb3ZHvGZmrFqjx+Nk9chCMzDuNYfqNmJ /IL5NbWvUx4Swq+Za4+6uXTzP4C0hKPSQ90ilvNc+5fkKJft0nfc/qaamdo2jcAKmfjf MPSQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DZHzssuV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:02 +0000 Message-Id: <20241211162004.2795499-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-6-peter.maydell@linaro.org --- target/arm/cpu.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..ead39793985 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,11 +173,14 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, + * and the input NaN if it is signalling */ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f5b422e07b5..b3ffa54f368 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,13 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_ARM) - /* - * For ARM, the (inf,zero,qnan) case returns the default NaN, - * but (inf,zero,snan) returns the input NaN. - */ - rule = float_infzeronan_dnan_if_qnan; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { /* * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) From patchwork Wed Dec 11 16:19:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849157 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp413513wry; Wed, 11 Dec 2024 08:20:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWjLJ8Xgt8T314H/PBqXTcsefjS5NlxhWODdwNEnIs3zHqGmfio0Tzmos9fp4Bm82jC3K7Ltw==@linaro.org X-Google-Smtp-Source: AGHT+IFgGlWdPzQlm97ZqY2x0gug3Al9PXyIqRMEYdjVpoAQS+Mkexuj3VylwEzmX53F4Os946ig X-Received: by 2002:a67:be0f:0:b0:4af:dcf3:b384 with SMTP id ada2fe7eead31-4b1d29c4cffmr2647969137.11.1733934056687; Wed, 11 Dec 2024 08:20:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934056; cv=none; d=google.com; s=arc-20240605; b=a713ac3hrZnlRwyTQIyOpcU3aRLOHRkfoYxqKrT6g0QpV0E3m2surcpIMzdKSI2R5t ZYXNbWUSOyhftsbptou22I62AdxE3hbzmxNVSZVTELYGH5QsvFBjBwrxvN8oseMnjWOZ fVpq4NM0+94MRzeJtycAWkHJBDedmoyoU1qH1raGsurq5KK+jOg3f10lCQYVaq/bdXh8 RHBYm2gTtfyfK844iuxsObl1lKcJH8/hXUnbp2z+NB3SqhbtcWmeVl5Ozn/UlOSPzY2E C7oeKn60n2M3nNeU9pY/9cPJirnN8o0FYz5RHKSMhXo4kV0UDarcVM/gfVvm+Swtpis2 DEgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T/PmqSLjuyiOzk/RkL1cFPZCkALByoouQahg0DiW16g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=HMMIpUifzIoQGZpU+zR4JGQGSFDip+YbYRi9m93zo88kT68wOXNxGUn6iszAr/k/9c BeS18I2w06Lpu35atbWbNLH5VBDZyZMzbNiXE67dsrd8R+97ZLg3BRPGO2pp5tTyut3u Z20clu0ZHEILREVetXjHDOj5CrlW+8Ia7yDX2yckVAZaZ//ITbH/p/fFkyYvWKYBPSTm Ty3OxOjY4OfzAqVkwEvIvrf/uy34VVHwth7/n+AVi07AfqISKpIsAhhpZaTI3pgx+6ix oTQKRNFqHTBtl2ZPAqzSxvbyAzZ/mdaQvrwj+nqeYwibCtW/CshBmycc2hqWp0YKJMni oc0Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l8qIUgEe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:03 +0000 Message-Id: <20241211162004.2795499-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for s390, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-7-peter.maydell@linaro.org --- target/s390x/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f3010..d5941b5b9df 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_infzeronan_rule(float_infzeronan_dnan_always, + &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b3ffa54f368..db914ddbb1c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -516,8 +516,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * a default NaN */ rule = float_infzeronan_dnan_never; -#elif defined(TARGET_S390X) - rule = float_infzeronan_dnan_always; #endif } From patchwork Wed Dec 11 16:19:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849193 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416076wry; Wed, 11 Dec 2024 08:25:35 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQr7UGx7TCiFY45BznLRgra9sKYJpaPIDIP67PIreiJxrdNOY3rlPZoOyPPuDAqIXCsmIThA==@linaro.org X-Google-Smtp-Source: AGHT+IEbGHrICJ4N8M72BpN4uVNbijVr0o/daIOULIxssETal/+VzEkToTNpXPQybkjuU0vlw3Rd X-Received: by 2002:a05:6214:19e3:b0:6d8:83bd:5cfb with SMTP id 6a1803df08f44-6dae29bc7a4mr5983806d6.10.1733934335620; Wed, 11 Dec 2024 08:25:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934335; cv=none; d=google.com; s=arc-20240605; b=XtgdDZGG8gTiC6SqzU76PZjjWIHosUxi2spr+jMG58LuIeUzkefa4eh1rtAws5s/cI DFzM35G2lsNcsWZ146gvLtnhUD7ZRQjgwBMhAc3PpzBhp+Nus4+H8TMQBfwCZ/Ew5NmN izCdeDwjT1C6IundFCadKeB4Uw//hewxnHBh62k0OvHv4Vxnujl5TCjtTf3zygK2nEth OdyR2iUfXsNrNQN8OTCGs9frZ7Wuo7gb4ocFksDo8aRM6o9GC8K+B0ip+17U72xtwdJ+ Bp0abwIsYcKmnxG+j3VRtBg3GxmH55IKJ5zOBASiSELAit8CrvNMvsqnwLZSX10f/4YK wojg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NzL75CnGj5vekrbIr9hglljRLm1m2p+xEVNazCq4Ld4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GzEMVawpxkHlrAHcaxK1o4U6gnvxNBmozl2aQlQW9J8o7nWqyPPV/9KL9F65Qef98P FUgUDTW7pPprvkq96QtrAWufOi74L+DxZfUYt3+MrI1cdjsHghEn7B0BffwIY2gWe0PK HcuiuCk9W2dGPmEt/fOT6eCDsg7NycRAPDD1S2plDV+OSC9Yo627SfxX7H/ar+w0sP8R fKLWpAHWxTrLhkdTVVRH34LmszU+F1dV+aDljCbLWN/gXZQ3Dp4dIMyYxb3nnE2NeCTm YYoorUVfmdyIDbc9zAUbLN9YOWmbzUF0pjEpVBgyQjHxOLMgk0uit3qucUatiPxcGI8K NxxA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cHL8z/LU"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:04 +0000 Message-Id: <20241211162004.2795499-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the PPC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-8-peter.maydell@linaro.org --- target/ppc/cpu_init.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c25..f18908a643a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,13 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db914ddbb1c..2023b2bd632 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -503,18 +503,13 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ rule = float_infzeronan_dnan_never; } -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ +#elif defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - /* - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ rule = float_infzeronan_dnan_never; #endif } From patchwork Wed Dec 11 16:19:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849203 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416818wry; Wed, 11 Dec 2024 08:26:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUnhmDmJGcx/KreeYUV4Hpq1alNQDH4IryvA2HyFi4hkO4zOiVvg71Vq3RXzmigJQURZM9WRA==@linaro.org X-Google-Smtp-Source: AGHT+IHFIIODy4gLw9zBEYQQQDsCnx1WUJrsW3cdD62TFkkR6Anm911r9HnOWqjex1klI6bb/R1i X-Received: by 2002:a05:620a:4694:b0:7b1:48ff:6b3c with SMTP id af79cd13be357-7b6eb444756mr616047485a.16.1733934415948; Wed, 11 Dec 2024 08:26:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934415; cv=none; d=google.com; s=arc-20240605; b=SdA93ZQ2VJz0MhPVhhUoJOOdU6Lt0tcr0sKfDykYko+DLzA68AklRsP40jbcNIr98r AyO04eJycPBstElhjs/USpb+5TEJeoJMwcGn8NfHFGUB6ho8oqXkReeYGWcly1Y35suK URA8uobtaurn0THnEqAOva31//CcfjyM2XaT1UDE17L0AAdtYAtaC8B0IUTyMur/SOoe 8FvfD2zZi18eh4V8VGXZ868IesSUObBEVzfVx+lwAHtNUmhevPd1/ZeqHpfuAveFWM0w c2sJGujnOe6k04kzLtMmL1iR4J6l1afk94lkgAD1Rx1q0gBUCe4H+YD9k/mkDZAZCr87 8oZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Q41LJZFRzxatWl3ymykPA+glM4cmXQHmBtmZ8EVJ7Yg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=T1eEYzgyA/XQtIz2gyzt1J7F/zQ+CR0l+ZOz5vZ2W94sINv6WpIHM8mQ9ZUxicYRbS ZSmUy9srZaSP2I4NeupA7036c+hXujEifAALq7knDvX1ucdJuEitJgpv1mUc7ih8IdEJ sCIDAYovTmVh9PvMP+dUUHTSvkmonh9XJE0/BuihIBjsuqj02Ufco8med2RtuC+gelRa xcj3K1PJ4+sn03PF0rsiGJLSCi/d9IiiGeZavpHa2a9ESMvsWeKpQaEc1Pck9j+lwKbi jm5DGomd1sfEkMXoAUUYEhQzpBCFDkU1tAbUjOj+SADoQvGaI5Km6sYMAfBBrkcD/agZ b05w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oS01Cv2P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:05 +0000 Message-Id: <20241211162004.2795499-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the MIPS target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-9-peter.maydell@linaro.org --- target/mips/fpu_helper.h | 9 +++++++++ target/mips/msa.c | 4 ++++ fpu/softfloat-specialize.c.inc | 16 +--------------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 7c3c7897b45..be66f2f813a 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -28,6 +28,7 @@ static inline void restore_flush_mode(CPUMIPSState *env) static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); + FloatInfZeroNaNRule izn_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -35,6 +36,14 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN. + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c'. + */ + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index 9dffc428f5c..cc152db27f9 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -74,4 +74,8 @@ void msa_reset(CPUMIPSState *env) /* set proper signanling bit meaning ("1" means "quiet") */ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); + + /* Inf * 0 + NaN returns the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, + &env->active_tc.msa_fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2023b2bd632..db9a466e05b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,21 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - rule = float_infzeronan_dnan_always; - } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - rule = float_infzeronan_dnan_never; - } -#elif defined(TARGET_SPARC) || \ +#if defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* From patchwork Wed Dec 11 16:19:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849205 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416853wry; Wed, 11 Dec 2024 08:27:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVC6o6dvf8bUhV/W2YxBzYa+uf+b8zeUgk9B1ozKxwVzPoUU6sS+XFfu6Nu+5+9qnJEyZdQSA==@linaro.org X-Google-Smtp-Source: AGHT+IFV+zIPKXvlVCT/ME9VRi3C17h0oQWM1UA+K0DH4jEOKocZnR+D6VH+Y0rXjTFnsO78z8Co X-Received: by 2002:a05:6214:627:b0:6d8:893b:2a13 with SMTP id 6a1803df08f44-6d9350678a6mr62598376d6.0.1733934419927; Wed, 11 Dec 2024 08:26:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934419; cv=none; d=google.com; s=arc-20240605; b=huDZawxCJUCw3QpFgO8TiLdav1v2JuyDGbTgeDioSHt7sJ8aH4cRWMJ35gI0jBmnWz FYVTkG6ncD12fnlrpziDZxbkkgo9kDSMi5zb+szeZIFI35fC1uw1x54Fq5R9GWzjHgy2 9jddTC92PdUT/TFHblf1Wc3gdqTjeqxyb46abMR/ojB4VmVRXHp/wvxEaIysKln2MjnU Dgw/NFN2gQAJ1Gasnfl4by+JvQWLTDjL9JZsLTC+4dnxopsgy20SvqJcnZetwQUSwRP2 LT7LGtsZjwK7C63ge7VqO5UEGHy7rty4XmxgAIp18Ji/wenxlqxn07poTjE93joV0zex AIpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ec4PeXlmg7CtR/PXfmSknGAM8RrcTIj+cvTbuOFtEy4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=b/MdkEvaWurTROzeUh7U7/ArUj7W9ljAtnN+vqntUzZy/RHPpYDkNLt4g/aGbvkXEa 5r1bmowsgoBfEb+Hr15SrqLKSldWwg9TTwuSDZsjXrVLD55SLUA7NuxQih6FB7J0q5Qb 2PsFuMJbD6ARuPPt2wmOAkj9Mr9NNaKfBu8dsg9Vl1uzh/cUuS54DHB8GSPRVkLboQEW FQYG0xsVv1AyC1ivoxPEbydCgJ+UZ5r5/1IpPRmqi/cALQP4RyTlC0w4d9e/22o6DgOz PV0ycssBv1HP1Pu+EeL7YqtXUCQGFyIWygGB3O/CAWqTtXJ7U6t26/pz8wAH8qEPNmNH d/Qw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pSTaD1Nm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:06 +0000 Message-Id: <20241211162004.2795499-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-10-peter.maydell@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de73..61f2d3fbf23 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db9a466e05b..7e57e85348b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,8 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_SPARC) || \ - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Wed Dec 11 16:19:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849155 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp413502wry; Wed, 11 Dec 2024 08:20:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXjOqzXzKYzhlQzVkc+jKk6eaG3QboUFeJ80UwiLnyVs3SRpI9oAETJavI2jaSmcLISNUXc2Q==@linaro.org X-Google-Smtp-Source: AGHT+IFyzmmGrYynplR2g9Rep0aCq+PpjILWUllD4rbnvjkxH0er0FEyOzKLBT6urKGI3eiAWWOn X-Received: by 2002:a05:6122:250a:b0:518:91b3:5e37 with SMTP id 71dfb90a1353d-518b43002b1mr785832e0c.5.1733934055769; Wed, 11 Dec 2024 08:20:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934055; cv=none; d=google.com; s=arc-20240605; b=frNNmKGbzS5ow0jM35aqRp2hIcNR+eH2kxy56o05I82MBPaIoA2nbHDmmCCCP1Pack k2wRlbIM4Yyp1IFYgRCph8+7cS6Y3cCg0XnEOhv9NqD9YQTnhsHIQdk4CzUcpFKtob/X Rl58sMC071RbbXwXvkHM4MYmIehYkUjwK7gGnt3M66MqqQfhBiXzfd4GQsf010l5AYRu A/DWcdkhmIerM7khr+JfCFax2YUswT1HnxYdt9CBrEH9tcO2yYtQKEh9H+sjIeZRVTrq BqAMeFdEWpLwRZjfgOZQB3bk+GAJez9q7pCkeOZCsJ4mueUA9osM1G3CNxnRF6ladVrX tFYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CQjRicSg/XdHnvLYpOYP7psZ4EG5XIl4wxja3fhCd1M=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=JnSjJ1ttzLhT9JDpPUz1M2RyECidmU6DF4YI8hiX1ORWFDgwpntibraLI0wci/9U9h 2ZQYzehQR9EG8yzozZXzCTENRstaDD22pqw4mtkmOKLotbFX3SykWdD0Be4/vMNEJ0wY dVeBPTwFEifaxHJokSODpJ7DsDFAEj9l30l1qpcAaVnxN0zIqi7o5nSAugd0dSYLa82M 5BAA7s/ccU7uJ/t4CRQapgjWnVwcBrHwx7AUT+6rmdjH8W3TtbjRnW+89Q9S3cfbbrrM NAra9RSBsG3kzvTjfFv88mkKkWZMnjHHX1nT6H+MusjS7CdhRd5ja4QenRF+1fkH9nro Vj+Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bhh0bEpM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:07 +0000 Message-Id: <20241211162004.2795499-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the xtensa target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-11-peter.maydell@linaro.org --- target/xtensa/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abaee..3163b758235 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -133,6 +133,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) reset_mmu(env); cs->halted = env->runstall; #endif + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 7e57e85348b..3062d19402d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,7 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Wed Dec 11 16:19:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849186 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415775wry; Wed, 11 Dec 2024 08:25:03 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX8csefD/gyCu6dsgjCSDmJbUtOhunOOVsHi4tZkocRI0cQ+VFXeS6JUPeVeD20fHhHIYU9CA==@linaro.org X-Google-Smtp-Source: AGHT+IGMBsM13eKT1XGvRsApXdo2K8hADsqlFCsYCxEg8+1uY6yQwpl5SPFbaRHtAnMg2Onr2bvN X-Received: by 2002:a05:6102:c08:b0:4af:eed0:9211 with SMTP id ada2fe7eead31-4b2477e73d9mr25546137.13.1733934303067; Wed, 11 Dec 2024 08:25:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934303; cv=none; d=google.com; s=arc-20240605; b=MVdT6MYvQzZUJSoGB+BUEmCzCov4jYocvHZFTTZy76t5HxeRH+JJnkTME4+tg/gEa0 vSqukmrUHwKHg3LZCDwZ8gbdhqnvQXLL9zuiDaIFSFZ/ApuXuIMbQ3z/rpACQb7TZExG +lc/FXk6/MFmL5AukYIaVAIZYnJ6ngLTRKmLbKvRSfftdIXbv+0g3re5Mu6xzOw3jgX7 Ivxoy3nrq2MeOzT6xoadC3dz0GGLPangCoVx1QlFsJzL2fRSs6k4X8xHPPf52Uj1CyJg Li3mtM1IOtBmvl7UEnvlRKS7I94/PQ/0bp55hg8ulTm7t8aUX8QtoKI47d6D3SKhANY4 JdTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A6eEv6wPqQgMdCISzrXsTLaQsxZwE/ao0DoOYZ7nU5Y=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=aojwsC9Yciwj7QcglQ8CUOu2yMHINBccHc8f/MnE7ebzcrg4x6hrlXEKWHG6PFHmWn h0gFfirsqmWfWcN/vaHHLTKvqx50X7tYq6BGQnhv06ev6nrbH033Ujg+NR8jTjNlOGAr pfy54wffHA64CnCRztsrnOjGWCXYpkKZgouTCqh9ZghREQ8R1JnwBR6xl5it2KD9Whtu V2NlSL51ucXxrklZ69SAqQ/LKIy8J6cFRqjgyTQgeVFDeGWGV7PUKpKECD+ZL1WOBllH StABn8T4NzsOdKydv0isxiD768PNK3GVTbRlATo+dkTFKVOBUWzQs3A+wjZpiQVonSOQ 1KTQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wTvk6kRj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:08 +0000 Message-Id: <20241211162004.2795499-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-12-peter.maydell@linaro.org --- target/i386/tcg/fpu_helper.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb2977..3295753e075 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); + /* + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is + * specified -- for 0 * inf + NaN the input NaN is selected, and if + * there are multiple input NaNs they are selected in the order a, b, c. + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3062d19402d..ad4f7096d09 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * Temporarily fall back to ifdef ladder */ #if defined(TARGET_HPPA) || \ - defined(TARGET_I386) || defined(TARGET_LOONGARCH) + defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' From patchwork Wed Dec 11 16:19:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849187 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415795wry; Wed, 11 Dec 2024 08:25:06 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUInRm6j6rSx8C2K2RnRg87QcZIxi8mFY4CmF0WdJ8qFqwohB3J76UtltrZAU8JzOMwmKf9Zw==@linaro.org X-Google-Smtp-Source: AGHT+IEvyuQBcN7dmZ55sTu1dtE7e+TMrq94EITHkms7RaLGTg5l1wVerCTeResfqCSpb8l/bPTF X-Received: by 2002:a05:6214:260f:b0:6d8:8466:d205 with SMTP id 6a1803df08f44-6d9348d1bf9mr44765606d6.6.1733934306002; Wed, 11 Dec 2024 08:25:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934305; cv=none; d=google.com; s=arc-20240605; b=gnWuXNkbZt8ftmZMtvmPC7/TBKjUqAa9gBWsY++raFZG67t8m7s/C4HbkmLibnpAGj 3H8zlywB2V0i48igj8E2zL4nMfek8+TgoeiYUu7hQ2Hp55HJpb8NVzXTEcmLkSrAkbOY LI5SjqSgCIo99lcn/xaQSJyvWWxP58BQmONaSPOvXKwVyxim6jd1TOQ4QjDJsVN35yJr jlppl4OaDl3oYN++C6gVwuqgdJGyI9p2Y8kf3Pog1ysUzLF3PM9+3G38ZpPwZ2erEOse DpxfNgUdoPyhcsuQ9GOf74neibzkTMaEhyKEIeer404fXawSOZgUtoJ6wtG4+Pm7KiOy A8EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MfZN52pgrp+/nZeB9BI1gMkKMPo4Kihy7pjqat+nckw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=HgFccQVUkygcywGpjweusb1VyKIvlcK1tY5docyfj37sbu3hynPoyxCP9HkvK3OQBz 5WpX/HxDLHFod9YY2Tji5xeZp+dXmcPDVZFlXWi3b3l6V98r8ftMRo9n442oSjIKkBF3 VfCp1u/v8RZe4blPdMeE+Anh5cX25pVFHV/QpFVmB2qGlAK06NajujguJDBfMKCo2qkM zl6X7Xax2opwrMQlPTXbUA4YgOca59SgPwvqgNhebNlBXXdjAR2De6KLkmY34ZgJH1D8 aXPczNLoiYHKXC4qiVVK3GSMe6FM9WsdWs50M0tbR4OZ6B5nuTKHApYBzn1hnAMedeSa XggA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E2JLlQaI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:09 +0000 Message-Id: <20241211162004.2795499-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the loongarch target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-13-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 5 +++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 21bc3b04a96..6a2c4b5b1db 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -32,6 +32,11 @@ void restore_fp_status(CPULoongArchState *env) &env->fp_status); set_flush_to_zero(0, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ad4f7096d09..05dec2fcb4c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,12 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_HPPA) || \ - defined(TARGET_LOONGARCH) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ +#if defined(TARGET_HPPA) rule = float_infzeronan_dnan_never; #endif } From patchwork Wed Dec 11 16:19:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849190 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415921wry; Wed, 11 Dec 2024 08:25:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWbtvRsPrJlmuyno8aUXHFKOO9JaJ7mCQplpWFFy6j0DWPMe0PRzB7IWlGHPBrfhv7WmvWkiA==@linaro.org X-Google-Smtp-Source: AGHT+IHFynQH/wf0xH8H6jAGbWlcC//vfMofZB3tlut4EQmx6gDEjTm6T001Qo5rfpEptIvMH+so X-Received: by 2002:a05:620a:191b:b0:7b6:cdd4:bde1 with SMTP id af79cd13be357-7b6eb420131mr583510085a.1.1733934319389; Wed, 11 Dec 2024 08:25:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934319; cv=none; d=google.com; s=arc-20240605; b=lU6tyA3GSLppdHk6hDDx92q/3pHwnqIXf50F6FgoZSeDdEz8S/iyVsADOr3ozMMgbW GJ1vuFg9Nb4VNEB69pl7RQBCUfmDnj4glUAUEK7JlUo+R4TI9ELbAFQn/I2V1cWMSiTX yviFllApDDai90BmD9kOv/juSIYcGxnJroS6RI2xdionx5jScEBpOgVlTJLCYGE2L8Mt UsRX1juNcLGhoP6YetxqrqlXSRxMxHlXkBcoM5DbU1E88gNXdBUC94GSdx5tgPoIlZ3q zK4EKG2TYa+S+u2+R5uFjQkpLfqaogQGZXNHHnEbRo3mE0VfIuIRG+lgb3FkmT8Ctcfo 7Oxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=129ef8vVSPhcYKXwuPVUePnnMXZtavBkurzU5VPKzhM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=T79o0DAfAMwcmvalUskjE1VCMb8bVFZ+LMLcpiIZhIMdqqW1cG8bxDaYMWYQvqsjXP WXKz1diF+q3imVwqB++xkY5QpSH5Qaj3s01Cvn8MPeTKUY5vsYHhoUF+R7gPC5vm4Wvb TFpxQ3rJn24Uk69zvElb2cLD96HLzXCy3l8oYIh6oIieRmdWCbfJ8Eckdm4u/rP167do bKmKS/6Pn5rhM4MoYhtXvfc4m5n8yKFeaelCW4oMZwZsuLW58GB21UheyOOIXpXzyejY MMYjibCvFBH/Vufp5PnTWkiXTTHipJmDJoPIu3T+KO9EapdXHROURPQHz2leYqrFYj11 3LzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rHcRkOb4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:10 +0000 Message-Id: <20241211162004.2795499-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the HPPA target, so we can remove the ifdef from pickNaNMulAdd(). As this is the last target to be converted to explicitly setting the rule, we can remove the fallback code in pickNaNMulAdd() entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-14-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 13 +------------ 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 0e44074ba82..393cae33bf9 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 05dec2fcb4c..3e4ec938b25 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,8 +475,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; - /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -485,21 +483,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ assert(!status->default_nan_mode); - if (rule == float_infzeronan_none) { - /* - * Temporarily fall back to ifdef ladder - */ -#if defined(TARGET_HPPA) - rule = float_infzeronan_dnan_never; -#endif - } - if (infzero) { /* * Inf * 0 + NaN -- some implementations return the default NaN here, * and some return the input NaN. */ - switch (rule) { + switch (status->float_infzeronan_rule) { case float_infzeronan_dnan_never: return 2; case float_infzeronan_dnan_always: From patchwork Wed Dec 11 16:19:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849198 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416488wry; Wed, 11 Dec 2024 08:26:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWiTZJKIIfR4tNbrJmxwHbtmmsyqXUAJ16PuYE0CUUmxQ37eideXjUBgdjR9QaaZwUOGOSXgw==@linaro.org X-Google-Smtp-Source: AGHT+IHSMDMa6u/QzHDTuwaOLl9+4cQMavk4jL/Sa4tj9Viql2Tt/jYX0VThWiFef7xsvRoa//qu X-Received: by 2002:ad4:5bc9:0:b0:6d9:2e46:dc35 with SMTP id 6a1803df08f44-6dae2a3d5b5mr6294106d6.25.1733934378888; Wed, 11 Dec 2024 08:26:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934378; cv=none; d=google.com; s=arc-20240605; b=KhYrAJUN/PgNG9UtH/sAMzhp9kTiSbsGexFBViMurJxxWnLDUzMUnyX2vo+8Ddhhje r/IeWNpYLjO8CH+XcF0H4ElCO5qLhagOVWwA9g6cIu4BkVaceXC9MZ31eyil5Mu/w7UZ EATMyj18GaFLHG58/DL87kAOBVnMALnlB0Yw3vf2LImRIPw92el+w46At81AhwkzkeJM Rv+e5STpSVkoGWTDAuvEBXh9OIgCaYemkT8LjXn+ZR3mQZvpsRNkrL3uRAkigBsbe6hx HKi/FwuQBrnaHdzq6U64VA0PG0WgscpvgqXkfdKVjIyXK3d1uFx0IelVWNE3I1WeQN1s RzuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nW62S+pVfkUdfFUsUNvfDmxePuMcoH99NH/YmsJ1zQE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=bmJdY7JMrGjV7ostFnL85Ql48+VL9ySy/JLGzYxhsgz834pGYhxd8ld83P4gklwY+n CPaxsMrUW5+656TabKlJ/jnUoZxIBW35Cip0G9yiXO9eGdQ3843EligdK1JYsI0efi2h OOaw/jXUaplfAwnim7OBFlcbtri35miFKCgezcediQxAY5aeaVZ1RHgvpef/99dHAUTg ugME5s3x1c7GIr/jjyrLX2Eo7MoWVeWuiEb0eV50d3fm6PgzChRTkimBWSNy5Yg+Fg8m 1GQeeLsmlTGbPQZLsVOvGIq9Vsf6HdoFCr6IBaRCaTgzccKNaS7qf/UfkIf5rBTD4Q22 S/WA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="IQmp//B1"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd Date: Wed, 11 Dec 2024 16:19:11 +0000 Message-Id: <20241211162004.2795499-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The new implementation of pickNaNMulAdd() will find it convenient to know whether at least one of the three arguments to the muladd was a signaling NaN. We already calculate that in the caller, so pass it in as a new bool have_snan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-15-peter.maydell@linaro.org --- fpu/softfloat-parts.c.inc | 5 +++-- fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index aac1f9cd28c..655b7d9da51 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -67,8 +67,9 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, { int which; bool infzero = (ab_mask == float_cmask_infzero); + bool have_snan = (abc_mask & float_cmask_snan); - if (unlikely(abc_mask & float_cmask_snan)) { + if (unlikely(have_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } @@ -80,7 +81,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, if (s->default_nan_mode) { which = 3; } else { - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); } if (which == 3) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3e4ec938b25..a769c71f545 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -473,7 +473,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *----------------------------------------------------------------------------*/ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, float_status *status) + bool infzero, bool have_snan, float_status *status) { /* * We guarantee not to require the target to tell us how to From patchwork Wed Dec 11 16:19:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849209 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417011wry; Wed, 11 Dec 2024 08:27:15 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXg8gIwUBU2heRgm7AP0A97UdyMJ7qzSaiK1wmYAWtW8/h+C8YfWoKTKjk+bB9JleQH/+JQqA==@linaro.org X-Google-Smtp-Source: AGHT+IF9TXVLJtwKclTapqpe/UTD8S1uNVOPRe3kaBuS13axXiPHRoZ/3ihEQUe8BXbnNVrCxezC X-Received: by 2002:a05:620a:240f:b0:7b6:cd90:c0e1 with SMTP id af79cd13be357-7b6f1bfef34mr58233785a.37.1733934435284; Wed, 11 Dec 2024 08:27:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934435; cv=none; d=google.com; s=arc-20240605; b=VTALL9IiEmvhineLb6kg12Q3FBMYKXc4kakKFOOLm3q27C5JetwvJh96x9jEdmn79d Y80+p2wp2MBMTyDCdHMaQJl6I7Fyzik279wbLIrIW+xPPPGbN7G81Vjb+LKslYj51j6A 02dePrhajPFptOiXmkVi8nwXs6K3VSqdf+cKbX1KV/b5JdIdQ/DCJvDzDoamkJ9A79EU mC6qLVXG7By80BMiBO+BWYtOcZODZJoBxbYNEw00T2j/p5Nsh+zFxL/muaxaI8M0Dz11 YuWc6DQYwsy+uftvMWJy03lWOsW5XIVRlHbCW/774MibA/AVgjUYpdU5s617xLoTcaC4 0upg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=m+1slj9CEPjQ+UJLwRK3O4Qe3zcWWfdTbryXtY+6Fyc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ZrceBTYPB99L5qQ/34svCo1wQ1SCg66fVX/NcfEj6jQizfnbO376nXjk9Fb6ZFchgD B3dAFYTn9si6PofVmQYrzr4zdJ7HpLibwJkmw2y/VydOtH66MjbVyRXXX8154WRmuyyF lm7qqOnnvRY7IQsGZ152fWUpLNneav6UYqpHZxMtZrlOEVxQaWPQgMfF/bDieKDZVY7w ihz+4Hx4klcrVU4NoB0ziMT4oKEu8Nr7GO/zBE2lMHNwI/pxWINk6DbCsdU85WrBIY9G VO+iDgcdSYdE0Tm5W8PEiSP/2nFKug3xfh44wNaZ+7HHDhgEiTkOQkuOqpLM4b3UQdCt Fe7g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=COzxIHnm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd Date: Wed, 11 Dec 2024 16:19:12 +0000 Message-Id: <20241211162004.2795499-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 3-operand fused multiply-add operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary because pickNaNMulAdd() has an ifdef ladder for different targets. We want to make the propagation rule instead be selectable at runtime, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. It's valid not to set a propagation rule if default_nan_mode is enabled, because in that case there's no need to pick a NaN; all the callers of pickNaNMulAdd() catch this case and skip calling it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-16-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 11 +++ include/fpu/softfloat-types.h | 55 +++++++++++ fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ 3 files changed, 107 insertions(+), 126 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 0bf44dc6087..cf06b4e16bf 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, + float_status *status) +{ + status->float_3nan_prop_rule = rule; +} + static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, float_status *status) { @@ -143,6 +149,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) +{ + return status->float_3nan_prop_rule; +} + static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) { return status->float_infzeronan_rule; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 47bb22c4e25..d9f0797edaf 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -80,6 +80,8 @@ this code that are retained. #ifndef SOFTFLOAT_TYPES_H #define SOFTFLOAT_TYPES_H +#include "hw/registerfields.h" + /* * Software IEC/IEEE floating-point types. */ @@ -207,6 +209,58 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * 3-input NaN propagation rule, for fused multiply-add. Individual + * architectures have different rules for which input NaN is + * propagated to the output when there is more than one NaN on the + * input. + * + * If default_nan_mode is enabled then it is valid not to set a NaN + * propagation rule, because the softfloat code guarantees not to try + * to pick a NaN to propagate in default NaN mode. When not in + * default-NaN mode, it is an error for the target not to set the rule + * in float_status if it uses a muladd, and we will assert if we need + * to handle an input NaN and no rule was selected. + * + * The naming scheme for Float3NaNPropRule values is: + * float_3nan_prop_s_abc: + * = "Prefer SNaN over QNaN, then operand A over B over C" + * float_3nan_prop_abc: + * = "Prefer A over B over C regardless of SNaN vs QNAN" + * + * For QEMU, the multiply-add operation is A * B + C. + */ + +/* + * We set the Float3NaNPropRule enum values up so we can select the + * right value in pickNaNMulAdd in a data driven way. + */ +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ + +#define PROPRULE(X, Y, Z) \ + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) + +typedef enum __attribute__((__packed__)) { + float_3nan_prop_none = 0, /* No propagation rule specified */ + float_3nan_prop_abc = PROPRULE(0, 1, 2), + float_3nan_prop_acb = PROPRULE(0, 2, 1), + float_3nan_prop_bac = PROPRULE(1, 0, 2), + float_3nan_prop_bca = PROPRULE(1, 2, 0), + float_3nan_prop_cab = PROPRULE(2, 0, 1), + float_3nan_prop_cba = PROPRULE(2, 1, 0), + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, +} Float3NaNPropRule; + +#undef PROPRULE + /* * Rule for result of fused multiply-add 0 * Inf + NaN. * This must be a NaN, but implementations differ on whether this @@ -241,6 +295,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + Float3NaNPropRule float_3nan_prop_rule; FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a769c71f545..b4f3f0efa82 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, bool have_snan, float_status *status) { + FloatClass cls[3] = { a_cls, b_cls, c_cls }; + Float3NaNPropRule rule = status->float_3nan_prop_rule; + int which; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -500,145 +504,56 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } + if (rule == float_3nan_prop_none) { #if defined(TARGET_ARM) - - /* This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. - */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + /* + * This looks different from the ARM ARM pseudocode, because the ARM ARM + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b + */ + rule = float_3nan_prop_s_cab; #elif defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; + if (snan_bit_is_one(status)) { + rule = float_3nan_prop_s_abc; } else { - return 2; + rule = float_3nan_prop_s_cab; } - } else { - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - } #elif defined(TARGET_LOONGARCH64) - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(c_cls)) { - return 2; - } else { - return 1; - } + /* + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + */ + rule = float_3nan_prop_acb; #elif defined(TARGET_S390X) - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 2; - } + rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) - /* Prefer SNaN over QNaN, order C, B, A. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } + rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) - /* - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns - * an input NaN if we have one (ie c). - */ - if (status->use_first_nan) { - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; + if (status->use_first_nan) { + rule = float_3nan_prop_abc; } else { - return 2; + rule = float_3nan_prop_cba; } - } else { - if (is_nan(c_cls)) { - return 2; - } else if (is_nan(b_cls)) { - return 1; - } else { - return 0; - } - } #else - /* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; - } else { - return 2; - } + rule = float_3nan_prop_abc; #endif + } + + assert(rule != float_3nan_prop_none); + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { + /* We have at least one SNaN input and should prefer it */ + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_snan(cls[which])); + } else { + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_nan(cls[which])); + } + return which; } /*---------------------------------------------------------------------------- From patchwork Wed Dec 11 16:19:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849220 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417391wry; Wed, 11 Dec 2024 08:28:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXFmzV+D0DIk2rex/tfc0OgiMZ1oEfSOfF24KAugm1zNIQRmCRjxkDkeWmYrR/q+Z4em1DTmg==@linaro.org X-Google-Smtp-Source: AGHT+IGN6bifV9DY6zjog+kd+TAb52X9Tv5RCRonPKznhH06Jm5JQdLHE1gc5A7n2cPZuzVcM6aK X-Received: by 2002:a05:622a:1183:b0:45d:8513:f29a with SMTP id d75a77b69052e-467892e96damr52366331cf.9.1733934483933; Wed, 11 Dec 2024 08:28:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934483; cv=none; d=google.com; s=arc-20240605; b=NxY75G8BSCI5Ht4mK2hj7XgCpCDTMj4zqTSb3V3Jpi4uasltNnWCqCtYqLX6iXu848 +Nn5MxCdp3KxDGxTpqACK1J0VHYZIzTy43c0iC7tfrmc1qHpSTX1TK4dahyqXytje6wN r8QREpFzpgpNhZTQAOqHN6wRNiA7rrG57BUHc78F9mitq40KMWRbA5bONAC6akpvb/zP 8FR32fw5PSz3Ivxbe7sYvZ//IHiWE0/Zal1RMGvkTSXbvLg10/LhRODOihEmbOnSzOyz V4OVvUoQLdn7GXgcad7FOd6BE3LiMwkRgQQ3k5evknN7UCuXj8f1bcODh4eqbYZHavl/ jahA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VgRz67Z5K6+YnxII3Thd0LIi5lCTv/FCJxlYwTXEoK0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=L4B5dV7rComja2uKGyYCRMwyjRwMfMlTLOi+DfgJ8w4UuuYL4VRpVqfV9N15rhry35 bMs1anloBolhf5nwHiKCEx7BDc0a1znGaGnjbvQ70ObHmFSinB1jcA5A4qQ+ULNI6pO9 7LDQdXco7M1qcZZZHiZE9YCVyEnLXV2fIN9mBzoESSmosaf8Zcdfo8DivvPydwy838+u Rq2Nssy7WKW6Tn7WJwwXbm3ycdLP0dqOveD7X+gdwsUhp0VpQ9cze4mKDZmwNmD1DzLY DfEx2bayR7rveKvNZSUP1GDfcgKN3BUqFUGqwOj6vEG8R1dr/JfOH0rxglj8yB0D008g dZkA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S5AL4420; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule Date: Wed, 11 Dec 2024 16:19:13 +0000 Message-Id: <20241211162004.2795499-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Explicitly set a rule in the softfloat tests for propagating NaNs in the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_3nan_prop_s_cab. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-17-peter.maydell@linaro.org --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test.c | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index fde64836194..39d80c9038f 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -493,6 +493,7 @@ static void run_bench(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 251c278ede9..f290d523ab1 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -940,6 +940,7 @@ void run_test(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Wed Dec 11 16:19:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849217 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417276wry; Wed, 11 Dec 2024 08:27:49 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVOvoD4jcQSVF9bDR3UzQ7WbOzOYIDjxN+vJo8VRTsDZUU0ePtbrpLDdw8wyZQkTqAHIBt72A==@linaro.org X-Google-Smtp-Source: AGHT+IGtrX1DBJ+Ry64UPIYv2vPNodSjIVthdKaMa+T7AOzeAlma0t5UUItVhPiKKyykIon3Inbz X-Received: by 2002:a05:620a:3955:b0:7b6:c6f8:1d2f with SMTP id af79cd13be357-7b6ebcbea4bmr637315585a.30.1733934469287; Wed, 11 Dec 2024 08:27:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934469; cv=none; d=google.com; s=arc-20240605; b=iMZUCgftIf1vRilp3CoWR7UL9TbQ565m0uxUjlHPzYCdMHPoRS08cfU/HjsOZtZ2Zz 2DJnbNc/Pnbjoqe0LR5HJYC1wZHmPjHoieBEgumCMG+TIjIpI20XT8OIZAqrzBBI9MYQ s0Jd4xsYvpGhR6j1kSvgpXcUN0B+2P1zTNS+7YNgnH7dtUC4M6cj9cHZylApm8+MALjB +kwu/5arA62tUcassYCJn16KBawq2Dixvj2GzZAB3ojw+cSEHQrfskoB/wyBDUhWE4hY WeEOLuaa5Ks1SqTtQnh2Y+Orpj0Qr4+caI82pFEV2zmmtHiYUdMBvjGerukUp5KF5ooJ er4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8h/sNzFR5aix6eqqSQJk01xGJeoXIpNBM9AztS4My+s=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=S2tKSZlVyDlAQypMcbvJYPuOAWLSLUWWXMiO76gx+0Cf0z9/UUrou8ehHnyeYYwvlc C7nLNlHgpabFeV1fqK0srGB9VtT1rejBm8+NrAN28TIuZ9lsv24ZJ/FHVkLMtyDw+U5C DDcEXGWY7a65CV7NtwoAklSfWP54r6OG/SAaGPnt6Sq+EMDiyoDxCjSekZZ1QwaGxgKx 9vPkD8CAvGLx04P9lY8NJ9rvs/Rw8ff3vpdwccnbvPPbBAm6RbVZz+pJglQYuCq412uT ixVrfkZLKXG2rAtNFe0LjOFc/HBEkEcYDD9QGUj0KL9OOwGT/2vZ55xqxadIurYa4Q9X tERA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TuWWeRex; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/72] target/arm: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:14 +0000 Message-Id: <20241211162004.2795499-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-18-peter.maydell@linaro.org --- target/arm/cpu.c | 5 +++++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ead39793985..c81f6df3fca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,6 +173,10 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 3-input NaN propagation prefers SNaN over QNaN, and then + * operand C over A over B (see FPProcessNaNs3() pseudocode, + * but note that for QEMU muladd is a * b + c, whereas for + * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling */ @@ -180,6 +184,7 @@ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b4f3f0efa82..3a2d0444475 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_ARM) - /* - * This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b - */ - rule = float_3nan_prop_s_cab; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { rule = float_3nan_prop_s_abc; } else { From patchwork Wed Dec 11 16:19:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849212 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417158wry; Wed, 11 Dec 2024 08:27:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVlWIcAlMlBssdnBiyfj1ui8lGHBenBz1IueA3H92XgEfrZUcy1utPO0XsRtmSnblguXam2hg==@linaro.org X-Google-Smtp-Source: AGHT+IHm4AgqB3oSnSBTyl22eXX3IldYwL7LQoyZxf/fcyq48W+A4zq+KzKMCQsMPidqqqKip6tM X-Received: by 2002:a05:6214:2682:b0:6d8:8b9d:1500 with SMTP id 6a1803df08f44-6d934b7f066mr60923526d6.36.1733934451878; Wed, 11 Dec 2024 08:27:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934451; cv=none; d=google.com; s=arc-20240605; b=VteXzVueOm9yS2BpxaAKLgqiJ1TlENml7PRP9cyFOdGFFQwEL1z2YdlCG6GH5Pg96k XonBlL/BBfgxWVT9YXUf7u4l2RSQwWDWSoadt1l4YKrG5dVA8HG10zFNpTExG7hNmE07 Q7re9QExGFn5I5coENk5YXDseU04Np70FUGIrlmIMEwk2npSwWrFHjwR6A9OEoG4ZLFL GtYJjYRwdOuN/cimmCYR1/2JWnWzFFqX3/p1ePR3bQu8yqGfdRFYXTsYE/i/FIkT6/Cb D7vEGjIcvWg11Hn2Y9kYDfEDXoYLKZ/tErPs082RCSOi/uTQCA1GPvJCkTxzqj5GBRkf UhBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9JNv5O6oxFzvaBtjpDgniZj0/Bs8bCD6Hgo8p0cpegg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=RgDGNd77JczA+TV6C5dHxynLAQ5sNxZGO/NPRAIWQs/aPf4uMWcbhg8cPs3kQwF+Tv kzp5hi7Bi6r87i1qm5qA0hMIumtRexStvTT6qr2vttorj61ijy5HhUAHllSqCdsvzahF 7YLYaCB20RyGGlsZ7D4w9lE7NPO6crn/0iy3lfoZ3qW6/9z2upyITKFv0tiYXlILOy9W Elw5NiIB8S+XO8RbEVvFEoWUwmPJ+/xhwKUf1GDcIUWgpD6mvllgXi02gQIbEPvTmFIM lMnrxi7YDgH4iuD2rq1AET0YufUQR9JeZXjVCEpbAmLSxefPvlmmbuS0DZOFmf3Vl1LW Lh3A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zw675H10; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:15 +0000 Message-Id: <20241211162004.2795499-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for loongarch, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-19-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 6a2c4b5b1db..37a48599366 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -37,6 +37,7 @@ void restore_fp_status(CPULoongArchState *env) * case sets InvalidOp and returns the input value 'c' */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3a2d0444475..d610f460026 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_LOONGARCH64) - rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) /* * If fRA is a NaN return it; otherwise if fRB is a NaN return it; From patchwork Wed Dec 11 16:19:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849268 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp426342wry; Wed, 11 Dec 2024 08:44:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXp+SV1AcfQVFCAfoybtYkQZIy3pMJIG0Hrvs+a2WiFqyf42pozvRoS4MAwWy/iUNuPpHjffQ==@linaro.org X-Google-Smtp-Source: AGHT+IE2BmKx4+0I9mhZXk453RL6kGgqfwO7SxF5Gud3AmAHEjdXVZgnaWu9dED4gJl14Ucb2n3c X-Received: by 2002:a05:620a:6507:b0:7b1:11d9:446e with SMTP id af79cd13be357-7b6eb436896mr600091985a.3.1733935471697; Wed, 11 Dec 2024 08:44:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733935471; cv=none; d=google.com; s=arc-20240605; b=bMQLYfrQwRVlnD8LWEvc4ey/D17+2nBYV6gX+VtA87Kz8tROPAENH1LTWzvhgBV5gh 1gZPeTY3bcaM6L6/dkkQI0ZcxAzMaoLyet4IgC6PV9ai9fKFKQxEkGUfk0I0sdZHtLK4 KEE1AXd1dKPQQLqRpYqbuJJAx+L0+Jc0nHKNw4LodT2KU7QpUCCQITnEvUe8iwfq/0D3 AQfL/ri3zjSPT4cTOi42gF82sIurKv+Kt/3yhjITEGSo6eyFcsHNHa8M3A/lITaGh15E ELwFOWQi8+KgcPprhRByTH4qWIUry3ZTXQgD61flltiDB2zWuDOgxw58zQ4pjPFszVly 163g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Lo7VMCHiiH9lz9IaE5gLakal324n4TYjmC+cVkhARM4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ltd9x4HUN4RxcE5/ZiF4YF6vAbz7a/1ZktDFn43bODuRun+HFIeVUMzHl8I8DmSqMh qV4DZlig646xXhTkIonbiLGXC3O+TZSbADlwDpztYfELxrY3RT0ShvxcPgaZOTkmcyrl 6+tMroMjuUZx9tqIdHTlE6DTCqVq4/17+QqUYfouznzU9bR6kgbeZprQgFlE4js3Kjf3 5bOIx7BROHXAQv03rvahtia5D/TzdJEupoHLdhHOl3OUJX5kvvfdaOAKbbJ5H9g0W6wz WpW/RXiY0ejq6OV5OBIkgLRSR/fCkfdz1cWIjEnpo80kK/3UXBrgmnWxcoE63CCSl+a3 u04A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VWuzXDw3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:16 +0000 Message-Id: <20241211162004.2795499-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for PPC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-20-peter.maydell@linaro.org --- target/ppc/cpu_init.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f18908a643a..eb9d7b13701 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,14 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * NaN propagation for fused multiply-add: + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + * whereas QEMU labels the operands as (a * b) + c. + */ + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); /* * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d610f460026..173b9eadb57 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,12 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_PPC) - /* - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:17 +0000 Message-Id: <20241211162004.2795499-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for s390x, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-21-peter.maydell@linaro.org --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d5941b5b9df..e74055bad79 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); /* fall through */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 173b9eadb57..8a36280df1a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_S390X) - rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) From patchwork Wed Dec 11 16:19:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849178 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415442wry; Wed, 11 Dec 2024 08:24:24 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXiq28ONv4Ly0jiYq/1h5H8tLPDL7gnCNELBggISsUcW0SfxagQnnwkFqBh6z44YAeqtShT0g==@linaro.org X-Google-Smtp-Source: AGHT+IHCrpLenWQpJng9N9jD8YOTK2OWoDnl+XkBbnhXf6cZsoipVdejrsSGsLgoeFOMxscEzM2H X-Received: by 2002:a05:6102:c91:b0:4af:c3ed:b926 with SMTP id ada2fe7eead31-4b245f0ecbemr1074636137.23.1733934264298; Wed, 11 Dec 2024 08:24:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934264; cv=none; d=google.com; s=arc-20240605; b=g9eQOqEUuOrMDdS2lpm1uoIlttV9DKozPfVI20RZcIeb5fNOvFfEwPvqLay0s/+scr 44zWlrfZqmtGiKkFxg8BaESCwE8UO9V7BfiW4yaIbh6AKcVK1S0w20VbhI6q2Yq0wsmE +VhfP2hs0FZu5vQkRzVwxtk3OvQAqzm0P64rm4C/IOo4d68usz5oKN52RGIg8qNOYhuh cCgV0/jy3Mvhf+7br43mU5yHFpcU3Jcs8amSPNSkBBNHCETgsnrGlax6k2fJT226p4HB 8OJ6OoAAd/du2U4G4SmnfnG5CZDedKqesV6jPB6Yy1I10K7L+lsAOfCiCnaNWGD3TOa3 ZxjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=elThihR9o8htBA19kSW3jQQIVfaQiQSaHPvk+cMrk5s=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=k65wWhuo1DBIIw7GxWWhaSk4thAkxUG//DrXE693D5OeImmDeWl2AxlZCVDQdm96Gc WgjT4ce95L0tltsze+dxItGfIn9qq7PdNF8WE3LxzuFLmP2X0HWZlqIro8awO2TnoVno XCDAtR60TbESSRSbk8cXXH1Xzuoo+PcN0D5rIBZSmKODma0iv97kPHg1+bmW4sT9mhm6 jw5J73BLxUA7Wo6NgRJygYWMHFBsKLeLoTQROySa77hPHpR9hMAtsP2CcKAl0BumYY88 jewLUSATbl/TnqOcM7SiyDL6X6w+PnU2WSHpjIj+eQtJSVHs4u9KP5fM0v5so4yZ0gt4 eBKg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EvFITmLk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:18 +0000 Message-Id: <20241211162004.2795499-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-22-peter.maydell@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 61f2d3fbf23..0f2997a85e6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 8a36280df1a..c4d8d085a98 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_SPARC) - rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; From patchwork Wed Dec 11 16:19:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849296 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp429586wry; Wed, 11 Dec 2024 08:51:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUX6J+gBOiQBJPB+IN2vgjiE9REuata8YU8VzDfurKC+srAidLsfQx74TJtQSX0CT0o5ohKgQ==@linaro.org X-Google-Smtp-Source: AGHT+IFIsJJpOuohrH8FBERfcSV5wxajJAygLU81+WdtBgvbqpuHHtSFi/hvT3ASc6Vi3tcQf2ta X-Received: by 2002:ad4:5f8f:0:b0:6d8:916b:1caa with SMTP id 6a1803df08f44-6d934b201ebmr64679846d6.27.1733935861467; Wed, 11 Dec 2024 08:51:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733935861; cv=none; d=google.com; s=arc-20240605; b=WpiAQsnqZZRTb0XV6AMzmuFNReNQEU2kHYauTv3ugyIs35wNIO07xIUcFYK/QDNEKr YL5FT7Uu94cyUaHXx6VZvcR78Roe68JwaACiLqzIEolL+Il+69W5+KuUzNpXAXs7IOdA RWxMW+MdKx+upvwbE6SGYMSJn7AjfuzFD1WGZhASpA4h0Equx3IGP9Xj3Ul+tUvDWUXj /vgZsQcqkZ0tqmr67xiIC+VEqYp01RTXL6Dvw++b2eazmlK2PRMn27aRaWhB1EdAwJmz UKtHybiw96pXIAtOm5Dist9aqowW3XVc3SjELPdiXpOffhL9otV6LhShOpDNmcDEhC6s HYXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IY8zOoALtZnJGd9D02lgKKAFGzmZzVDZQ3xBBMlHM34=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Upsbn1cXShtesEraspEV3vb9c80Ip5v6Mo/RnEFRQJEjZRh6T0knQO8ROsy9yxwE48 H2JTHvHDZtMqzz/T4qlCuOECoIUheCBoE3Jd2NmfB//v9d6BsQMPJtRQxYk0or5j/4DC Gn8+Rses6m5SepdZhpEx+q5ZLdtI/hkSEax2fBY0SXYtsAG+uvLGZAte+GWipR9HYv96 4OWFwJFdW3oVMdfLOEUVAV5TJeitMLBE4sx8S704UXc36y4sxW8m9BBzSMFmjkud8ldG UED60jBrAmFdCfNO/KyJW7X6u4q/x8Hhww2oUN5yJ/spypZX6XCXS2vmiBqtY1ltEJN1 yGzg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zqwNghzm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/72] target/mips: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:19 +0000 Message-Id: <20241211162004.2795499-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-23-peter.maydell@linaro.org --- target/mips/fpu_helper.h | 4 ++++ target/mips/msa.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index be66f2f813a..8ca0ca7ea39 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -29,6 +29,7 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); FloatInfZeroNaNRule izn_rule; + Float3NaNPropRule nan3_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -44,6 +45,9 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index cc152db27f9..93a9a87d76d 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -66,6 +66,9 @@ void msa_reset(CPUMIPSState *env) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->active_tc.msa_fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, + &env->active_tc.msa_fp_status); + /* clear float_status exception flags */ set_float_exception_flags(0, &env->active_tc.msa_fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c4d8d085a98..28db409d22c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - rule = float_3nan_prop_s_abc; - } else { - rule = float_3nan_prop_s_cab; - } -#elif defined(TARGET_XTENSA) +#if defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; } else { From patchwork Wed Dec 11 16:19:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849177 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415314wry; Wed, 11 Dec 2024 08:24:11 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVzL6wYiIRvwcG4yBq6vRBiWYyaTZMshlRADNRjKd/46pp5Fta2BAmr+DFmzqcPQKr5gcG11w==@linaro.org X-Google-Smtp-Source: AGHT+IGoI7PcDBLIOV/h1Qop37a0fLqaVeIruo1zjYAx4IMzUpUQaWk/8aN5tUttYPlEFvMDCxC+ X-Received: by 2002:a05:6102:5489:b0:4af:a216:c0d0 with SMTP id ada2fe7eead31-4b247472ce2mr141638137.0.1733934251404; Wed, 11 Dec 2024 08:24:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934251; cv=none; d=google.com; s=arc-20240605; b=dPspvBb6sMGtFq1XdTIAZxdEbY/NvUM9oeFbO3Ne3epFP7ifonaqRRxQOUqQfJXiKn YVYxzdnar4m/mBnp8V+eyWGck/Zs1Q8dRquj5fULwNytrFb7cmTEvcd5Cc8+zX7gm8YV 0RYest6lbE5PydeIop5vU70pPFDRuowxTAe05Dmwa3TNELi4pR6CWzzfzwv9S5o77Mnt iYpXBxbs/HmvNaZYmnDbIkhU2+g0SwwiafpM9d9pUonxIEh+sDypo5Iaceo/o39okYRn eRjbvanJ6FWtDCepTemqlw98hWkbaMo+BClFFvP0/j9OHaqOi0OhSWgvz3QFbchTma6t isUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LqLnmo8ZeuKt9gJbN0OoofaNl977bhykVsCXiY8ZDEI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=OuWpEeoWvCMpZYHRtnmnorMWoSCHkuucevJcas5ehWvPi01G+agWjilk6QX+T1a5h5 z7UdXBi/a4p4/cLsmfRYTi4h+zNvCGiZUFFMBdxl/8xy8CPXS5aEAzlgjHHQ25gHf6u3 J96hBu+QQjHDQeXqrZ7/79u5aE5ZyZyBNuWSEc/kXpoAZAAwgA4bHSOpriDJrIYeCmyG ik7QmoyILRSadwMxGgDjSE3VTsj/rZ8YmoTRvj4l3mTyY+jNfL0YjWnlETLgbGpSwDnR sw2e01XWqudCmVyKyGT3gCnypNbZZ09BVhjb/ST8ddlCnjy/+dI/7TfJdgz644buOitj 0OBA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P+rdJQfc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:20 +0000 Message-Id: <20241211162004.2795499-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-24-peter.maydell@linaro.org --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 -------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index f2d212d05df..4b1b021d824 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -62,6 +62,8 @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, + &env->fp_status); } void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 28db409d22c..67428dab98a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,15 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_XTENSA) - if (status->use_first_nan) { - rule = float_3nan_prop_abc; - } else { - rule = float_3nan_prop_cba; - } -#else rule = float_3nan_prop_abc; -#endif } assert(rule != float_3nan_prop_none); From patchwork Wed Dec 11 16:19:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849183 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415754wry; Wed, 11 Dec 2024 08:24:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVfFzWS/vLefW9+keDeGZnEFUK4Kr/Ecoq/s203AI4vZPZk60EUI6SBOr3sqehsx89/XOxkIw==@linaro.org X-Google-Smtp-Source: AGHT+IFetpit0rVS2OPdlZrpLWFxcGJ3ckPHYNBlhn1NxkEPkWSqNin90LEzby+2t873R+4MRgvn X-Received: by 2002:a05:620a:7186:b0:7b6:5f2f:526b with SMTP id af79cd13be357-7b6eb442b1fmr522481685a.15.1733934298453; Wed, 11 Dec 2024 08:24:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934298; cv=none; d=google.com; s=arc-20240605; b=a0gCFK7Zf9fGdgFWjM2s2BlUpSroUtXsdon4HnO9KJNRipV7L4fzwEUXPVLmjhp4KU Yo1CkseVnPUrF19odo9Yd3jHpa58m6nc3s/7j3YFINEX2IBn3H+Vx8e9TNg2DCDzuI/k r9XDZFgAiiN2i2rthiDQSXla9EwOiuae3mxxTYs/YaBa/Ldg/OhinZrJImTRWx9Ppzqv xadQrK1m89zwA2zxxnsXyMebtDslpYdxqu3wKjs+36GQ2lsvUjjqoPkVOpUYMVVav/4w kv0pWfVonzahjz+iPS2/eLKm3mB4AtUxQj7tcYXtLwQYXbw3w7xU/RBzEdRcGxDWIuFk 9/TA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=klkjETkK46JGPy4cr1z4ranKH2QbJ9BDEJxJzYH0IXk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=RxrN1c0QO3EwVfncFgKxQmCI/sgc6fKKvAW9phqMzn3lLx23aM/xakHIKLMp+O0wLR bBA5WZqRIA2evL15GHwmgif/xVo6vtpDtlLhFVbY5DizyDrbQXWh+HIi98Vf2OKNyqrB l9uTM8Sp8kLyFq5QKD+ZtjGTEllmUqPPyC9kc2r9gqvm2/0uzNX2Ugfc5oIkeXYqQtI/ M0CobjtA1/Pcm1Ta5fhzMbRO/QprjzsRjBJ0xiDFykAZSdSOT2Px5Iapi1ZH+F2CGaDm f1bVPugT/UXRU5OjsN2MHnU7QFv8XLWBNrYiR6GB58YWCyot6oLT9uVb8Wfo2eLfLwpO dVoQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q4qWPh94; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/72] target/i386: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:21 +0000 Message-Id: <20241211162004.2795499-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for i386. We had no i386-specific behaviour in the old ifdef ladder, so we were using the default "prefer a then b then c" fallback; this is actually the correct per-the-spec handling for i386. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-25-peter.maydell@linaro.org --- target/i386/tcg/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 3295753e075..4303b3356aa 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -180,6 +180,7 @@ void cpu_init_fp_statuses(CPUX86State *env) * there are multiple input NaNs they are selected in the order a, b, c. */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) From patchwork Wed Dec 11 16:19:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849162 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414162wry; Wed, 11 Dec 2024 08:22:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWAR1jbACRsfavHsQmiBM7e1kLXCb3rF7yYGippIpC48h24MgKrvDKtTJKCiTAp5l83+tc/Gg==@linaro.org X-Google-Smtp-Source: AGHT+IGHGcYDAjz1ku1Mx/nUC14UIm1nZH7iaOa3dtlH4K3rv2D8yaVTYOZoteX+HZ8vcUS2X/1V X-Received: by 2002:a05:6214:c64:b0:6d1:9e72:596a with SMTP id 6a1803df08f44-6d934b7f2f5mr58020756d6.37.1733934125269; Wed, 11 Dec 2024 08:22:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934125; cv=none; d=google.com; s=arc-20240605; b=Szze9UrYRBF9IYmEosSG+NJng6OAlPk88TuWs/0Rpqb7yWBnPDaNNt4o6ZAqknjLlm Q5LBmxyC/BDwf3mNKKPHchFPjzVRHu5No9MB7PcJbrrcijQcsHzK1OWXMLRDaB62xcdO gMmDTj/62uoVGpYLOUKHlWzKNJoqXE6Ek3FHiVWCjCMlPFznJOW4Ue7sYUsVHopW7LU/ nj1yNCq7DRLszmKjkIqZeN7ZTIRyxykSYnTuIqEeHG7oc5PzsW3SH6XBheT9kit+osIQ AOJqO7sFbjb8JhEHPUU1DpSkrPKGOp63jUIUSms5BMkYgq2+rAogup9w9DMFuOAdL8n/ sP6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3myRINrKnQas6bU6fv1OR23zH4Adyf999B3PUNZnQ7Q=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=kF9z2yLGFQfh9PyAndegkEmIiNSKanXErF17yXDmSnFTnMkaUXQ/i2IOHoaEr+JLzF R23AOZhBWoA5VXfm+wuqjEEdT5n7ECA1G5KWFsyBTL6F60wLQmWgYUlSh/p4VXyfKHds XFEvyPYO5B3BvkMlkszjf2yyzXgPiMj+jB/xU4F1XqVG1xt6t/z2IwVueGWXOWaoK/3N /V9WjIxwe5+w/3IHErzP/vIEzfm8QXs4+4XmyupH20lvXfAo0YDi1OyjaReNlmznRY1A whnqcIvyFKLrNDjBQt/g/moK4nSeMqRh13JHj2H10z5ElFR202jsz3lhYpkq404STZLp vNzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gjuf9Ml6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:22 +0000 Message-Id: <20241211162004.2795499-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the Float3NaNPropRule explicitly for HPPA, and remove the ifdef from pickNaNMulAdd(). HPPA is the only target that was using the default branch of the ifdef ladder (other targets either do not use muladd or set default_nan_mode), so we can remove the ifdef fallback entirely now (allowing the "rule not set" case to fall into the default of the switch statement and assert). We add a TODO note that the HPPA rule is probably wrong; this is not a behavioural change for this refactoring. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-26-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 4 ---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 393cae33bf9..69c4ce37835 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,14 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * TODO: The HPPA architecture reference only documents its NaN + * propagation rule for 2-operand operations. Testing on real hardware + * might be necessary to confirm whether this order for muladd is correct. + * Not preferring the SNaN is almost certainly incorrect as it diverges + * from the documented rules for 2-operand operations. + */ + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 67428dab98a..5fbc953e71e 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -504,10 +504,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } - if (rule == float_3nan_prop_none) { - rule = float_3nan_prop_abc; - } - assert(rule != float_3nan_prop_none); if (have_snan && (rule & R_3NAN_SNAN_MASK)) { /* We have at least one SNaN input and should prefer it */ From patchwork Wed Dec 11 16:19:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849171 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414445wry; Wed, 11 Dec 2024 08:22:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUTCoiBnw1uq8vRCRQcAi+6u+tik2rIJrIf2BmQa3eJ0NQxYYXjBwRC7gT+UeL8adXu6xneRA==@linaro.org X-Google-Smtp-Source: AGHT+IEUj2vrAHr3gsGgzQRUtplDEC9y3uA+7bCDhvCd0T7+ngOFXP8gNVu2Xa0sswgoLNTsXQEZ X-Received: by 2002:a05:6102:292b:b0:4af:f576:b639 with SMTP id ada2fe7eead31-4b1ca388004mr2971472137.4.1733934157566; Wed, 11 Dec 2024 08:22:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934157; cv=none; d=google.com; s=arc-20240605; b=U6fFEVYQI9Gt7KR6p0BYX0w0q07XYyW0ZzgG3pHIKqKIcDRAPEBs88XXvR4frL8O3H 66AsAcxJOSabbC0DxkYaeeeoyFrLtmKTHdyA7lt0dDKjGA5jAktNPiwlh9NysDpA0O1F y0/vJo6lnzHstFozZWV2QKGkH//unEp0CCr2t4vMSXDxB67WvPkq9wj7Im7bPMxwnkt5 HUUbHWy9p1HWQtMJjJDXAhBMmg1sPMm61/A9QUgvRq8RZ49GRYDBbigmY5J4w4Wpe4/d k38HFXoop3SyZzBbbMJyWgdYIm9Gcp21JZcjCMsYRa99NtSWcbztY/PTZ5A/f0OpPM+e OmGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lRJiit52f5redlFxi2z3tbKksS9bryLnGPt7oPWvzf4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=DqzGHcT/KjNR65CgU70Ykx/2wuD7ELbFTmAfB17UOo42v1hykrLhR2ZrOAl5zWbcpP F7ZxlN+/YckVxAl+6IgZxfeeDC50NTVn7wUy+nrz2tYTZ6iu/85YFaH4z1cEVcCHHk0L j4OVLPBHv6pDk588xQHgGLz+pF33sy6yTzHFZoSr6GGjDPTlb5tHVzt9CPhF1stVJTKW hrDb1VH/OicWrCf8m0w4We1Oble6ICjeEdnhA32Rxahb/bH4oDm9pOD7IfbRovJ4q637 Ebq4N1OeGGwGtfBMTZ9J7mOwS8MUfEvhpub2GL/r9kGRD8jWhq1W3Tdp59S0qqdbOVGj rM7g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WpFfEk0r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/72] fpu: Remove use_first_nan field from float_status Date: Wed, 11 Dec 2024 16:19:23 +0000 Message-Id: <20241211162004.2795499-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The use_first_nan field in float_status was an xtensa-specific way to select at runtime from two different NaN propagation rules. Now that xtensa is using the target-agnostic NaN propagation rule selection that we've just added, we can remove use_first_nan, because there is no longer any code that reads it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-27-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 5 ----- include/fpu/softfloat-types.h | 1 - target/xtensa/fpu_helper.c | 1 - 3 files changed, 7 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index cf06b4e16bf..10a6763532c 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -113,11 +113,6 @@ static inline void set_snan_bit_is_one(bool val, float_status *status) status->snan_bit_is_one = val; } -static inline void set_use_first_nan(bool val, float_status *status) -{ - status->use_first_nan = val; -} - static inline void set_no_signaling_nans(bool val, float_status *status) { status->no_signaling_nans = val; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index d9f0797edaf..84ba4ed20e6 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -309,7 +309,6 @@ typedef struct float_status { * softfloat-specialize.inc.c) */ bool snan_bit_is_one; - bool use_first_nan; bool no_signaling_nans; /* should overflowed results subtract re_bias to its exponent? */ bool rebias_overflow; diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 4b1b021d824..53fc7cfd2af 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -59,7 +59,6 @@ static const struct { void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) { - set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, From patchwork Wed Dec 11 16:19:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849167 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414351wry; Wed, 11 Dec 2024 08:22:25 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXwSMs8w+fUekFpnyOO+yahyQngR494XKrqB9EwlboQRrcomnm9byQT4abS/TIrQxA4ebbuYg==@linaro.org X-Google-Smtp-Source: AGHT+IEY25faNbJiOpBB360LPwxSfcwE4vKfAAvnEltJjC84gStAVY0KcNZIebQSHVRMrBIibjsk X-Received: by 2002:a05:6102:1625:b0:4af:eccf:e3ca with SMTP id ada2fe7eead31-4b2477c2017mr8872137.10.1733934145628; Wed, 11 Dec 2024 08:22:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934145; cv=none; d=google.com; s=arc-20240605; b=SQ97OJYZddeOQk7sQp+SUlCTD4ddQF6FmRVX8tZdimKJq4MPtaQ5Lyw3GOgEOpDPGq L8vwTq7VbX28vs4UBHkUQM7epClIGuXLMmcJT29Sk0D9KKkNo304dGfpu86f5qkW+W+n oSl47PbpmHe1wqFoESGyfIxH5ClOT8uwFqfL6IXwBMRqiPGM3DL0ONEnRj7egp8qkQf+ jzU002pW5rxIgUihHB4K6l7lDEy5Yg0DZFg349tNDUTyhPOA7S/b1R3aS097NO5T2+bk 3MkxVj3qtGT2Ao/iOsrqrNxI4lSNB0Mc9I5YWUImlRpsfoS5rCS6UX3iu0Ghg0a8g5vC c6JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PQNG0n9NXp4YCePXcFiDn3lq3sTBy07a0OMkjgz62Dg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=DSBjnwmJipI4Cg/3fL2ILz/cknNBEUrtpRCXAtBT6qmzR6EajqLI7RzRjXRwjSprse yx7QKY/HA+Yuxhpz2hKJCwsHO+A5zvqoGzuZTTusDsLiptI8lrkXLUs8TvIwZKHs0QiL AwBSP2gPkgeNrHSaJmf0NFzMYBqfyPLzFB92Vc0KJ9syEKFcSi+zFs/UP+B5DAm5qJUH XNPpfGYdarkWqb5WwCg/XiuomwigpnE4dOr9x3xYifUtkWzC7zb6+7hkC27xSb6JFmjf BlrCDJPIoAQZsLDb0SsbzhTQ7hqsgyOFHudxATLUbXSef2O2bzqjNQQAEK79Z2+VPeYQ nkyg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RV4aXd6o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan() Date: Wed, 11 Dec 2024 16:19:24 +0000 Message-Id: <20241211162004.2795499-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) to get the NaN bit pattern to reset the FPU registers. This works because it happens that our implementation of floatx80_default_nan() doesn't actually look at the float_status pointer except for TARGET_MIPS. However, this isn't guaranteed, and to be able to remove the ifdef in floatx80_default_nan() we're going to need a real float_status here. Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status earlier, and thus can pass it to floatx80_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-28-peter.maydell@linaro.org --- target/m68k/cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558aa..13b76e22488 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) CPUState *cs = CPU(obj); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); CPUM68KState *env = cpu_env(cs); - floatx80 nan = floatx80_default_nan(NULL); + floatx80 nan; int i; if (mcc->parent_phases.hold) { @@ -89,10 +89,6 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) #else cpu_m68k_set_sr(env, SR_S | SR_I); #endif - for (i = 0; i < 8; i++) { - env->fregs[i].d = nan; - } - cpu_m68k_set_fpcr(env, 0); /* * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS @@ -109,6 +105,12 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + + nan = floatx80_default_nan(&env->fp_status); + for (i = 0; i < 8; i++) { + env->fregs[i].d = nan; + } + cpu_m68k_set_fpcr(env, 0); env->fpsr = 0; /* TODO: We should set PC from the interrupt vector. */ From patchwork Wed Dec 11 16:19:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849201 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416653wry; Wed, 11 Dec 2024 08:26:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVU1r5KuYU/uE5KJle4SGTv3CieYCWgFcV0QZTGXsGrc1Q606JSBnybJOPTYblh01xtW0V0rg==@linaro.org X-Google-Smtp-Source: AGHT+IFZ5K670sY9VV8e46TmhSTkY0X+oOUXMfLK0HqwHnFCpZRLE/+o+JXGIgMZx6/Jp77M59ZR X-Received: by 2002:a05:620a:2609:b0:7b6:d7a6:78e9 with SMTP id af79cd13be357-7b6f1c3b2ecmr43414785a.40.1733934397140; Wed, 11 Dec 2024 08:26:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934397; cv=none; d=google.com; s=arc-20240605; b=bluP9wzOja54bY3tH3y+e0i5jxgW+V5u12q/8ANnfdWkedHA13+RSzv/s9TMeiIb4m 1jj7bD2EGphYDP/FhJC/CST9imvxtjNDKlwIY17LEt4YVWeguyn4JFTlxjPW2bTJZQr+ oLHDdcO26PIxPV/sVac0SDAOVQFwlMEpdyyGPx4vocKHr+2JzE1dHj7HjgH7YDBgXP/F TTwxhKj2a4PwvaVqVRZ9yYJfjM86CfsJ9rV1lXBSQRrp8pKKzSl7hRyuXnQR21QEHrjG GMq2jdk4Xcr3veeeMixixgklPi5sqd3HU90aXtTZPulMMZvphXcvQOTPEsWlqR//hAX1 f/Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gHqtgcXwaXzVvVdsrCBhcuw/gjNtZbZ0W54PPbBKVlI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=LxsfdkfG8ZC48pt3e1VMSxS+DyobhclKd4FaS65yrHfH+Zwzd64sA2uj/d3T2CySYy J8TFD2orf9aYbPHQvKsme/OeWRxbEFOZOdmRdzE6t4677cj05NiVMLo8H3mhDnjnkcsl iMY9pxflDxdNKPGsCbH8DlTvTiSdLdxUBLGZJ+rH+qMo/xln5zO6Dq5BKqVELJzGCB2s vvg0KTSADWlpo5fgbJl77TvchkuJN8xDf2s09fxJWOXq4obk+bC72OkGqzREcBlScOFF f9wfASDzeluYxJq9Skaq75S8koqNbUdykkZU02PrAGRnDwvagyAr0K4caNgHGLgqgNfK JBVA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wR9HS04S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan Date: Wed, 11 Dec 2024 16:19:25 +0000 Message-Id: <20241211162004.2795499-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We create our 128-bit default NaN by calling parts64_default_nan() and then adjusting the result. We can do the same trick for creating the floatx80 default NaN, which lets us drop a target ifdef. floatx80 is used only by: i386 m68k arm nwfpe old floating-point emulation emulation support (which is essentially dead, especially the parts involving floatx80) PPC (only in the xsrqpxp instruction, which just rounds an input value by converting to floatx80 and back, so will never generate the default NaN) The floatx80 default NaN as currently implemented is: m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 These are the same as the parts64_default_nan for these architectures. This is technically a possible behaviour change for arm linux-user nwfpe emulation emulation, because the default NaN will now have the sign bit clear. But we were already generating a different floatx80 default NaN from the real kernel emulation we are supposedly following, which appears to use an all-bits-1 value: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 This won't affect the only "real" use of the nwfpe emulation, which is ancient binaries that used it as part of the old floating point calling convention; that only uses loads and stores of 32 and 64 bit floats, not any of the floatx80 behaviour the original hardware had. We also get the nwfpe float64 default NaN value wrong: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 so if we ever cared about this obscure corner the right fix would be to correct that so nwfpe used its own default-NaN setting rather than the Arm VFP one. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-29-peter.maydell@linaro.org --- fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5fbc953e71e..9f913ce20ab 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -227,17 +227,17 @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) floatx80 floatx80_default_nan(float_status *status) { floatx80 r; + /* + * Extrapolate from the choices made by parts64_default_nan to fill + * in the floatx80 format. We assume that floatx80's explicit + * integer bit is always set (this is true for i386 and m68k, + * which are the only real users of this format). + */ + FloatParts64 p64; + parts64_default_nan(&p64, status); - /* None of the targets that have snan_bit_is_one use floatx80. */ - assert(!snan_bit_is_one(status)); -#if defined(TARGET_M68K) - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); - r.high = 0x7FFF; -#else - /* X86 */ - r.low = UINT64_C(0xC000000000000000); - r.high = 0xFFFF; -#endif + r.high = 0x7FFF | (p64.sign << 15); + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; return r; } From patchwork Wed Dec 11 16:19:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849175 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415292wry; Wed, 11 Dec 2024 08:24:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVS6cRDQca8u3Hg7iAj5mMwzHsTTYHJcU2+nsJ2Lo5NwP3J7r2epHLs/imSa4+B0pfw9oHfaQ==@linaro.org X-Google-Smtp-Source: AGHT+IEwnYLy3Wl8jgmS/lfp0cY9K6z+Mdeg5RbUZicDmdar9vM9FAGmV5y/KiAwxwbm+f8IHURW X-Received: by 2002:ac8:7e87:0:b0:467:1e96:645f with SMTP id d75a77b69052e-46795263d01mr5135841cf.6.1733934249536; Wed, 11 Dec 2024 08:24:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934249; cv=none; d=google.com; s=arc-20240605; b=YYod/+js2QzLmSrso5BEQhXhevCfvPv/j7acNYC1dHq7UZz1OSiuTqNhAOObmUgYbH H+kfJiYpCFDuL2FuI+OL6FGCxXgVKO9SAa/7nx4Wk6Xpb0P8/dNH3Ku1UTDPE5IcfnJs 93eEJvFfFQ9aInxb0GgYqj+7M0XWZYqTrPGUKe8FGe1xFpt/fpnYSJdsD0ldCUmDPlzy mFitjg250gYSQnfCT0HJkAwd07Q1rBG3t5jP32bNL1A1tc98WfHcAW+0qISef5+Sbkd8 uFJ+iiAisWFsWEjWn9v1WoNT8wt89+hQq2BXdiXZduLheVo5ZBA6s7ewL+Iz5TqkqKp3 HBBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jSuOu2n5x/+mHXTv9G32cuk510bUbTH6keT/6j4dWJk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=YtjKTmdevoiG1z7nHFeopUntDaqPBYeBr/nKDt69QzygOJiU7+M/iPHkHONF2Rgd7u 715ai+e3KJB1MpNqTuP+kZEIEuqNFPacHJA+U6ZtKQiHI/gOQNZQYuPva2XNrX1SSskR /1eq3n/eALBSxLis10hlkXxslQFNpfrJLesOXQt3UTcMsfNjTdURcyJDvOflB2l3gXMn tDm9tusl7a41A+CR0lKfqA6vbk0T7eQ0ThcrRkMgEK4A2YMwz31czQhzg469LsDOY6t2 /SJf7EhW37hZuBt9hy13EEmBmQIQ6+IhxBjIxIe90aaiQoK2iv7BPoQc7KCDuIbrpKup zMjA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VP59xEBm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers Date: Wed, 11 Dec 2024 16:19:26 +0000 Message-Id: <20241211162004.2795499-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass a zero-initialized float_status struct to float32_is_quiet_nan() and float64_is_quiet_nan(), with the cryptic comment "for snan_bit_is_one". This pattern appears to have been copied from target/riscv, where it is used because the functions there do not have ready access to the CPU state struct. The comment presumably refers to the fact that the main reason the is_quiet_nan() functions want the float_state is because they want to know about the snan_bit_is_one config. In the loongarch helpers, though, we have the CPU state struct to hand. Use the usual env->fp_status here. This avoids our needing to track that we need to update the initializer of the local float_status structs when the core softfloat code adds new options for targets to configure their behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-30-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 37a48599366..aea5e0fe5e6 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -359,8 +359,7 @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) } else if (float32_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float32_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } @@ -378,8 +377,7 @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) } else if (float64_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float64_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } From patchwork Wed Dec 11 16:19:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849188 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415871wry; Wed, 11 Dec 2024 08:25:15 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUnE2+xU68FxaJN8VbPxo5qeCcpqadeXi0yiKApWWNSRraTqM15PxPOiZVFjLUjD9c7t4iSVg==@linaro.org X-Google-Smtp-Source: AGHT+IFN+wCaP0ZdwxtTWiw3lKu/wau/Xns7o6F7asi6E2g93MbE13aR9KdXN3pRd3PlhZtshsC0 X-Received: by 2002:a05:6214:d48:b0:6d8:9e16:d07e with SMTP id 6a1803df08f44-6dae29bc34cmr4952236d6.4.1733934315326; Wed, 11 Dec 2024 08:25:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934315; cv=none; d=google.com; s=arc-20240605; b=iXbbqI6ckcSgKyQXDLNWHlQitOLBBsTQpbMJmiEeZvc70MRANyKzAja5ITzJMlkBNE kKSxIoz78VJFSKU1/8oFW3ErAvAq8gOys3khQyQPZr+cZPtb3O2AiUNIOVcTUnevzqd8 f8znEoqlJn+zr0E2bi50txQ+DI6nhwtAZkd0qm4x7q+mvcMcWXFAUbEYH+T7O2mBLtsa tXICFTHZRL02EuW9E5NptMWkno8VgbhJ62hhMRgKg3BrYpeUv7dVlcVYCJLp13ESf79F YHfKBt208udgD2r4JMKU/NEPPBlBfIzpZKqe7h5ReQOcL2iFwJbA7CK3PtX3gfLUretv WPQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GJ2MxfIn+bPI815lGa0YYGJVtmHJ6iQzs9ubSygVReI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UlnoiNHIU54y78FaGNbCuD8soioS81YqU75iTX7Zy2ohfwIrJ8nbFilMp43JO2QiFJ 3Ve3KcTr54027osS286cL/vYj56B5tlj0gpZPnvh3nQGXhuFP8z3UGdpCqVCk5M70wL4 203swF8SE5lDl4BWIkodvgWFpRtpEb667eumDDirSSw2i5NmsFpH1KgAI7A3eXcZwQW2 xrTXGb4rafmIQXwzIf48wAX7c2cqza9BOQWGDqM+r8MVw5c8P/KMtbWKPARHFvoyG9ED PWOQXleZWe9/PWLP2B1mRxoctQIpSdzeivcngYAmAxAB1cUzxzQGLYcFE7u2xHAImZcZ ymEg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CKD0pyTo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status Date: Wed, 11 Dec 2024 16:19:27 +0000 Message-Id: <20241211162004.2795499-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the frem helper, we have a local float_status because we want to execute the floatx80_div() with a custom rounding mode. Instead of zero-initializing the local float_status and then having to set it up with the m68k standard behaviour (including the NaN propagation rule and copying the rounding precision from env->fp_status), initialize it as a complete copy of env->fp_status. This will avoid our having to add new code in this function for every new config knob we add to fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-31-peter.maydell@linaro.org --- target/m68k/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index a605162b71f..e3f4a188501 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -615,15 +615,13 @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); if (!floatx80_is_any_nan(fp_rem)) { - float_status fp_status = { }; + /* Use local temporary fp_status to set different rounding mode */ + float_status fp_status = env->fp_status; uint32_t quotient; int sign; /* Calculate quotient directly using round to nearest mode */ - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); set_float_rounding_mode(float_round_nearest_even, &fp_status); - set_floatx80_rounding_precision( - get_floatx80_rounding_precision(&env->fp_status), &fp_status); fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); sign = extractFloatx80Sign(fp_quot.d); From patchwork Wed Dec 11 16:19:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849195 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416276wry; Wed, 11 Dec 2024 08:25:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVTkeJC3F74VAcgHRkn5HrG5wjcv85YQCz/cJp7JY2qdAHU8/IRjR1vm29tqA8SDmOcT7RAfQ==@linaro.org X-Google-Smtp-Source: AGHT+IHUG7wZ370kR3uwcNG4Ul49vToB61uozVznanXLz41mWAbiaI//c3PtwqUOirqwdUIEauPq X-Received: by 2002:ac8:7f43:0:b0:461:646c:b8fc with SMTP id d75a77b69052e-467953b6b88mr6253071cf.23.1733934355013; Wed, 11 Dec 2024 08:25:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934354; cv=none; d=google.com; s=arc-20240605; b=Hft/U9UuVpBQ6kdEzu9Y8LLoBC3EPzoD88Y0wHLu1gt7eGGxB+25OuLLbnsz+ZHpGi WWDiD9Ubtct0fvVXe5f3rJIGXurb6dyaNWmaeyYwCgdaBGK4mVLPKNGBBY2ac8EcWWn4 2p6iwc3RH29Or5FYR8j8H90iaMxWc1YGIo3pk/c0+ZqL4GRvg3KctVy+D9pZUzHvr/4/ jBoZ5Bl8uPK2q63N+B4m7PRFJnEjyagAbOMcBXjCEGGsW5q2axqorx6jT4vedXUoIXk1 zSesuN3dj6xLNu5h9+TqzAh8pE/vv90iHKsgZa+9YNtFCfgi9Ze+kwcwu9OVHkwQFcHr UHFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+U+8i8q/4gXE3A3yYLQmyNCA5wUq2DI1uSwKXqmKO3k=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=afEQGm/BPwlz7sfvDeqoRllesAlFqWHyWglHraN6ScexBEwjpJtA/F0WwUD5Efbtdg cdYkUuhBPqYkmqG3f3InoDo88rpNhh2C32auLVUo0j6A5fcxtjnnvgZLwr/1L8p4UD7u 01BbJ2gBwQAKUXpBl0hKQGAwk5zpzp9EdfcU2dkwQraUlpX/+Ry4qBhLSmlDFA5MIF6K iE6yW4mM8biQQ99x8NYCeJ9qLw2GhsEQWPJJ212N5C0tLbJnZut7z5Mk9OegOCxW1cB6 97LjR5kZdnQW0ICQ+EDCYQE3cQFvfiTbMXqw4GQk86oSFzr8aUuZTWz8rbCgQF+yeAAj 6E5Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hJePzYhz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg Date: Wed, 11 Dec 2024 16:19:28 +0000 Message-Id: <20241211162004.2795499-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion from float64 to floatx80 using a scratch float_status, because we don't want the conversion to affect the CPU's floating point exception status. Currently we use a zero-initialized float_status. This will get steadily more awkward as we add config knobs to float_status that the target must initialize. Avoid having to add any of that configuration here by instead initializing our local float_status from the env->fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-32-peter.maydell@linaro.org --- target/m68k/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bfc6ae97c0..beefeb7069c 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -36,7 +36,8 @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); } switch (n) { @@ -56,7 +57,8 @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); return 8; } From patchwork Wed Dec 11 16:19:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849173 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414938wry; Wed, 11 Dec 2024 08:23:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWjb9zBaEAfB8MhX39eiM62d6gYmyRnEIr36Rp/W/mX2aWQcJEAGtkAYDykVLQVbq77h4h6IA==@linaro.org X-Google-Smtp-Source: AGHT+IFRgyepjIx5Ca5ACgYBgcwxpk4+3nNNfVCS5nuppViCgF2rvMzp9U5f85IoI8bZ+QZulYmy X-Received: by 2002:a05:6102:cc6:b0:4af:de39:216a with SMTP id ada2fe7eead31-4b247772541mr33570137.6.1733934212529; Wed, 11 Dec 2024 08:23:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934212; cv=none; d=google.com; s=arc-20240605; b=Fe5hK5Sa1uGXZ8sluOUmxXHc5WG1AKzSGsmw4ss3pLVfbTUALpobjRhsxTlkkfupxc WlEBJmBdpV7S286Sks+Jj4z14IG/O4k6XMFpLtXb7wu3LnyI81Ub5HoXu/DubQrbQ1n5 mYILceJVq0vbpRYauDAwRAM89i8buiJBU8laRh7tGrQC7Oy86SjZD6OZT6FrFv67kSJJ sZ1Rqrd+X5/uRHGmzwTjTg/okauO/3ndEb4Z7jaa46H6r9vlJz+nNZ3OLSFUtHQOhVr3 9agKfZzrYYQnEjKWQKe8MH5u0lPk17CVur4+2x3spK0JHcSp8rDdCPrLjW21+Z306atF dt8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8QtRpOUDdXPykNSh2kSGznv4CfLLLfE60kE3MXT1yOA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Gmb30syeImCqsLs7mA++6ALrhS0x825IERlOnnfoD6YEpv+BlhXrLLG6ddAtHtoQ0H MOSdOkQwOE5DLF9g2epHjNtTV6LQVYCQTJSHtIUX7n5vwYla7uPWq0ZnSj+ceY2RtRkU VtmM4Xt6er2qptBlmHpXFY1bbxtXWtJcjme5BO99Jc3GtRTX5uVnxMCuD4TLmBvkoyB5 9uvTvkWF4pPntmRrle+MaLPI968h5OdsAVt4hCTOwOtFt4SK1vjeEleac77jCi/H8UIn SxOfKRBXWntbyVfON9bUvIysyINB2u4DkWBaPIb19MxiHOK/Aunr5QmYR+QTV5Jx3PDQ 4w2g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M9yWJlEw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status Date: Wed, 11 Dec 2024 16:19:29 +0000 Message-Id: <20241211162004.2795499-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env->fp_status. This avoids the need to explicitly initialize settings like the NaN propagation rule or others we might add to softfloat in future. To do this we need to pass the CPU env pointer in to the helper. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-33-peter.maydell@linaro.org --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 134e519a377..1ae3f0c467d 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -51,8 +51,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) DEF_HELPER_2(raise_exception, noreturn, env, int) DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 6f9ccc008a0..236d27b19c1 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -490,13 +490,13 @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) return finish_fcmp(env, r, GETPC()); } -uint32_t helper_flcmps(float32 src1, float32 src2) +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) { /* * FLCMP never raises an exception nor modifies any FSR fields. * Perform the comparison with a dummy fp environment. */ - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); @@ -518,9 +518,9 @@ uint32_t helper_flcmps(float32 src1, float32 src2) g_assert_not_reached(); } -uint32_t helper_flcmpd(float64 src1, float64 src2) +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) { - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdd0a95c03d..322319a1288 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5584,7 +5584,7 @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) src1 = gen_load_fpr_F(dc, a->rs1); src2 = gen_load_fpr_F(dc, a->rs2); - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); return advance_pc(dc); } @@ -5601,7 +5601,7 @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) src1 = gen_load_fpr_D(dc, a->rs1); src2 = gen_load_fpr_D(dc, a->rs2); - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); return advance_pc(dc); } From patchwork Wed Dec 11 16:19:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849179 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415526wry; Wed, 11 Dec 2024 08:24:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX65jCn6qBuw87OEizq53aYPoiSbXcnkABsYafsnWsdjXwl3falKuDf9hAyenvhYmyEyzVFnw==@linaro.org X-Google-Smtp-Source: AGHT+IGDd5guy1UdkWYreJR3QbYG6cjfOmgXm8RBWmRQiQzDwkQntIa60MlsnB+y7UJLk/4AyVr8 X-Received: by 2002:a05:6122:1815:b0:518:859e:87c0 with SMTP id 71dfb90a1353d-518b44310c7mr688904e0c.9.1733934272054; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions Date: Wed, 11 Dec 2024 16:19:30 +0000 Message-Id: <20241211162004.2795499-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the helper_compute_fprf functions, we pass a dummy float_status in to the is_signaling_nan() function. This is unnecessary, because we have convenient access to the CPU env pointer here and that is already set up with the correct values for the snan_bit_is_one and no_signaling_nans config settings. is_signaling_nan() doesn't ever update the fp_status with any exception flags, so there is no reason not to use env->fp_status here. Use env->fp_status instead of the dummy fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-34-peter.maydell@linaro.org --- target/ppc/fpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 230466a87f3..d93cfed17b4 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -155,8 +155,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ } else if (tp##_is_infinity(arg)) { \ fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ } else { \ - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ - if (tp##_is_signaling_nan(arg, &dummy)) { \ + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ fprf = 0x00 << FPSCR_FPRF; \ } else { \ fprf = 0x11 << FPSCR_FPRF; \ From patchwork Wed Dec 11 16:19:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849197 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416329wry; Wed, 11 Dec 2024 08:26:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWHBM8p4TWDjRr/HQTa+PWhgaMc101S3yuDXJY96As0B6JYnpoYJ3ZdwEL1wyRxIafl89HbHQ==@linaro.org X-Google-Smtp-Source: AGHT+IERLgzkgCZlcaXBW34jz2L6btkCIQeHRf+T/AI49PKUilser6k2fgqGqxFPyXGNGR2DfaYP X-Received: by 2002:a05:6214:2427:b0:6d8:9a85:5b3d with SMTP id 6a1803df08f44-6d9348c9a3bmr57488696d6.7.1733934360254; Wed, 11 Dec 2024 08:26:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934360; cv=none; d=google.com; s=arc-20240605; b=YUP9a0IJ9X5MNUAjdHMHlKHjzT19TTtaW1XsI731R8IaedN66InYW91vcgov3usHrp 69g/58iwVqC6AdwKR0O2sdPNu7aYyQPXp2ulAQcxZU9JCpbN970nvSdvO5ISTM/nP4MP i5WgzMZ4bZ0BFaQMw48sWtTjP25VJSoMgR3xHCvNl5Dn5CTa7gJz6x4cyBXxHazoBkHY qgbV8Opph9b1fYl9r/GBfPDPWiQYYomnc6svtQ2iST7mHLJcYPr33BdowcNKif1wQin5 2BougRq6Sxc4SYO7xmvlr6lczEJLMRserhbO36VQjKcggA4EMgZr56UHn3Z6etth2mlp ks9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0hVwJ7PhWgaa1nanKp9sPo09AWgYuiJDE+Q3tkgukF8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=aRlkWrMbPl7Q4qUZnaucRyuT7oBuAfjoBKvc+/ajmcGxoIprL6mrtoNI6LyOqRk0Ob o1qS73n6nJMuHfPnSnJ3g23cTrf9+pooaqNH145NKaxgLjSatxlrbm+48CdxvEx1y9v3 YGkzecKrRf08E0NKSy0ztPtEjLS0gZ8m24ma/yLb8XNBSA6nPb3WNnuwOXLRejcnM/uu AQiJNbC1ESckg2No1v38ZCwZPgyJYqtwk1Z44DYGDJNOGNjWqYpxKrVAqByuVNEcZ0lt 1WgKtd+rvQV5lrslWmg4bLibimlFzUsfHF1YB8mUKKG1hys8NnBNyyi2Kh4mPCffH4lI h3Og==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jTM8UaFk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/72] target/arm: Copy entire float_status in is_ebf Date: Wed, 11 Dec 2024 16:19:31 +0000 Message-Id: <20241211162004.2795499-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Now that float_status has a bunch of fp parameters, it is easier to copy an existing structure than create one from scratch. Begin by copying the structure that corresponds to the FPSR and make only the adjustments required for BFloat16 semantics. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/vec_helper.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index e825d501a22..ad6f26545ac 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2813,25 +2813,19 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) * no effect on AArch32 instructions. */ bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; - *statusp = (float_status){ - .tininess_before_rounding = float_tininess_before_rounding, - .float_rounding_mode = float_round_to_odd_inf, - .flush_to_zero = true, - .flush_inputs_to_zero = true, - .default_nan_mode = true, - }; + + *statusp = env->vfp.fp_status; + set_default_nan_mode(true, statusp); if (ebf) { - float_status *fpst = &env->vfp.fp_status; - set_flush_to_zero(get_flush_to_zero(fpst), statusp); - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); - /* EBF=1 needs to do a step with round-to-odd semantics */ *oddstatusp = *statusp; set_float_rounding_mode(float_round_to_odd, oddstatusp); + } else { + set_flush_to_zero(true, statusp); + set_flush_inputs_to_zero(true, statusp); + set_float_rounding_mode(float_round_to_odd_inf, statusp); } - return ebf; } From patchwork Wed Dec 11 16:19:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849158 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp413738wry; Wed, 11 Dec 2024 08:21:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUDUNbZB9SJbWoSGqRNkXNICGjEL28Hyk2Wv42nN31aPvsmpLNhBqZ114P0PzeSTq9T5DtTUg==@linaro.org X-Google-Smtp-Source: AGHT+IHM6UdI0S5Mbw4NdWR8MB/rHkizUOQgqAujB9nUban+EyWSarkit8zf7rHWq6o3EtWoKRbK X-Received: by 2002:a05:622a:8c16:b0:467:882d:e7cb with SMTP id d75a77b69052e-46789389573mr62973761cf.54.1733934080297; Wed, 11 Dec 2024 08:21:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934080; cv=none; d=google.com; s=arc-20240605; b=AUqiRod/5iYpH8jIkIn3njyPRXaU38LVllwaEC0ugEXquRWnslyHszo5ze8TuidH8p UiNr9zE0G4eO58gE9V0DYGysqt9il2rurKBMBeVH40EQiS68APE9JFKO2/nVEBsSqWFx eCRBSU8ifo04YuJbU2YnsrLVWbyHGPrBMrr0qXiw9/H5d1lVYxubfhbOuI5+RwsKRjgv ljN8zjsLzXE1sZXBh+TUhoHTXvhj7SioKRwLZ6CxIcbktonspoFdqU433MozlBE9m43V MlerS++jrDptFvLca+iFt5brlZ7sT2xdlnz4fm+PxixdXdiaEHy7GpcQlalhfgwqKhWs MnLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5/6kEX1gNzfQ+l4QKWLxGw2T4UU2uunALU33y3cz//o=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FKgvgnYMesvXmSsDAoe2D+CZTMUgTWuYFy6mnBRt50WOR4MR1/CXEq0F+ORu3dk9fF vX8HBMo3i+jsRn0/AR2fj0lBaI1jI4KoYl0Dfs3Sl2hgOXCW88WDlZO3TWpP+hvT07yw CIXj+YtMsBF7UCQKPg3LbCjTWVVB0Jb6hdPXT8kknYG7CepFz+hrmy6PVFpwNXJ9bhma v0UeiJVA4n2NpHQh5m3JDBs/9ZsEVKiKeuORnrQmObIjdqd58s6TKINEpM56k23iIg1t YuZo8KxaWgO91youdU3kSG39YFHpW7BYj6MbpCCVrEZ6Xm0q7ZMxBBpdt6UibDTQWv8a lubQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CrX+O6rw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/72] fpu: Allow runtime choice of default NaN value Date: Wed, 11 Dec 2024 16:19:32 +0000 Message-Id: <20241211162004.2795499-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit is different) Add a field to float_status to specify the default NaN value; fall back to the old ifdef behaviour if these are not set. The default NaN value is specified by setting a uint8_t to a pattern corresponding to the sign and upper fraction parts of the NaN; the lower bits of the fraction are set from bit 0 of the pattern. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-35-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 11 +++++++ include/fpu/softfloat-types.h | 10 ++++++ fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- 3 files changed, 54 insertions(+), 22 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 10a6763532c..dceee23c823 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -93,6 +93,12 @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, status->float_infzeronan_rule = rule; } +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, + float_status *status) +{ + status->default_nan_pattern = dnan_pattern; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -154,6 +160,11 @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status return status->float_infzeronan_rule; } +static inline uint8_t get_float_default_nan_pattern(float_status *status) +{ + return status->default_nan_pattern; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 84ba4ed20e6..79ca44dcc30 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -303,6 +303,16 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal flag? */ bool flush_inputs_to_zero; bool default_nan_mode; + /* + * The pattern to use for the default NaN. Here the high bit specifies + * the default NaN's sign bit, and bits 6..0 specify the high bits of the + * fractional part. The low bits of the fractional part are copies of bit 0. + * The exponent of the default NaN is (as for any NaN) always all 1s. + * Note that a value of 0 here is not a valid NaN. The target must set + * this to the correct non-zero value, or we will assert when trying to + * create a default NaN. + */ + uint8_t default_nan_pattern; /* * The flags below are not used on all specializations and may * constant fold away (see snan_bit_is_one()/no_signalling_nans() in diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9f913ce20ab..b1ec534983c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -133,35 +133,46 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) { bool sign = 0; uint64_t frac; + uint8_t dnan_pattern = status->default_nan_pattern; + if (dnan_pattern == 0) { #if defined(TARGET_SPARC) || defined(TARGET_M68K) - /* !snan_bit_is_one, set all bits */ - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + /* Sign bit clear, all frac bits set */ + dnan_pattern = 0b01111111; +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ || defined(TARGET_MICROBLAZE) - /* !snan_bit_is_one, set sign and msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign = 1; + /* Sign bit set, most significant frac bit set */ + dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) - /* snan_bit_is_one, set msb-1. */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); + /* Sign bit clear, msb-1 frac bit set */ + dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) - sign = 1; - frac = ~0ULL; + /* Sign bit set, all frac bits set. */ + dnan_pattern = 0b11111111; #else - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* set all bits other than msb */ - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; - } else { - /* set msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - } + /* + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. Our other supported targets + * do not have floating-point. + */ + if (snan_bit_is_one(status)) { + /* sign bit clear, set all frac bits other than msb */ + dnan_pattern = 0b00111111; + } else { + /* sign bit clear, set frac msb */ + dnan_pattern = 0b01000000; + } #endif + } + assert(dnan_pattern != 0); + + sign = dnan_pattern >> 7; + /* + * Place default_nan_pattern [6:0] into bits [62:56], + * and replecate bit [0] down into [55:0] + */ + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); *p = (FloatParts64) { .cls = float_class_qnan, From patchwork Wed Dec 11 16:19:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849159 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp413847wry; Wed, 11 Dec 2024 08:21:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXIAbCjebPvqZRv7pSLyOt+DWG4txWLuKozTSufP38r+Y0IcgUk08jruSIbx3wEG6iR6Nmdww==@linaro.org X-Google-Smtp-Source: AGHT+IGa1QqnvGoeYjVaXoVZFhtBv8HQtHPpmuFDNNzQgVthMtse2mRhC2owawoYKWItBLUj6VlW X-Received: by 2002:ad4:5eca:0:b0:6d8:8256:41d7 with SMTP id 6a1803df08f44-6d934bc4798mr60330776d6.33.1733934092829; Wed, 11 Dec 2024 08:21:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934092; cv=none; d=google.com; s=arc-20240605; b=e3M5J5JOPHwMLQx7qkYwmTvgjTw1YllnAgJw0JydxzNag4mCjDdqScGHN0CJhouWq8 PnzzflibePD9opP/9EeghTcdEQWhjSG7AU/mAh3Rohcn/RbzCrmW/A5EwfgZ4t69ixvF tBGEzlxSF94SIFo2lvXThjTA/Sz1Q1Td0CokCycVIX4lIK4U7ryG1e6nW8fGIxtbYlbx sLzZVPhdCC2wnkrxOaRUPr60pBz3XSULeJE/q/fBGcB4Vj4E0S7+WmmCOqPHjR/YLg2s DXExrN6zxnMAUxGQ5Uyn3yj/rik3FFsCFcQtx3CAxAV9O33yKPMu1spTUw5UMmHFU1MP oc3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=t++4ywN2N/TpqmWSD8grbRREKM5vsqH/rZ/w1M5vhhs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=CdxiMa81ZKrPGd0wk3VuJVadmqwuwtl5S3UkM75Cruekw1e5glolGAwmDxgSDIhME+ ZlwJRYD9Q1HKXXqTOqR2c4322Ca3TV5c27Q8w5PaEmgRRQAqJZAQFfsE3XgverLHnE+d qhlixw0OgZciN+RYDF39fO1tDva5NGVJl39kxcvXpH9s5PHV0qwdZZliilsnEmffYt4Q jHJMb7xJTc11qaF4oZIS9N8RlJcecwco8nJFWDzzsdHGrVck7ig3SUCrrKm/kaCgbYSl hhdWHLKd7P3KYB4R4mb9TN02eQTlmGFuA44EscWDN5DFGEVzuLzWjMPUNW9WgwSPYROi piIg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="XG/uyIZL"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/72] tests/fp: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:33 +0000 Message-Id: <20241211162004.2795499-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for the tests/fp code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-36-peter.maydell@linaro.org --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 1 + 3 files changed, 3 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 39d80c9038f..eacb39b99cb 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -495,6 +495,7 @@ static void run_bench(void) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); + set_float_default_nan_pattern(0b01000000, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c index de702c4c80d..79f619cdea9 100644 --- a/tests/fp/fp-test-log2.c +++ b/tests/fp/fp-test-log2.c @@ -71,6 +71,7 @@ int main(int ac, char **av) int i; set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_default_nan_pattern(0b01000000, &qsf); set_float_rounding_mode(float_round_nearest_even, &qsf); test.d = 0.0; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index f290d523ab1..c619e5dbf72 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -941,6 +941,7 @@ void run_test(void) */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); + set_float_default_nan_pattern(0b01000000, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Wed Dec 11 16:19:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849185 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415770wry; Wed, 11 Dec 2024 08:25:02 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXBFOGNCIjwp67warSYNv5OMjksHcq6JhspTW54V47WIs/rlqZiSY/RNGNa2bLfBjwZGHHm+Q==@linaro.org X-Google-Smtp-Source: AGHT+IFNnfP7WROdG1LEr1CRaErjHa/un7Kys8l64Aa6l5zSx67JsYmGIVro1FX9B7F3Kaf7m9bh X-Received: by 2002:a05:620a:6007:b0:7b6:d23a:be39 with SMTP id af79cd13be357-7b6eb525a04mr691034185a.44.1733934302733; Wed, 11 Dec 2024 08:25:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934302; cv=none; d=google.com; s=arc-20240605; b=FBmZrefU/FExOMjp5/QYZZ4eZcrnGbQcWApQTGO4f7VlRrulYm49J0suDVcwEV4yRX /thlYVH0bcNm2JED89T4lsktqoN5HfxuMUdXDcPjxtEngMs8Hjsvr/HzV01Zw5u92KDS xJWnphm0Vif1IRLgT7qUlAwqri8VbvOy75gqa5gdqfICpXrnUWMZafnKzw7RuEziKJoS i1ETl1bxCGGNkWeOoP8BY00PF7q5yKWdGOzaLTGGUSD7vvqhMfBVWFTv4BnOAH0k12ZG /d1MgdcL8YEtgWLM38ZKZ8pDv8O5plCH7Oty376PyHCF1HIKLUxrz+uS/S1GYkizJlt4 aJcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4qjVm9wsFk96NgmHYl7UvnBuTY0x8lduv0VcruWM9xQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=gU5T81cQIilYGgivB+FrPHrvwRWkU4aoutZe3kNlA6VOszCPvGw4FNuSjyJ73xwQFY rP4JuZM+3uGJ+X2yaUgnRky8Fv/5C0hBvFE/tKkIiWMMmGxYLayjCKpqte+Ix4C5VaF2 bYzUTUVzbPbfX2xd6mqqdFq1fce8pUZOrwgfY5S+Ov8lOf1+qrrbEzlz2kTPFHIzpuYS tcSg84lILPVXhXmbOL55zr4iu0JYQUi1VX6RCizEljCrNZOG+/w/kLchL5fzUFM01LeG Ml02AdGlDMbbrKNWdhzty/fuTBMzUTguGa97jnQ/3L2FMlh34AIqj+/5WhaSOQzUhggx BsPA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qDeQ7qr+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/72] target/microblaze: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:34 +0000 Message-Id: <20241211162004.2795499-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-37-peter.maydell@linaro.org --- target/microblaze/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c1..0e1e22d1e8e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -207,6 +207,8 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) * this architecture. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b1ec534983c..d77404f0c47 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,8 +139,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ - || defined(TARGET_MICROBLAZE) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) /* Sign bit set, most significant frac bit set */ dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) From patchwork Wed Dec 11 16:19:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849181 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415671wry; Wed, 11 Dec 2024 08:24:48 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV99qAzKHone6xHo6Sd5EYQkFBweV/bDhPeGm5KlADAseItAhoiiDRnA4YNVuf4Vzt4b8LumA==@linaro.org X-Google-Smtp-Source: AGHT+IEqOFmu7O5px4MteNHLQjZOXFqT+/Rz+JiliStMpwVIm6Xa25meWBcJcaRhbUsjW49vLXIk X-Received: by 2002:a05:6102:c05:b0:4b1:ff3:6132 with SMTP id ada2fe7eead31-4b129162d83mr4031023137.21.1733934288230; Wed, 11 Dec 2024 08:24:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934288; cv=none; d=google.com; s=arc-20240605; b=c5GOaaewUru3UoLfsLvvLMHt9vuaLC6UCZyd/3yC/3H9sEi9UkWnFIbryLxwKRCSMd 2jwHievLc9UaujUPF7Hnx7ZfHituF9ILLuBju0hou6aJi93lktKhgXXeZlWQtZUOwf2V be5jqdiyyPkgZBtFuimsOmvE/miXzg5Ephv0q2GjRBQdeuv9hCxS+WygTDSYqJ8qU3Ps +0WaQaS5ZQsEzknCS8VVJPMH79IH0lwu3xlDNuTBPLnQ80mfFZXMAByn9OD/j/rBn5Zc CJlM1eSbd7MN8bzryJmDiewKrmtKKJGgmc57G51OywBCxNXAzPznJZUZ8sCTmsJ3SdtN u+Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mgg20eSIrnOO5pFUHw3GiJXeV9/eizL/vriHmsBEKfE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=iWnKRwYq1B8KjG/n8RKC6U0pV+F6b0hRmi9gbe6uhQm69hVUckmKdzSNRhB6nABodH hQiFHLm/I7TsRbr4eUkGhT9KdsTI+535UflQwWG6ZT1P84pVGXL9oKrjHVq2rP/Oe9D8 U/ZUVd0OAYV4859aA0qBRFj0C6cPOqxl0SFhPZp03s3zuYqBaIz0iycBPB1Hn9E/XcAN jiJoPcSHq4nEsB9KMb8KeLJuWF/t5LsUolIMH+OzgVk2g5x5h46+gYeyZJJuMqsnxD2p Qwy7l1F22G2w7ByPhmGQIY4VmnFzXoSZQH93ujEI7XmzL1hkmQtfHBcOC38ySR58e/DA 1NTQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=txfUR1EP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/72] target/i386: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:35 +0000 Message-Id: <20241211162004.2795499-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-38-peter.maydell@linaro.org --- target/i386/tcg/fpu_helper.c | 4 ++++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4303b3356aa..d0a1e2f3c8a 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -181,6 +181,10 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); + set_float_default_nan_pattern(0b11000000, &env->mmx_status); + set_float_default_nan_pattern(0b11000000, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d77404f0c47..452fe378cd2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) - /* Sign bit set, most significant frac bit set */ - dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) /* Sign bit clear, msb-1 frac bit set */ dnan_pattern = 0b00100000; From patchwork Wed Dec 11 16:19:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849184 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415749wry; Wed, 11 Dec 2024 08:24:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUSxMKOuseyzDPeN8sxDHOLTsePdlbLpEcUjJWZI+p379k3zVoNRGE2SrCfEfsHcBvoGbtg1A==@linaro.org X-Google-Smtp-Source: AGHT+IHAnr8vLNiOyY5TddF9EIyZ6G8IfC0Fc0/UUlyStDH/G0pjOQtwj1nPz0RDNKBKjQnN62lP X-Received: by 2002:a05:6214:20aa:b0:6d8:981d:529 with SMTP id 6a1803df08f44-6d934c3abb0mr49896626d6.48.1733934297822; Wed, 11 Dec 2024 08:24:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934297; cv=none; d=google.com; s=arc-20240605; b=JhL5IwNGJVBMXY6n9DtZFsjgGSin07grdozZzUIxKPptcCNR0IBBRIR7vHelzo1she W5QlR7ty8GUph4q1vUk4yEyg42+n3X2uAKJMRmsUVspZdnartj2T7Hfv+BQksE1ergAm 6+ULJ2gMRS0Urulc7vE71d5y0AwY6StZ2OyBSQ7uD+GkfJgHNpYCFxZd0kJgDisXSp/7 MAZ0G8Oafejm1va1XX9C7GEbHC1HFFZpBRHGgdzkgIeF41pFRLA9AygafK5BEbzpIOPq MmfLo9SASST0KkrVtFq/0lD2RMWeKKdTQDGji1/YVrt83uhtG7S5duKbsoPm6w5MPf/2 vdGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6N1dihOamyfHYjM/z+kdaJYMimdmA9nR0DIGLi0bWbc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=T61WM0CKi6vXTzEmWynWqKtpaL3YRAcv71Aqp0xeFWhSQtxxnr/Oqe/zRBdz6ME0e4 M8jQidZdYBxl9C8VLIQdExGccUufpyKxB2qIV9TuivW3vnXL4pG3Tul6KsPjiZedAmpU uEnmjAIzoYDZKg465HPaPMXGDmKs++4Rl2jYgS+BZiARtDtYOUrHwAYt/ARt5uwGG2W1 gJLxROyIwV5KMRnl0GJjT5Byny9B0XeNDYVvpBjQM1N8wxMEbJesOFAJt0SxQw+hI5/E Ukalg/q7+9i/q9jU0WCeS8SWeEQzQxu9p4lmjyIsFxwCrMtyKmJvSdO6rFPeRGs1NJMW PaRQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CRs2wdne; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/72] target/hppa: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:36 +0000 Message-Id: <20241211162004.2795499-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-39-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 69c4ce37835..239c027ec52 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -65,6 +65,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN: sign bit clear, msb-1 frac bit set */ + set_float_default_nan_pattern(0b00100000, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 452fe378cd2..b5ec1944d15 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_HPPA) - /* Sign bit clear, msb-1 frac bit set */ - dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; From patchwork Wed Dec 11 16:19:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849202 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416751wry; Wed, 11 Dec 2024 08:26:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVr84orA6n5Srb/S84DGa6fY7cISJ3LpWQVcv/2QsF3IFNEVg6CqVjrnQqu2+/4XsdegGUycw==@linaro.org X-Google-Smtp-Source: AGHT+IGzRnv7mmZT/SXvTlyMlMmVpVYlS4w15rE9LkYcsdv3Gflb9Ge1me2f9MaDw68CGomMOqPn X-Received: by 2002:a05:620a:2947:b0:7b6:d0bd:c7e6 with SMTP id af79cd13be357-7b6eb4d600amr536602585a.32.1733934407182; Wed, 11 Dec 2024 08:26:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934407; cv=none; d=google.com; s=arc-20240605; b=cUGi5/mUiSVNP5R1nxz5ZP1C7lNPEeuithyMWA/gN5YgaEeRx/Vlqs+8KPXBMUKxHD nYrMKeARIPORdmDFz02BQEfH7Hk3THcAlwOmKw8+K5LV41jVzzs1LdkJPtkU0GjNYxH7 ZMlOnZr2lLfBViXgdkP76Kol9+fK7LkSa9jO3Y6/IWf5kM0CkDtBEGP5PN6Fd/016ShV fzhlpWxXdoAdi3TGAnpJA9XIZUyFI0XTc52lqRylxfNdjIxWsQXN9ZqSBIH/m2Mziv9K T2jXpzUA3u2o9cog4F25UZr7IO8Gd+2IPGg/vXuKUBIfHifQCrTWw4qtKpsl0pDHKi9o QWvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yKsdVA6fFVWyT5C4g+dHlzCsxIZ5/YpoZTGllaXzw58=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=It0oIKE1qCFFVsLLb302JyHSZIVKoUEPf/AszoaQMD/aZJT2iT1t2jepjymxxGXg/R WAE9+juPiy5+oxfrvvjXMQHWh8eTWD/yDmfd46HHBDEpCRXFgi3Nj0TIX8QK6NjPOqRc XX9c9rADcB2QVcId3FSczqsTapcigSjkBMVo0+vJ7A7IbCHP5XhCzZkm83HB13qT9wCh ijyyWcci3RNMdKcqIkyg+E9vXWeEaf/bCNa1pk1zPRD8lbslC2XG0u0HWeV6aqE7qVUN vGeB56p9WOsF6pggbSCzJ9QjFJOEYKGo6JTvPlq7p1J/gCJC1p6c4hxJxUIUMiLfXBwy zxeA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RnNtyQ1K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/72] target/alpha: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:37 +0000 Message-Id: <20241211162004.2795499-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for the alpha target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-40-peter.maydell@linaro.org --- target/alpha/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 5d75c941f7a..70f67e6fd4e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -199,6 +199,8 @@ static void alpha_cpu_initfn(Object *obj) * operand in Fa. That is float_2nan_prop_ba. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD From patchwork Wed Dec 11 16:19:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849168 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414384wry; Wed, 11 Dec 2024 08:22:30 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXNGtMYgAEUZQT86AH3cZ0qmi84mV5FYsYeJehhbjnulC7T+mVJEyRMWX2YIvCDU3V9DX+Z3A==@linaro.org X-Google-Smtp-Source: AGHT+IGtmWXAsmAo2/61w0v+L3XjCFuwNGUYOG2K+kzzqPjSluS7I6bIAkCXudRG9cn8HWv0vg0d X-Received: by 2002:a05:6122:3d0f:b0:517:4fb0:74bc with SMTP id 71dfb90a1353d-518a3a10de9mr3121981e0c.3.1733934150250; Wed, 11 Dec 2024 08:22:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934150; cv=none; d=google.com; s=arc-20240605; b=RR2KoRqVmFTbHb6tkLq5PXUwp4ZSHx1/Dl4XjveUXEVPhyvnH5AcATf4UQ/E0LpNsR yxC37s+/ftsz8ctrbKX0c9IF+3D1MT3vjeIsXWY56y3VMhXwi6zvc8I/+K+2aQXUVvSQ BtH8tNj43I2NNaFVdGDl7fHwUi6UyrGM78OkTosQOUNHKxGhjL2zCkp5sPWsdza6ar2R l0P/lUlu2cBuL82b0pitCqIvVXvGbBBWHwMlMLjWAMqcIU6C+kk7Q8MiCEN/yjrI9Ebq wodiMUOJdqBHFWCHnaawjb5ylIUE18qyxFdQNPPLMy7TPQjhzXiG/byiEUw/bGl3ykqG IqOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2r0htTAsE1i09Hw2gTl/jAfOrYRUikK5HNqJfN6jEc4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Yjt3/6EfV5UqSN1CIojlX4S9f0pq/qhMCPS6do7NtjR+KDzGAaKRDfyIJM7wPUQfqe acsuIRawbKVImERF7mv76FEuCfT6ZDs0CGG0R1cgha7whzVp7kZzzC3eQD+rohEBYIma Ew7BjOjHc0LP6q5g06AVBJMKf8LOEyX+dwS7S0pkGkrRLrz5g1Ph3evR1tCxMV+O8d7g LozHPPpfdozvmls67PYXvexjA0slsInuCHOrvCjqu43WaZOIeweHT6Lk/eb3lY3LVVn/ 5DARUDbI37PBOMpVWGs9dypGjm76ojiqEg9rHZINZOxM2etS/kmOW46Mf5kq3ffS+9pQ biPQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EeXbrkHz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/72] target/arm: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:38 +0000 Message-Id: <20241211162004.2795499-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for the arm target. This includes setting it for the old linux-user nwfpe emulation. For nwfpe, our default doesn't match the real kernel, but we avoid making a behaviour change in this commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-41-peter.maydell@linaro.org --- linux-user/arm/nwfpe/fpa11.c | 5 +++++ target/arm/cpu.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index 8356beb52c6..0f1afbd91df 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -69,6 +69,11 @@ void resetFPA11(void) * this late date. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); + /* + * Use the same default NaN value as Arm VFP. This doesn't match + * the Linux kernel's nwfpe emulation, which uses an all-1s value. + */ + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); } void SetRoundingMode(const unsigned int opcode) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c81f6df3fca..4f7e18eb8e6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -179,6 +179,7 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling + * * Default NaN has sign bit clear, msb frac bit set */ static void arm_set_default_fp_behaviours(float_status *s) { @@ -186,6 +187,7 @@ static void arm_set_default_fp_behaviours(float_status *s) set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); + set_float_default_nan_pattern(0b01000000, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) From patchwork Wed Dec 11 16:19:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849192 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415987wry; Wed, 11 Dec 2024 08:25:25 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX1lz7ZpoKLNF++wZpqVAHMDcLIRTG0Q6PlatQhki2y5d1Y8qZO+2MgkTefiBPPrR6pmQEBhg==@linaro.org X-Google-Smtp-Source: AGHT+IGX+oN8vMBC2mcEE3lwRvzVb/5MrAZ6/P/Y5cr6H5wpNAfVG0S8ndIKnbjnT5C5exGe82YW X-Received: by 2002:a05:622a:8c0d:b0:467:6ae8:a1b0 with SMTP id d75a77b69052e-467892d2af2mr68518801cf.21.1733934325536; Wed, 11 Dec 2024 08:25:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934325; cv=none; d=google.com; s=arc-20240605; b=Era5KZFzkPK6GYSEHBgDqHj6b9zz7rjpqGuzF7VzOQ7BryDQxXyAHtuOpMwJENNWtU 3mHD77rH07Dzqo48ItuH+UiMxIeGt45nDv11opl/OCiKu8KNB1jZgyftZ6QVUyOQcLkF VJzfISgh1uCbdC2ZUTiwYVosQr/EF+VITpqyRZ5a8ujfJCcMmV7sgYwbhsD8KTlr3qYM MgqGmlFxT+tNyg/K34FGBcd4SFix13uw2Tjvq/wtXCOycuHjIhHNcprLANYtl1i7BZnM 3WP7O5YMWFOefj9A7AOtjCYqEhtC1Vo9CUSqVyb2MMa6wcC3manu1cjeOyrBHXFd5K+5 shCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CCObb/UU4fUvkP8uNIWpNMWZoNgBU5AdL8ALELaxgBI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Ky95B9Iz+EkpQMheOJCngVHAvupa7ir8S0SKhGG1wj04sQz/Nx0IuIEziON2K/so7t hqAWQRjne5ZdMgwrhCOJb71rYYWdBb496RN4lvDFjLIuJ2tHnt15pw9KNkGYGggBT8M0 QcR6B7vWEO0cjN7ums9I8eGhBcCHnV6QGBiAoPs/2K7yrS0VEsi85TcwJyH+s41Djnns QNP1D6yKlmb0qlAPxn5itV9Bcy45Y55cwWU2E30Rx49+9wc1R2gHa9M0NJGE07xxJnfE ESoASYQhio79z6+pF8LJjnB3wRx2fzeKdGDSypO0G54AstOJfVEIAxI6tBdHs589cwAx n2Hg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wqooi2zh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/72] target/loongarch: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:39 +0000 Message-Id: <20241211162004.2795499-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for loongarch. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-42-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index aea5e0fe5e6..a83acf64b08 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -38,6 +38,8 @@ void restore_fp_status(CPULoongArchState *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) From patchwork Wed Dec 11 16:19:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849210 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417018wry; Wed, 11 Dec 2024 08:27:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUZ11zj7XAvLchN0R0qIbuqKOQAbCNK/iDHa0C4fGoL2m7mIMpoRQgeWck5S0Q7Rkklqa7cFA==@linaro.org X-Google-Smtp-Source: AGHT+IG0Ee2u6qM/ZDf19hvduYfUzjuVXqqm/eQ9RAsa/T8gcUAPFkOj3jNk20O+JVlj9jEGtLbd X-Received: by 2002:a05:620a:460b:b0:7b6:6c2e:1fb7 with SMTP id af79cd13be357-7b6f1c2e242mr58640785a.45.1733934436266; Wed, 11 Dec 2024 08:27:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934436; cv=none; d=google.com; s=arc-20240605; b=ZC+5gXboBgBsJ6/ghRbqgTgchtjzX/vLZ2Ciu6vAhQlbly/KLglVVSNuj1xa14gvCO fhK4dEoMBVAIssc9dY93Fyyg3Mv4UIqGXzaYEWjGrk9tS6lf18Ndo9ZFIYn7nzkgf+j6 ktxW2htQ1LhrHDlPYzEzhrn4IdJlGa8FfeBT/AQb4nyGQQnMstIyVVEhq4SuJFYpLam4 oglZBonCDdNDfSN1gdOk2UyFWQtkujLJV4B8qEYM1Fiw1HUUC2F4Qku3Dc2dByDrR28p 1GCQo38y96drTgaZ6h2WoyhYnxk+itqRa2kQ2brztqecmvoOorPw//rXU+AbNk6vracC LVlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HIBxigbccU9+srEWhsNqTCAiXYWvyJ1k1YE9ZXRBOPo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Gd1YlXL4jm6aowYityyIZ4AnpRB5NTcpxrGlVI/HIHrmwWjdHBsjBK0voheIqIs6ZS hFsyUEoo4TmwBJqkb/cMIhJwEswxcQIf7uawAqKvFT4tS3a0kRQdiOTJu3PPfDhztJLb wGgzcaaN2x7tz/wC6bDzYPzh3xIYJCHHObIPMdOt4c+4coW+/kGsV1EViNTN0oFNtahs z0A/n1pq7lz8Pypnz8n916WGoE3gBOz5F0Ec5KsQCNSQQu88fNNSwI/K7Fqn09OTRisc sIbuE/cF1KNRPHWPIAG15Qv/Z9MAHGil7Udy48I61ZhsEeV26YdBOX+R3ZusbuPIqUVm ceWQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pFZzpuNV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/72] target/m68k: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:40 +0000 Message-Id: <20241211162004.2795499-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for m68k. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-43-peter.maydell@linaro.org --- target/m68k/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 13b76e22488..9de8ce67078 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -105,6 +105,8 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + /* Default NaN: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); nan = floatx80_default_nan(&env->fp_status); for (i = 0; i < 8; i++) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b5ec1944d15..ecb7a52ae7c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,7 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) || defined(TARGET_M68K) +#if defined(TARGET_SPARC) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; #elif defined(TARGET_HEXAGON) From patchwork Wed Dec 11 16:19:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849213 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417187wry; Wed, 11 Dec 2024 08:27:35 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUiEH9DQxDveiI5C89WxtBp+tYHcrx5o8C6h59IxjSlugZkMILhg7KXGERrpb5sqSp15l6f+g==@linaro.org X-Google-Smtp-Source: AGHT+IGNVWKaxDVw89PyqqeaJBkdRza9bDYMDjoGTBIZurZdVUWVdAwEMyDxf4fNJohcNE0AI27C X-Received: by 2002:a05:6214:ca5:b0:6d8:aa04:9a5d with SMTP id 6a1803df08f44-6d9348d2142mr56742616d6.4.1733934455003; Wed, 11 Dec 2024 08:27:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934454; cv=none; d=google.com; s=arc-20240605; b=UmUWUocCZAPaiuDP6r52Hd8ojdy3DT9eiV/15Ww1w5WiIRFgmicG6Df19Q0P8iEh8M j+PSRL5+gEomnh+h4nnziJ4cbJP+wXZOPvtexGr0JqLP4hAlDhB79aId753cizzm7HED u2xsh7zwXPfyeYB2Fwka2PRUTRjexcHxk/ep/D88PuK3uFNUk4dUbH6nFvRZnYSEMtxE 6SFUh2crIdbE9kX1AVy/5VPr5kIN0zS1RLzYnExCNTsTxhRqdRqD7tq3ZTTyH8STdq76 BJ5VmJ8ykC8I4fn77/YJIMGioqp6rz7/dQfY/GU7EY1NPeKiN0U7GIOxk/edF83HNRyd g3Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kqc/nDYRVw371GtkZwgUaEiTpivDb51JFPpNFEa+LMQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jVx5t4YAtaW7OWg/qlxxYqFZSlPLw+/Qkb2Nax5CLO2lPoShw2u52P/RMrNRVWjrUs e64I14491MBebtS3F+gJPz3RVp7S6YVo8Pj50DtXUmibOxbHMMdv8ZystXogQAlbHSNN TWnIa8iGz0vunoFOQPsQ9VZPzQUYFq+Fn/HzHjAKRCBogdjhAGuYAAoDH8781odcCwAb Vlc/slkiVCvohmH/+2ZmmzXiuE8cgOV0yYrzDRn0qzkRUppKo22EDASHRt+4FWCnyp++ nlLqD7G3tt8WFH56VcSXZGA+CblyU3RNq60xpwEPHrjipA0OP/tUCyK0wOTtdc2XSxMe oA8A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xxGLLGaX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/72] target/mips: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:41 +0000 Message-Id: <20241211162004.2795499-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for MIPS. Note that this is our only target which currently changes the default NaN at runtime (which it was previously doing indirectly when it changed the snan_bit_is_one setting). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-44-peter.maydell@linaro.org --- target/mips/fpu_helper.h | 7 +++++++ target/mips/msa.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 8ca0ca7ea39..6ad1e466cfd 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -47,6 +47,13 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + /* + * With nan2008, the default NaN value has the sign bit clear and the + * frac msb set; with the older mode, the sign bit is clear, and all + * frac bits except the msb are set. + */ + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, + &env->active_fpu.fp_status); } diff --git a/target/mips/msa.c b/target/mips/msa.c index 93a9a87d76d..fc77bfc7b9a 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -81,4 +81,7 @@ void msa_reset(CPUMIPSState *env) /* Inf * 0 + NaN returns the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->active_tc.msa_fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, + &env->active_tc.msa_fp_status); } From patchwork Wed Dec 11 16:19:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849182 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415741wry; Wed, 11 Dec 2024 08:24:56 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU+kgF8P1fOP70vnc4jCfbawK7D3kKTqSV80DblDUNAF30Fm9u33Lw6aUi1GrXcTjNJ71XDUg==@linaro.org X-Google-Smtp-Source: AGHT+IFEfujxm/d6o2pCXLtEVjI83HqytZkOAvBLlDGUKld/UUkGetvldhAxMY2sUZfRtFH+3Ovs X-Received: by 2002:a05:620a:1b84:b0:7b6:d607:96a5 with SMTP id af79cd13be357-7b6eb4d8733mr587911885a.26.1733934296585; Wed, 11 Dec 2024 08:24:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934296; cv=none; d=google.com; s=arc-20240605; b=R04JDGUelxMZxmlkoBAWYOSqIsF9FG0eWojrWy9hBAZr4uOvu+4kFzLWG0eatdYjRD 2rL5RHcZPw4H7sqCOYKPlPMmAnMD/q/q+HCtbSMD0J9hCplrsfxHk64xh5sI0OFPAJ7i RcapwPiQ6YGSF614U0bZ9bl/ct0pL0vgWLQAe0amSg3szkyOlm5u2aeKjuL9lJsvG22r zspJHna60iQ1Z4xP/dP9+r5k/eQcFB+7VZjD5j+R7ZXT0UMlw81aWnnytEf7JNX0pbUn gpuBS8Pt3Fi2UE3O16vHj/GWOoYa1ENcXiENilPR3zLc4+WytXuVRmnSwlKIoW6VoiqQ I5yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QOZvZF6lfd13HN9sGqs8XH84RBO0cCUPe2GnmCUxM8A=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=HMnOl3WJj5s9O3e4mmP/JC5JEZ3gFNJZ52RPSpmLX/fn6m2Iyk/d9iYSBZ9DhS+S76 Z9x99MsvFlO7nruodK0JDRxNAv8wlgbaB/d3N+4zlkmLSWEiGE2/JE+FIsaVxu3ta/hz lo3AwuI6dT2ndi1HBFVKpGVNkdXvm9+LarRBB/5385r9lzbwgrbY0knIychjd3ACPNcv py2flNVO2MC0APCpQEvtdHxO9jLoGcUqkAPtJdvsYQ/7yBi6FT/fo2za3g0P/xYMb24j Taq1XldyxP+hVzoG+swoghPjupf7ryCkvb1my54O89VB0IXTIu20ez6Y7pJtaYn1Jvwo vISA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pnpPf5zP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/72] target/openrisc: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:42 +0000 Message-Id: <20241211162004.2795499-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for openrisc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-45-peter.maydell@linaro.org --- target/openrisc/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f26..3ccf85e95f0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -111,6 +111,8 @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; From patchwork Wed Dec 11 16:19:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849200 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416652wry; Wed, 11 Dec 2024 08:26:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUTHKNZCNYMLAO0Y34vDJkpOnrq5yjG8qYm6n39jDdHW2h1XMPhumKLkU8tD3+nlMhVVww+wg==@linaro.org X-Google-Smtp-Source: AGHT+IGPvBe1lr/GQHlQymXTGb5hkIiETrW8kqw53Y75qNJk2tYviUIXHaPADEyIM8uW9FJh4gRc X-Received: by 2002:ac8:5d10:0:b0:460:8e3b:6790 with SMTP id d75a77b69052e-4679544f675mr4001761cf.48.1733934397272; Wed, 11 Dec 2024 08:26:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934397; cv=none; d=google.com; s=arc-20240605; b=MDoAOyOARwzGKK3dEVzlyW/IkGZWRz9e5GXt0lnHqQtW1Q0kESvPqAS+baJpawRoZZ 9zRd6fSpkZuQE0uEKHFdTNyUI3NOX0ofBYOUcStqBNqNV4UtCXL0yKUe40jKOJSWQOG5 3MJ8l2WEJdQFScI4ytjcP5scfLBlOtvHaiEatVCwWOQ6iYrfQUyt1Hh8+8iYrWHrKjc2 DvjvNzrr1NX9t7IXUDNI7VWY+dZgonj5QWVssaAK8VoJ13EaHifenYF3EAM4Z9+OXddC 3D5qSs8r4KBFSYXaDn5Xbowv4H6tJGyDq0q2d30tw+vUVuuQ+BuZb7q1HjQVAH8VGfP3 +5nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=upixniKzEOa/S8RuV1mPlSnfanTUMOTGZth3cr6koyg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=WaOcDWTB4WdtecUxWLfakxX8i2a3pCmYFpQ/68KTiDWjtmc9p6dtnkla5tQV0/XfvD dLyIFgt7nqCsG9DWYV3x2w6w0ctZ2RCGuf1huHMem5Nd/PHg8QIlFaVZ6B6LHm8gNQE6 qjGUFA9rNtAOGWONv9LU0iPgZTPTNxdWmU6z+fOXoFnkvPR15fGK/Yjtkv3BZiOy2xKs XfoV/+BM3yTpNLGtriBNrFh4hhfYh2VA2fHPres42dZa0UXzfgWKG6X27lU5gSeWHBKh DRKBEmx9gpqZ6O8lwhed59FLh8IIf/zfN5nPe8Tz+quhFweUNU2+RJPb4pUADqQ0Hq7d xvUg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wweJC04k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/72] target/ppc: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:43 +0000 Message-Id: <20241211162004.2795499-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for ppc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-46-peter.maydell@linaro.org --- target/ppc/cpu_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index eb9d7b13701..1253dbf622c 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7286,6 +7286,10 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); + /* Default NaN: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); + set_float_default_nan_pattern(0b01000000, &env->vec_status); + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; From patchwork Wed Dec 11 16:19:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849164 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414320wry; Wed, 11 Dec 2024 08:22:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUuDHlv2Nj5h3tPT7UOXncQbP7jBSqg6aO696exhOHfnm9SprFWPmpf843wAfXJ2Dls8FPdew==@linaro.org X-Google-Smtp-Source: AGHT+IEWgosUUNxLiKzbNcSObr2OX6/Wh76aHW+ySd4YUwN440SWlaNVGBE3c7ScUTnlTHvZxKNd X-Received: by 2002:a05:6102:4189:b0:4b1:20b1:bff3 with SMTP id ada2fe7eead31-4b245dfb24emr865434137.16.1733934142135; Wed, 11 Dec 2024 08:22:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934142; cv=none; d=google.com; s=arc-20240605; b=LE7pP1nqvEN2BgmE8GsKge73tA+QudA7qSZAtiJNbJfUCSIdwXeXtoVB1cZZQKQPt8 d+7bDt66FFI4ClORLGiFdkdYH9DST17l1JQsrAvaQmZLcC0ok3I4TzfcL9nGVxwxWewW DEtG7K9jcF6XQerUjQ9IHKdITYbkYniM5Pdj9sr6vyoEYPZU+Xxy7AvtxeQ2t7Bp7MKb oRU5V38/pc1O8Z0a+qkZ6VLOWgEfXawg/bhXJ0Y40Hgas386MC0V+3GntfP8zvIEzSOd 0zABRFmC2jSsxxbOxem/109EY0F8glP/K4yTqA3vu+DV25u4rPFRA9FRNoBVaB3tLfNf 6zHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ugtcp/+++sWtSJ1G0yYLp/YnlSvG52c5wPGIqMMfBnk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GGXyRvZ3n0TEBymCvnhCFS77uDTvuz1YhzielbpEsLeSkEoFZbCkJF+fA8MAsDEHRj /i6XggURFx4S7L26fXlmGR2p0+TD1BTNJvkQ30Rgo/ybym71oPhkZ2MDI+Hht6Szivig B/3qTKfhWWZDmK1ucDa1YRYasgE4/swseRCA9hJVwqozUW9V5UV9KjMsGUwUqg0SCK9o +8kOKXqAmO/wgmECXLS4WjDXcwSEGpls9ZKO6lFiAE0IGhhvacZHl7i7Ww5+mvwkIPVd SO7f897fmKEooBQo2ScxjYS95rxQ0GBiCyPNs1vs68x7PLUbYuJbZE2DPvfB0LcHTt2B FfQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EI5pQMr1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/72] target/sh4: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:44 +0000 Message-Id: <20241211162004.2795499-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for sh4. Note that sh4 is one of the only three targets (the others being HPPA and sometimes MIPS) that has snan_bit_is_one set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-47-peter.maydell@linaro.org --- target/sh4/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcfd..d5008859b8e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -127,6 +127,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); + /* sign bit clear, set all frac bits other than msb */ + set_float_default_nan_pattern(0b00111111, &env->fp_status); } static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) From patchwork Wed Dec 11 16:19:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849191 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415963wry; Wed, 11 Dec 2024 08:25:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUm7vBxqpaUVDTzUYfDlaiBZHnvTciPBV0zkXPjGKSFVjISK5f1QGuS13YOmmKTRtSMkbO/eQ==@linaro.org X-Google-Smtp-Source: AGHT+IGjX8UPVk7NMfd0SBbHAU/7fiGFQOiRfTiw9U1seZdBvNdKmCs5bIvh03aEkE1LPcDH1ubH X-Received: by 2002:a05:6214:5086:b0:6d8:b2f2:bccf with SMTP id 6a1803df08f44-6dae29c0536mr6147196d6.1.1733934322556; Wed, 11 Dec 2024 08:25:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934322; cv=none; d=google.com; s=arc-20240605; b=Cdj4PojVOiEAaMwBUZz/jNGmrA40UyIOoyHE4QJnow5p2KfW99IDm3LWyKlwb7CdBe bi9iyhvaM7EjBuqzlPTXIOnTKLiM4+e0CeMyuJXF84zNhpVVpJyguS1OFCQG9CWMxdpG Sf7ofRTYbFe7iy201y6y6R7FdcOuBoa3KN9rZr4PsIG3X5xl1BbAlAR6C93OTEXqLbpu CVGDIuGUfUk+GDOePQuuBYdmBDwYTqKsoGa/IyFn+/53Du37NcONclPSMJxabR8ApfHV LHBUR5+dqEL+TXbKdyvGFB41Teib+1uXAmuivSKb2T+lWCOnMZyvd38BZagk4e3EibY5 dH4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lp6ND6RqUxytAfiDR0J13A4aL9KjQfAUqGM2pRH1+ko=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=MGVQPe2DUJSP3I9rkgIc8hUIHProiJSkWqsmMBVathaycoeghzLOBf73RG8OxBteQ1 p0B2el/SlaF3e/KORV5YVjpi76PKeNMQqofhiH5+ztJRipX/eTuw4gU9XkftXV40yDy1 zAvK67zOxmnZOrhVcOOQ3n5ObD3uh2l8kLqxW3iyxbVS0suMic730CkDIcswvjE9LKrL ygW/WT5q8BrwB0Eixv23uA7uma0E+4DxRdHQJQCTGo5oPfNtjXAUArYn3viU2DoyYlLo SOzFSFjKQfE7QVQ32+HEcYu3bIUyllTlnKEQSsODTtQ8SoxzlJuF32/QfYS17Rj1FVQh JYRg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l4/DQnHR"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 53/72] target/rx: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:45 +0000 Message-Id: <20241211162004.2795499-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for rx. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-48-peter.maydell@linaro.org --- target/rx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720f..69ec0bc7b3d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -100,6 +100,8 @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) * then prefer dest over source", which is float_2nan_prop_s_ab. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) From patchwork Wed Dec 11 16:19:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849160 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp414040wry; Wed, 11 Dec 2024 08:21:52 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVk886nJvZ1ianc41MuB2GW95i3j0T3Rp0mWXvTHJV6M6e2uh0cIhTlYt68XSWz4+kJKS88eA==@linaro.org X-Google-Smtp-Source: AGHT+IHeTq5Fq9beagoyybX3ik9UG1IjwX4q6iQvugRCc96t5ObylMZYEZ2XwYkWIi4frpwB7Vsm X-Received: by 2002:a05:6122:2a0b:b0:516:1e32:f8c7 with SMTP id 71dfb90a1353d-518a574be15mr3215556e0c.0.1733934112518; Wed, 11 Dec 2024 08:21:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934112; cv=none; d=google.com; s=arc-20240605; b=e+NZlN47e+gXOBKS6Pk73A1SXObIh78Na6DaA54LqsKbfrmxHWMq1yq58auVJZv7pR SMotbKb34uEFxWpuMitaqDaZ1MwgPt0WqM8EYFBf3kmVl9/jDfWVPTw6rPN7/yPVOrVI YB9R0o8y8XbNiykOPH2q+BM9v1RWsJnLS55SBw1fDJLPMWVVjSY2rd+C8mmkwKsMtCjk 9C8GcSKY+5LTzd+V26+gNiLm++DE5yZ6W4YEjTfGF4etv2xeFwTdA1sNf1zpe8KpUCH2 DF5lKFw/K08Ey8pN91dBEpemjGaSPEecufaRB+raR6ua7KTD4+PO9H4Ou1t//itQ0MnS VfzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vq/x7YW4KLHoHlW1YH3eegjJxd8Sl/753I0gqQuiK/A=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jJAzn7g0RwAYW4p8yImoYlhwD81UqVlzsSePBaQEoN1n8P6cpEjUeeXaVNZb42Vtch TkP80j2mlzAD1gl+rpQTD7j3kqPPkUONoxjtwmWDMywTz3HaWglA2BGyhRBXRhvECY8w ZisI4GKGr3Lg82IF2geBQQoS3Ck9KmYWBkJiX0xvqIqGELxAaN3fqXwiGuMTMqNBFIHv dhKe+7s7Gl+1eZHifqy8U8iKB6XD61DV83meC9brheFbciMk4sPUCoDgy3JEkZJ2sBm+ o1F7ZyINQdO6WIRcFDQjPthwTBECJLwqnCSS+O0+XZzHRmCTfy/+m1nLlwwELiC1ytwm wALA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="eWku/iYw"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 54/72] target/s390x: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:46 +0000 Message-Id: <20241211162004.2795499-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for s390x. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-49-peter.maydell@linaro.org --- target/s390x/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index e74055bad79..adb27504ad5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -209,6 +209,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; From patchwork Wed Dec 11 16:19:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849207 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416987wry; Wed, 11 Dec 2024 08:27:13 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW1ZEHUxVxNXWVzvD967mgHJiiy6m3M2jgbpR6KdC+/2V0zfg8fuxrMrp08MgWIAYsFXvJZ3Q==@linaro.org X-Google-Smtp-Source: AGHT+IFprupe7fIKHEfyj5TML9BJUIkmFT+p4Mo4YeKCroLjIZSoQ0tr5Y9mRsCdkdMgANi7ZIH7 X-Received: by 2002:a05:622a:130c:b0:467:73f3:887d with SMTP id d75a77b69052e-467953df5f9mr6678311cf.33.1733934433720; Wed, 11 Dec 2024 08:27:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934433; cv=none; d=google.com; s=arc-20240605; b=VO9JoSki+BShNnKMh8kDLm97YuIsulZu/o0o66TBTQfiJKngpJsMVs+kiFSu18d8Tw OcrRAeqk1kg1id7YY/dwjdWQsk457+O4j8b4mnd36lsuquBEsCKLWH3j69uYrhPKWdUM Az0x+l/7XeyJVM+aKszT4BtIdbYr2+WWJTPml3OekYdHDSX6aWT5bziDHyJmCL0+IDVg NhwXoo6ziLF4qAF/flyCcYDiniwBi+f0jweqbL1Ao76NdQtoypm8qVBB5BWRtas5qili cy4eIxNiNFk19mq7pqKCJNrZWCVFSQy03aacdPz7NKc3Qw63pY0k2e+6OvTNrVBA/by3 pwOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9o6ZrjR1RXdiifOcsykBiN0/Ne/2VfOey1zb2DGye7w=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=bDo6LHuwpwsEb/NuCCdcq7KLliMr35wNjH1kvsEg5USRrm6rkbQ9YGn1xko9ut+gTB wjesuGuQSLsQ0goEed99MgHgsT92AUgMuc1GmVd7nwZqcHWemHVkIemL0YHaUBTnhPn2 EFnbv5xyPt1MFnaUmim6W/5IvoL6cMFdlRilcgTlBkHc55lCGiJxtISWvf6xkGJMQGaH lw6gQMH2ccHWyysnTqDSiAfWs5ky95lQSHJNKUEOAHcCDuyvuf+YPOBz8QSXs8qDfHBz x6sbwzQJgFk6uPdfcD7AJAdwywAzWg7vaYkryLJETdJNs044wgAIxyu2va3WDNAojuQI JL1w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nbCQ141Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 55/72] target/sparc: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:47 +0000 Message-Id: <20241211162004.2795499-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for SPARC, and remove the ifdef from parts64_default_nan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-50-peter.maydell@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 +---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 0f2997a85e6..6b66ecb3f59 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -818,6 +818,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN value: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ecb7a52ae7c..06185237d0f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) - /* Sign bit clear, all frac bits set */ - dnan_pattern = 0b01111111; -#elif defined(TARGET_HEXAGON) +#if defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; #else From patchwork Wed Dec 11 16:19:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849208 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416989wry; Wed, 11 Dec 2024 08:27:14 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWXqjKELxROthgeQg50+goweee4qTyQ2fwpGwoDLNaHTbzxU8vT9+UeW6xn8bffrpK8O7wbUA==@linaro.org X-Google-Smtp-Source: AGHT+IGcfW5fZU6/bO9YwqrmjQ4I1UJEVOZE4aA3sB1wV44TfAAN8nUMLubqCIMruX5l7DqRjHsB X-Received: by 2002:a05:622a:1a05:b0:467:6b20:e0b1 with SMTP id d75a77b69052e-467892e8a9fmr57840111cf.6.1733934433652; Wed, 11 Dec 2024 08:27:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934433; cv=none; d=google.com; s=arc-20240605; b=ABnRxaePcNqP18JzYhZgLjpQP7lWQqIXwLOMnpNnoungGNV5YIsO8bjgeg+G9Zp+wW 8XnIkhw13uwuE+tFUfpirxaYQjSyBQcEwMg/tUlhriOLlsF3VVIVrEAh3M87RdFm9OK0 I5kI25qGvk/fCWi3LlwvcM83Cqs56EzJw/jvYb+asrmJpAmk78JXXJtp9H2kNX2ddcra 68CSVGjgqBbatL+a/XV0xuQBefjUht0Z9Nkh+yvqlu5GJLjvE+CQ92oFpfmgj4UVrPDP XxgX8sE9yqR+lNVMaXxlD9OPQs++ASH1QnrqdpFznMPO4HGnwSi5BNC9Vzb9qOlD3z5D qD7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XpM+Fzv5WnqhGSvzHLutaRhswGeDxDx6i0Qnjz1mXt8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=G2Kom/o/9GPyj6JKuZqs4JbWoL5MyHlDbiJClXEE8QwxCRvJC49cOJ4clBggrEYRGL 0CA8SgNSbhwogTdY2Z42SVyOFNy81rszJcLxlVF7WV3vl259Pze23WbF5/pg69pGpqgA Sr+ZOOCIqG6Gj1m/zib2eloB6bUYg1BrhzLhhH5R8QVtWFerf0Wm5XtGgPmsWPOV6dGL YN6TOIVB5Ox22jJTfDsMVy4MLCtpkED1e9L1o0g8IMkNSimLhu+i1JjclO25Gze12X33 CQALzRUjtFzq9C/N7E40L2EJ0sJkWy5QHTae/0O+VEjPYYBCfXOAv3O5dNxtmCsFI9qc tPtg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PnNTz+Ye; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 56/72] target/xtensa: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:48 +0000 Message-Id: <20241211162004.2795499-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for xtensa. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-51-peter.maydell@linaro.org --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3163b758235..0d4d79b58b4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -136,6 +136,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } From patchwork Wed Dec 11 16:19:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849194 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416199wry; Wed, 11 Dec 2024 08:25:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUmKkDjOa3DHSmE9eO80vqobgT97dZwst3YIETL6kt15WTXwgjc8H+JFIVZaqwyPxAN0qikAg==@linaro.org X-Google-Smtp-Source: AGHT+IGEbqcGsoML3bmzA/nNP6oJD/fJQk7GNnTfWdDCyFsCOn6GuXxB8CEVM2W8JbhMTPvO0SoR X-Received: by 2002:a05:620a:a10d:b0:7b6:ea22:3069 with SMTP id af79cd13be357-7b6f1c059admr38844885a.26.1733934347385; Wed, 11 Dec 2024 08:25:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934347; cv=none; d=google.com; s=arc-20240605; b=F2wC5iIdtDUn2nsgAYjayZPt4gfg/Apf6Cw4W74Ji19JmtpLNOnuYo/VOImCBT4Giy K0r+QWxWAqSeCqZIaFlP9R5Y57Q6QWwgwe0BhiWlRX2CPCTsYzMXvk6/5rUKSlLZLWrT 41ICJ62NcF2xqWfkao8Qp9occO9qhKyUwnTne28YFI0NUnOK997eAl+dcZTbUiIrredI o0q+9iFn2XQseVK9wtgtGHyn88BRrtkN7iycQsO/VCH/eut5EiZYrcw805QqToG9YxNT Z13chVxF0D5QqBoG6ET+BPlaRPSF9gqXpATFsghW4+wZcm1R7dlLHdQ9hw44bfDn14Pw /WJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IFPKx6cYxrOvlpHIeqyqWQFosyF9dmEm3zNoKTLP07g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=iPHjNNqm44cypygMphPmVHh2NDX/IFdrIGqAdigvdkmD7EVtaLvXKyKKYAy9zZ7bYS P8rfbPQmQX0fLOFEpZabwP3wdwiFrRQtigt6wqPcD2xRiwH5NmNgBIPMbEheG7hgTgau XSxHjbn6qQfsEJPf2J2RTcMT520UQEqSaXelQCxFKbzE8hpPGlIendXbPkvRgwhQF3W4 BtD7EAOBDgV9WpcvLGu7Tp3dRI7ohtXy+rpE7GbzJXxg2JJqHvFc3jKB+iEE/lP6OBWC n61k21wM5zACrgGcjuxE8u/qu48gd0BCemtPx9pQRdeXT/F8Oys4RMiDwmTcojOJ4h3K eMrQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCAD+7vp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 57/72] target/hexagon: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:49 +0000 Message-Id: <20241211162004.2795499-58-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for hexagon. Remove the ifdef from parts64_default_nan(); the only remaining unconverted targets all use the default case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-52-peter.maydell@linaro.org --- target/hexagon/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc490..c9aa9408ec8 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -286,6 +286,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) set_default_nan_mode(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); + /* Default NaN value: sign bit set, all frac bits set */ + set_float_default_nan_pattern(0b11111111, &env->fp_status); } static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 06185237d0f..5954a6213b9 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_HEXAGON) - /* Sign bit set, all frac bits set. */ - dnan_pattern = 0b11111111; -#else /* * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, * S390, SH4, TriCore, and Xtensa. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-53-peter.maydell@linaro.org --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b52..80b09952e78 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1022,6 +1022,8 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); env->vill = true; #ifndef CONFIG_USER_ONLY From patchwork Wed Dec 11 16:19:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849196 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416315wry; Wed, 11 Dec 2024 08:25:59 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVArTZ9VNr5LhrqaFTZECOE3D4vntJlGMEqEs2uPwCNg01qcpmC4aZlg23VmWSA24dk6VSEPg==@linaro.org X-Google-Smtp-Source: AGHT+IH5buyxEAwuTHJlivv5+A4IKgy510gIoDeaWTx/rEjEe/nOMdK2dScXL7e3cMfhOSxp7zYz X-Received: by 2002:a05:6214:3018:b0:6d9:2e0c:56c9 with SMTP id 6a1803df08f44-6dae29c3573mr6384396d6.9.1733934359322; Wed, 11 Dec 2024 08:25:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934359; cv=none; d=google.com; s=arc-20240605; b=BwmKZU52EcWOD2kCTRCCU7J7EDQvu/8bM+7FdmgqllEjGoUMMGxP3gdOby7mRAUVZw 2xiDc0CLCyDep/DE5F1tw2c5/4g0YULkj59/SXFH2cogDVaHYmoVEq9v736WrLNen4Qu LrcCrniXhjWa2NCsCvJC8NG+xL3g1H12vIDh6TiBd8fqzkaZ2nGzHBLY2/gzKBzisfxq yOvA45jWbEpLTCF5v0kyhLSSaMpe5VVvhS+fwo2r536C1PzxJHXTsUkFfi1aGpu+tba9 bwuo90v7rFTG+vBMCZfintpP1WG/1M4EXUAc8Um822Ns9pS8bojkBg2c80/Sv/yuctpu eV6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zslQ1Gnt7shcKGxYg5Es0RVybgupAdobUOUAJLVJUTs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=c9IiqTDcSklW0/LwJud19JSCrcB19qi2V7yUFr6Bf51iqnLfS7Nk7m7TISeof9xhGT CzUbhbor8FI2bWj2k/yS3668bxSqi/VbFcPRWRWO8x8F8AfFfbMw1DJJM9uiBx16oqTv fjYJ7nlV6LFCc7rq3vZbUEZIfGMToxzWHRuf1e1s+FrkR7PFKSPa30DN61TvUp1B14yF zrqreRz1PWjfCzEPiBb1POEjBaBv/R5jWMnhV/XcvrBX6crqRywm2CoUJts/b/iWqptP dETsCoFHdakts/GzGGVL1YCC7B6Es6xdfaPNOwsnHR9Lx3Z4tlDMWPY0HKxiHINVtbOf iYrw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m+XpC6Ju; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 59/72] target/tricore: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:51 +0000 Message-Id: <20241211162004.2795499-60-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the default NaN pattern explicitly for tricore. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-54-peter.maydell@linaro.org --- target/tricore/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77c..e8b0ec51611 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -117,6 +117,8 @@ void fpu_set_state(CPUTriCoreState *env) set_flush_to_zero(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); set_default_nan_mode(1, &env->fp_status); + /* Default NaN pattern: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } uint32_t psw_read(CPUTriCoreState *env) From patchwork Wed Dec 11 16:19:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849180 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415654wry; Wed, 11 Dec 2024 08:24:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV6LDdwp/m4sPZkaAzVIBN2QqjzR/l9cIYx92fRUOzmVB/Ub0ia/iGPsojwAmmY0xsAdVuwQw==@linaro.org X-Google-Smtp-Source: AGHT+IFv92NWsBk7x1PKjSexqbmdYt43rlusELBZTXft1qF2CYIud+WwEoyoGD4Qv3Phmr8HcJRA X-Received: by 2002:a05:620a:2a0f:b0:7b6:d34e:b21a with SMTP id af79cd13be357-7b6eb4e79abmr670603385a.37.1733934285444; Wed, 11 Dec 2024 08:24:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934285; cv=none; d=google.com; s=arc-20240605; b=jxq+EMsKzEf+/4N0zYy+plD7o/Ft6bbRAAT2ktcvkJ8wfSWz5CXH4aJW3LUAtQ3tyB 6/H6N6Lk5CaVKRgjPC7mAFSUY9Qb3gAlfRAesCrk1EeS1nckEto6UwGuUotLCYgpA1d8 IPqzrfcNKZT9cakcfMIS9JI+ZWnVuoVAwacEOMKMokoeT+6iznZiBTRMXLJXpZB0HxQL RYSnV71vOKrUSIQwtpVpNtyJD6W+NNqOC4/N3mTrGwwBlaIzS2XeZowp76mvXKHhrTvv HF1muH3LRqg6z5xSEgN1smSbNgYylt8xrI89cmKrwgzPAk2eIX+DufnZ9gAnVVKhcO0s +/rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+m7UpkWXOD0kaMSleyeT/gE67bFfwBTpfKeuDgBDdb8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=iATFe0WGulgnZYTFV8j3ZOl3EZsxhxNUNj/0DTKAXI9TTL5CxM74ISkWWjYXxUDiSp 59vQFiiH7XJ1TyfPxbzlzDjqwOL97cAMgNh/Kc5ewvXiKLUJhCGIjCqB583+kiDAAsKs NuqvHGSC4JSEZh0vuXdi6ghh/sDJiRU9OMMH/xXrdxsKLy1xiOn2n45toigsjEm/dI0/ g/3BFwKhKWwcVzImrFmVzwx102gU9hf9dXTj+wOaIYGOxWzF+U3V2p2fCDv/Jim0pfGD CU5+qIaQz5a4Kly8XjKW3UaK2AAlTko83I6dXgYH1KLfYlvk7m09xM3CG3JcqNiV//Pq kvew==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HFBgsITz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 60/72] fpu: Remove default handling for dnan_pattern Date: Wed, 11 Dec 2024 16:19:52 +0000 Message-Id: <20241211162004.2795499-61-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that all our targets have bene converted to explicitly specify their pattern for the default NaN value we can remove the remaining fallback code in parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-55-peter.maydell@linaro.org --- fpu/softfloat-specialize.c.inc | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5954a6213b9..e075c47889a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -135,20 +135,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint64_t frac; uint8_t dnan_pattern = status->default_nan_pattern; - if (dnan_pattern == 0) { - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* sign bit clear, set all frac bits other than msb */ - dnan_pattern = 0b00111111; - } else { - /* sign bit clear, set frac msb */ - dnan_pattern = 0b01000000; - } - } assert(dnan_pattern != 0); sign = dnan_pattern >> 7; From patchwork Wed Dec 11 16:19:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849221 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417459wry; Wed, 11 Dec 2024 08:28:12 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXn2SRZCiBwhUh/oknrHRfF+c8486tS1yET5y7Q1vwofzWEJg1s8Vx4FI0CH8FWB8mNd8LTLw==@linaro.org X-Google-Smtp-Source: AGHT+IFATH2fqqUR1ff4Z0YXqQCoix+V1u7IfCBPzGQel6wp83yh8FwRox19cjSvXQfJAzaoz1KT X-Received: by 2002:a05:6214:5190:b0:6d4:4100:75a1 with SMTP id 6a1803df08f44-6d934be0752mr53139686d6.39.1733934491888; Wed, 11 Dec 2024 08:28:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934491; cv=none; d=google.com; s=arc-20240605; b=OWBDyZ1f9pgdBE9sAzjrcSJPAjmzqwRq41I5Mw04bMC4x1DpLn0XJbHjXY9zwEdLjT 6VXU7ZoMbWWbs952CDDnx+KcCjF8WARyJbEg3kcGeBifGWS96/QRDByLbnYzlqtujxO2 1pWtcisQ8bvfpWBf8gYk0j5Ibs1owcQBDq8R/Zq6qlx0wNn6or0fN3mKh5/v+gAUmyO/ c/Xlb22FPNJAsIkEc3cgu/mS2UF0lUgkuiKADGHsF7WSgo90cDmtyF+60lyRF6n+KQWW gXPqfANvYnuBdtD2T0nV/DbFbU07bdH7tuPRf4hfwJqfd1swUmtfnJ8PibQ9EAka0r4U aDtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D00DSruytulbxjjJ4e78+Qdhi69cDsAe2XaYdtO6NTo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=hRzIFdvG0AmEqgiSReDDa7g5Me7BjIUfZ4jXm6t6Tm99wnj10YwyJ4uGFX8VlH37m5 J5wX0OlgabrZ5GwcJBJL2JA9YctP9l92cyngHIsbZkKBYK8RRrwwmge70xBhI92g6szk njw4tLGKMuRVhevi6WAWo6aii3PRIdpmy50g+FDFO+2oj8maELUu3gvj86PkFCv+oMen XbU9dFcKXarGEkqIjJUCnJd1ksSC7YMaGK8ADdovQv1d3Vt4KcbJ5/b9WnUTGOrSPGQ8 6ICzbI3dDVoowLselXgHBKP1mGe/69cel+9vRRw92BLc0yZmFum1xURZpgzyaNN/8OAV Lc4Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a1xpGjNl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 61/72] softfloat: Inline pickNaNMulAdd Date: Wed, 11 Dec 2024 16:19:53 +0000 Message-Id: <20241211162004.2795499-62-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Inline pickNaNMulAdd into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-3-richard.henderson@linaro.org [PMM: keep comment from old code in new location] Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++- fpu/softfloat-specialize.c.inc | 54 ---------------------------------- 2 files changed, 40 insertions(+), 55 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 655b7d9da51..c1a97c35b20 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -79,9 +79,48 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } if (s->default_nan_mode) { + /* + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify. + */ which = 3; + } else if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the + * default NaN here, and some return the input NaN. + */ + switch (s->float_infzeronan_rule) { + case float_infzeronan_dnan_never: + which = 2; + break; + case float_infzeronan_dnan_always: + which = 3; + break; + case float_infzeronan_dnan_if_qnan: + which = is_qnan(c->cls) ? 3 : 2; + break; + default: + g_assert_not_reached(); + } } else { - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); + FloatClass cls[3] = { a->cls, b->cls, c->cls }; + Float3NaNPropRule rule = s->float_3nan_prop_rule; + + assert(rule != float_3nan_prop_none); + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { + /* We have at least one SNaN input and should prefer it */ + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_snan(cls[which])); + } else { + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_nan(cls[which])); + } } if (which == 3) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index e075c47889a..f26458eaa31 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -448,60 +448,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, } } -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a three-input operation. -| For the moment we assume that no CPU needs the 'larger significand' -| information. -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN -*----------------------------------------------------------------------------*/ -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, bool have_snan, float_status *status) -{ - FloatClass cls[3] = { a_cls, b_cls, c_cls }; - Float3NaNPropRule rule = status->float_3nan_prop_rule; - int which; - - /* - * We guarantee not to require the target to tell us how to - * pick a NaN if we're always returning the default NaN. - * But if we're not in default-NaN mode then the target must - * specify. - */ - assert(!status->default_nan_mode); - - if (infzero) { - /* - * Inf * 0 + NaN -- some implementations return the default NaN here, - * and some return the input NaN. - */ - switch (status->float_infzeronan_rule) { - case float_infzeronan_dnan_never: - return 2; - case float_infzeronan_dnan_always: - return 3; - case float_infzeronan_dnan_if_qnan: - return is_qnan(c_cls) ? 3 : 2; - default: - g_assert_not_reached(); - } - } - - assert(rule != float_3nan_prop_none); - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { - /* We have at least one SNaN input and should prefer it */ - do { - which = rule & R_3NAN_1ST_MASK; - rule >>= R_3NAN_1ST_LENGTH; - } while (!is_snan(cls[which])); - } else { - do { - which = rule & R_3NAN_1ST_MASK; - rule >>= R_3NAN_1ST_LENGTH; - } while (!is_nan(cls[which])); - } - return which; -} - /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd Date: Wed, 11 Dec 2024 16:19:54 +0000 Message-Id: <20241211162004.2795499-63-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Remove "3" as a special case for which and simply branch to return the desired value. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index c1a97c35b20..be7e93127d4 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -85,7 +85,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, * But if we're not in default-NaN mode then the target must * specify. */ - which = 3; + goto default_nan; } else if (infzero) { /* * Inf * 0 + NaN -- some implementations return the @@ -93,17 +93,18 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, */ switch (s->float_infzeronan_rule) { case float_infzeronan_dnan_never: - which = 2; break; case float_infzeronan_dnan_always: - which = 3; - break; + goto default_nan; case float_infzeronan_dnan_if_qnan: - which = is_qnan(c->cls) ? 3 : 2; + if (is_qnan(c->cls)) { + goto default_nan; + } break; default: g_assert_not_reached(); } + which = 2; } else { FloatClass cls[3] = { a->cls, b->cls, c->cls }; Float3NaNPropRule rule = s->float_3nan_prop_rule; @@ -123,11 +124,6 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } } - if (which == 3) { - parts_default_nan(a, s); - return a; - } - switch (which) { case 0: break; @@ -144,6 +140,10 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, parts_silence_nan(a, s); } return a; + + default_nan: + parts_default_nan(a, s); + return a; } /* From patchwork Wed Dec 11 16:19:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849222 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417780wry; Wed, 11 Dec 2024 08:28:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUuOJyuR01qfdodnAwXGf0e2WMuhK7NHkXjvhEzntHvYqjQhnPFsQbTGuxdP4RyDS/PucWqtQ==@linaro.org X-Google-Smtp-Source: AGHT+IEQU/+DCVjx40fKBOB/IlVTAFr/BqgK21v+MUQcqIVI6YJBZmUrK6bE96l9nTlsuPfxhCSk X-Received: by 2002:a05:622a:1186:b0:467:6ae2:75cd with SMTP id d75a77b69052e-4678933e24emr65622691cf.20.1733934531107; Wed, 11 Dec 2024 08:28:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934531; cv=none; d=google.com; s=arc-20240605; b=FKYgvmPPG1aD6GPvVBOB/SGaVVMBqLT6uPy/aKCXUdIKxKhZ8Tah/U0G9VtCbIo2ba ihfXFf0Vqu7/mMQr9jJUusaAunugwmR8JosabRtfrAjS5LuzFJN3UxrHrohHvLZazhqr dG+G6XsCfj+ROigjHirPyABaV75v9umtC8SMBNpNTXOXvChXVIwCK0jJN7yHUUCWYhl/ rJ8yR774jLWEhvH/8qbOewG5IH5dXyIaBHcZUSfc2v0sEecv0pb/FxkKbtX4i96sCW6k 5x+D6djfPu2TdKSUGV2CeL9FccZgL1ev6xN/O9Cf50Gka0G/uDYI7+ome7wOn7BFP5Dh BvDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WxD1Jy1Rj/MBN3Hz79N9s4ZRpfmRU1nfzEotTIZVleI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GBxp5BH7H8NgDChqd5NKb6QoF6bX8YDgjGDnoa0jd/Wg9IPP1AAQyXDb06IuKD3xxr lyJiRcWWzNZeluU5CSMycP+QgVWRgssrn1ubZ/52p4GNml2evnVJUn0uj+OjxhBOQcOS 5Ts11itA94xNYzUSyuRPYlNPH8qCVoCKgETFkprQEP5XOpAXMBhxGBt0tsP/mnA4lR4P Pg7pABacqfHnMUbA4xhyZl30PtwTVvryqSSJeTehG3LKcV6b+YdaYBiy0dJz13U4q2k4 KDoapI/knN2v8zahyFUj7toVP+5LT8BHUXGL7+kTmozdzoZ+3ZVRi2kXDERv4AGqkdqI qA4Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AhFQRpGq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd Date: Wed, 11 Dec 2024 16:19:55 +0000 Message-Id: <20241211162004.2795499-64-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Assign the pointer return value to 'a' directly, rather than going through an intermediary index. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index be7e93127d4..525db617411 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -65,9 +65,9 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, FloatPartsN *c, float_status *s, int ab_mask, int abc_mask) { - int which; bool infzero = (ab_mask == float_cmask_infzero); bool have_snan = (abc_mask & float_cmask_snan); + FloatPartsN *ret; if (unlikely(have_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); @@ -104,42 +104,30 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, default: g_assert_not_reached(); } - which = 2; + ret = c; } else { - FloatClass cls[3] = { a->cls, b->cls, c->cls }; + FloatPartsN *val[3] = { a, b, c }; Float3NaNPropRule rule = s->float_3nan_prop_rule; assert(rule != float_3nan_prop_none); if (have_snan && (rule & R_3NAN_SNAN_MASK)) { /* We have at least one SNaN input and should prefer it */ do { - which = rule & R_3NAN_1ST_MASK; + ret = val[rule & R_3NAN_1ST_MASK]; rule >>= R_3NAN_1ST_LENGTH; - } while (!is_snan(cls[which])); + } while (!is_snan(ret->cls)); } else { do { - which = rule & R_3NAN_1ST_MASK; + ret = val[rule & R_3NAN_1ST_MASK]; rule >>= R_3NAN_1ST_LENGTH; - } while (!is_nan(cls[which])); + } while (!is_nan(ret->cls)); } } - switch (which) { - case 0: - break; - case 1: - a = b; - break; - case 2: - a = c; - break; - default: - g_assert_not_reached(); + if (is_snan(ret->cls)) { + parts_silence_nan(ret, s); } - if (is_snan(a->cls)) { - parts_silence_nan(a, s); - } - return a; + return ret; default_nan: parts_default_nan(a, s); From patchwork Wed Dec 11 16:19:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849211 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417131wry; Wed, 11 Dec 2024 08:27:29 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXlmGRnuBBol8rH4I9QjSu9hOjF9euilSw6DTzvRCGJIHsUNKcChTLaxi0OiMJdjc0SHxlARw==@linaro.org X-Google-Smtp-Source: AGHT+IFVZ2ebhwFRQkcF45gYQWAo1Rt5TXsNfDfuIGjuC2nBDlJrnvdpEZ27skG/t6woAX2iAym9 X-Received: by 2002:a05:620a:29d4:b0:7b1:11ac:627a with SMTP id af79cd13be357-7b6eb475ee9mr545422485a.25.1733934449227; Wed, 11 Dec 2024 08:27:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934449; cv=none; d=google.com; s=arc-20240605; b=euJT+xp/gLHADVeOacGf1v+5H38wpBvFVxSraLYfkQk3H7rid+ESHSO0EnjepyxV+g tWQsEwYv7tICVmw3F8ij8vbDKpH2ekJ9OmfEC3tT6YOjSBfN68w8NPz0Y0H5yI6WaBCc 3Yb6KWit0b/u/5U4sb1tbFTVV4m74FlMiR0OVCxJjuXsqa4myfzNYdN+Q7iZ05QQK7Sq T3s8QpghfNyNDzCoTqbw+pBn5C9SCrmCN5/NqdkYo8Qgx63zoKWXlqLpjou8jb/SsXgk TebHjy5kd95NctZMjBRNoDJHPW6+oRhnWP3w4Z5ap4alwWQya8YGCRbVelA2DtLHIIHx c5Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EDkpBBfEr+kYrGwFggLG/G/iyWn141UY3RpqFYSFXYw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=gwB8jHZLQZTlSD136Sx5Cmo6iMer+V8OraEMQqjJ7NWS6I950sAPk3ObuH2cFSzmL2 z+0z0WaW4olvIqAkp8ml76Yk8rug1ycL6/KClzzzo2b1LZ0h52HCfrwpRuh3YE+XlKP4 llztHgeWe83E48q9gGDToJN5xax6yLxdtHUGVkUHYpKbEylA3+otLq+TZ9pAw7GhaEEt gs5p/DrHF7A0zxepAtkq+GuCvA3q670mhBq7+80wZVJT6jRqS2TIRnXVteoOXo6PdXYT 9tJ4eWlGQDaVlCIBU0l7v3l1atZQUfFFc+xXkOUx8i6PYtF63JNyA9y1QuOquWZ1V2nx yuqw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=klx1dFC9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 64/72] softfloat: Pad array size in pick_nan_muladd Date: Wed, 11 Dec 2024 16:19:56 +0000 Message-Id: <20241211162004.2795499-65-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson While all indices into val[] should be in [0-2], the mask applied is two bits. To help static analysis see there is no possibility of read beyond the end of the array, pad the array to 4 entries, with the final being (implicitly) NULL. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 525db617411..5fcdbc87fd7 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -106,7 +106,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } ret = c; } else { - FloatPartsN *val[3] = { a, b, c }; + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; Float3NaNPropRule rule = s->float_3nan_prop_rule; assert(rule != float_3nan_prop_none); From patchwork Wed Dec 11 16:19:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849199 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416531wry; Wed, 11 Dec 2024 08:26:23 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX1bo7xYeMTWowtK85bMJbOkGd2h25g+YDbnAyRqyUNTDwTOumPpjEtOn0XWPEmDuA0MnPlgQ==@linaro.org X-Google-Smtp-Source: AGHT+IF3rP/NVeK5PBhrK0UWwuGcCcovTUn9HTnsHbrhkWm659UrA/zpWP6D3D/SsjfTmjyKWMsE X-Received: by 2002:a05:622a:2595:b0:467:7472:7ac9 with SMTP id d75a77b69052e-467953465d4mr7797431cf.18.1733934383467; Wed, 11 Dec 2024 08:26:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934383; cv=none; d=google.com; s=arc-20240605; b=AQvMhnktOA/BRwUGDuQBP15KUaKNgquPeF0gS+SfeQB0r/wk3pIl7+Q6Dw7GSw/Lmo hiTUY+n/zoeXMx4bdqd6sCEs2xcgZlUelmu4M+wXdwUEa1WQBWem70G9a8yUm4bCAhaU g4SB848soG8ZC9PVaoWBDrlCtGpLLyXxJObkOZjdEOWZ7nGpmjGdmi44f3NPxA75u46w VpYSwbDC2UL02rHJZXSE2u1fGnkLldmWvlR4wcJC1jUu2d6yx7dr3WBznvE62RXFUZFI ayDCPGqTYI1WXmWpEMWqEPlqWFbGWXmHT8lBCslbgJGhPXGmDN3s0XvSQXmWFxBhBxz4 gbPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5+3C2AdZ9fftwrmxk/ig7qIyG/mfuZxKLEQCuOb4ibU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=k0fCnOnYBlmDpfNIR5QB7aA3OkI6alFsf5vE81D86yPKj/RYqwuLCfoHOXpaYUs5SJ dvjT5NUdEWRm5XLaE2v0zoKoMCsTOo+9KmaY65h5OulpA4cl1lnAON/ynbfZPGP1M8cz spXCbl6ioJ8cxULJNJNhmi9KFagJ0Lp1K63WA4RusLkjBQJjK7iRfmdBgDY7U2WV0h8v HJwJFzDwI3wdFJiD99bXf/k0OvfzF2kcjRmTr+n8lR+SRRsuVGUPKOJEsy/tRA1B27ft atd0rIndqZ/jNyXqq+/od722nq4RLwNr3LkS+hKLxPP11YbhMtnBcVSBj21nZfMHXiWF d3/w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FSY9KYZh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c Date: Wed, 11 Dec 2024 16:19:57 +0000 Message-Id: <20241211162004.2795499-66-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson This function is part of the public interface and is not "specialized" to any target in any way. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ fpu/softfloat-specialize.c.inc | 52 ---------------------------------- 2 files changed, 52 insertions(+), 52 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 027a8e576d3..6ba1cfd32a0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4920,6 +4920,58 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, *zExpPtr = 1 - shiftCount; } +/*---------------------------------------------------------------------------- +| Takes two extended double-precision floating-point values `a' and `b', one +| of which is a NaN, and returns the appropriate NaN result. If either `a' or +| `b' is a signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) +{ + bool aIsLargerSignificand; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); + + if (is_snan(a_cls) || is_snan(b_cls)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return floatx80_default_nan(status); + } + + if (a.low < b.low) { + aIsLargerSignificand = 0; + } else if (b.low < a.low) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; + } + + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { + if (is_snan(b_cls)) { + return floatx80_silence_nan(b, status); + } + return b; + } else { + if (is_snan(a_cls)) { + return floatx80_silence_nan(a, status); + } + return a; + } +} + /*---------------------------------------------------------------------------- | Takes an abstract floating-point value having sign `zSign', exponent `zExp', | and extended significand formed by the concatenation of `zSig0' and `zSig1', diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f26458eaa31..f7a320f6ff9 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -551,58 +551,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Takes two extended double-precision floating-point values `a' and `b', one -| of which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) -{ - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!floatx80_is_any_nan(a) - ? float_class_normal - : floatx80_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!floatx80_is_any_nan(b) - ? float_class_normal - : floatx80_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return floatx80_default_nan(status); - } - - if (a.low < b.low) { - aIsLargerSignificand = 0; - } else if (b.low < a.low) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return floatx80_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return floatx80_silence_nan(a, status); - } - return a; - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN Date: Wed, 11 Dec 2024 16:19:58 +0000 Message-Id: <20241211162004.2795499-67-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Unpacking and repacking the parts may be slightly more work than we did before, but we get to reuse more code. For a code path handling exceptional values, this is an improvement. Signed-off-by: Richard Henderson Message-id: 20241203203949.483774-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- fpu/softfloat.c | 43 +++++-------------------------------------- 1 file changed, 5 insertions(+), 38 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6ba1cfd32a0..8de8d5f3425 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4928,48 +4928,15 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; + FloatParts128 pa, pb, *pr; - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!floatx80_is_any_nan(a) - ? float_class_normal - : floatx80_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!floatx80_is_any_nan(b) - ? float_class_normal - : floatx80_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { return floatx80_default_nan(status); } - if (a.low < b.low) { - aIsLargerSignificand = 0; - } else if (b.low < a.low) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return floatx80_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return floatx80_silence_nan(a, status); - } - return a; - } + pr = parts_pick_nan(&pa, &pb, status); + return floatx80_round_pack_canonical(pr, status); } /*---------------------------------------------------------------------------- From patchwork Wed Dec 11 16:19:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849223 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp418307wry; Wed, 11 Dec 2024 08:29:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW+ZiwAyBbhuSBvRXxM9gOAfGsbcAxll0gs8fH4j0eyO0dCOevsjD8qAVegAW6nrY9SVwgkeA==@linaro.org X-Google-Smtp-Source: AGHT+IGmpN09SXzq54O1LN8rMklv2Jy/OrQE4jiOBA6x4PDcwBA0+HPs4AXkYnPqBzvuLDX4u8uJ X-Received: by 2002:a05:620a:86cc:b0:7b6:d350:9bfc with SMTP id af79cd13be357-7b6f1c0599dmr53521285a.27.1733934595570; Wed, 11 Dec 2024 08:29:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934595; cv=none; d=google.com; s=arc-20240605; b=aTbY90ouZ+A/2+MP49wubq/h0hnPmSMEoc+VXobfdy+rHwRZiScun00K3XbOllX5AB FBZP/ji/1MeKLCr8DtzFwpNJAegXUm67itv+WQkVt+EXX0LQ2E/dk/Rv23Da9LfkQ5+z 5WqnvPYwcXUA7kk7mMvCP7vS2XQ33vxre140XkH739zWnnjtT+/diSSi9kcaHpACiMqb H5yE996QCxLPqIeqfd3YhCIoAicGa+K5O5aG/ipsA1nsAnu08MAM5uwtcmKwJLtRjxhr z2iGySsBMVn3JZTAUCxYR7unNgSFBTtt9AFtBsThV3OwPML0hbGTF2HeuVgeuYNAcffG KXyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E0giBM/EpXvNpQdM8VbewBXwD4I1LGLbeL66q1YYWe8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FMzNQTIuwMAxqF9Med+bwIYZ0PuzWbkqsoWmTIL29OlyB3FnZkoYLP6UAi1zDln4a8 +5BuHn5hgBllKbpix4MUW4+1QeLM34oDXJVoZmvgPGIe+FBD5VCdtRkz8MUb2mQMOf9Y 7j//yapG+nqtDDOzmjnche6H8umsptecSt/ba96tF7SAGtm65rNLe/ewDIThB7qHHtSb UOyejx1GrhRDkrbB3v3TVdpvmx4pcw3odawJMZuoQmDREeVm0fLWa1SwNGfhaTVXN7wP bpemxWl+nv0+p3UMuCjsu3anYaKnUwYHkZqAT5PQ+NRJK/Xw7mjOJ66x+GRqzTCCLbFv OKIg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y2h58+qP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 67/72] softfloat: Inline pickNaN Date: Wed, 11 Dec 2024 16:19:59 +0000 Message-Id: <20241211162004.2795499-68-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Inline pickNaN into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- fpu/softfloat-specialize.c.inc | 96 ---------------------------------- 2 files changed, 73 insertions(+), 105 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 5fcdbc87fd7..a1b148e90b9 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -39,24 +39,88 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { + int cmp, which; + if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } if (s->default_nan_mode) { parts_default_nan(a, s); - } else { - int cmp = frac_cmp(a, b); - if (cmp == 0) { - cmp = a->sign < b->sign; - } + return a; + } - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { - a = b; - } + cmp = frac_cmp(a, b); + if (cmp == 0) { + cmp = a->sign < b->sign; + } + + switch (s->float_2nan_prop_rule) { + case float_2nan_prop_s_ab: if (is_snan(a->cls)) { - parts_silence_nan(a, s); + which = 0; + } else if (is_snan(b->cls)) { + which = 1; + } else if (is_qnan(a->cls)) { + which = 0; + } else { + which = 1; } + break; + case float_2nan_prop_s_ba: + if (is_snan(b->cls)) { + which = 1; + } else if (is_snan(a->cls)) { + which = 0; + } else if (is_qnan(b->cls)) { + which = 1; + } else { + which = 0; + } + break; + case float_2nan_prop_ab: + which = is_nan(a->cls) ? 0 : 1; + break; + case float_2nan_prop_ba: + which = is_nan(b->cls) ? 1 : 0; + break; + case float_2nan_prop_x87: + /* + * This implements x87 NaN propagation rules: + * SNaN + QNaN => return the QNaN + * two SNaNs => return the one with the larger significand, silenced + * two QNaNs => return the one with the larger significand + * SNaN and a non-NaN => return the SNaN, silenced + * QNaN and a non-NaN => return the QNaN + * + * If we get down to comparing significands and they are the same, + * return the NaN with the positive sign bit (if any). + */ + if (is_snan(a->cls)) { + if (is_snan(b->cls)) { + which = cmp > 0 ? 0 : 1; + } else { + which = is_qnan(b->cls) ? 1 : 0; + } + } else if (is_qnan(a->cls)) { + if (is_snan(b->cls) || !is_qnan(b->cls)) { + which = 0; + } else { + which = cmp > 0 ? 0 : 1; + } + } else { + which = 1; + } + break; + default: + g_assert_not_reached(); + } + + if (which) { + a = b; + } + if (is_snan(a->cls)) { + parts_silence_nan(a, s); } return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f7a320f6ff9..cbbbab52ba3 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -352,102 +352,6 @@ bool float32_is_signaling_nan(float32 a_, float_status *status) } } -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a two-input operation. -| IEEE754 doesn't specify all the details of this, so the -| algorithm is target-specific. -| The routine is passed various bits of information about the -| two NaNs and should return 0 to select NaN a and 1 for NaN b. -| Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_silence_nan() before -| returning them. -| -| aIsLargerSignificand is only valid if both a and b are NaNs -| of some kind, and is true if a has the larger significand, -| or if both a and b have the same significand but a is -| positive but b is negative. It is only needed for the x87 -| tie-break rule. -*----------------------------------------------------------------------------*/ - -static int pickNaN(FloatClass a_cls, FloatClass b_cls, - bool aIsLargerSignificand, float_status *status) -{ - /* - * We guarantee not to require the target to tell us how to - * pick a NaN if we're always returning the default NaN. - * But if we're not in default-NaN mode then the target must - * specify via set_float_2nan_prop_rule(). - */ - assert(!status->default_nan_mode); - - switch (status->float_2nan_prop_rule) { - case float_2nan_prop_s_ab: - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - break; - case float_2nan_prop_s_ba: - if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } - break; - case float_2nan_prop_ab: - if (is_nan(a_cls)) { - return 0; - } else { - return 1; - } - break; - case float_2nan_prop_ba: - if (is_nan(b_cls)) { - return 1; - } else { - return 0; - } - break; - case float_2nan_prop_x87: - /* - * This implements x87 NaN propagation rules: - * SNaN + QNaN => return the QNaN - * two SNaNs => return the one with the larger significand, silenced - * two QNaNs => return the one with the larger significand - * SNaN and a non-NaN => return the SNaN, silenced - * QNaN and a non-NaN => return the QNaN - * - * If we get down to comparing significands and they are the same, - * return the NaN with the positive sign bit (if any). - */ - if (is_snan(a_cls)) { - if (is_snan(b_cls)) { - return aIsLargerSignificand ? 0 : 1; - } - return is_qnan(b_cls) ? 1 : 0; - } else if (is_qnan(a_cls)) { - if (is_snan(b_cls) || !is_qnan(b_cls)) { - return 0; - } else { - return aIsLargerSignificand ? 0 : 1; - } - } else { - return 1; - } - default: - g_assert_not_reached(); - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 68/72] softfloat: Share code between parts_pick_nan cases Date: Wed, 11 Dec 2024 16:20:00 +0000 Message-Id: <20241211162004.2795499-69-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Remember if there was an SNaN, and use that to simplify float_2nan_prop_s_{ab,ba} to only the snan component. Then, fall through to the corresponding float_2nan_prop_{ab,ba} case to handle any remaining nans, which must be quiet. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a1b148e90b9..3c77dcbb154 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -39,10 +39,12 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { + bool have_snan = false; int cmp, which; if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); + have_snan = true; } if (s->default_nan_mode) { @@ -57,30 +59,20 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: - if (is_snan(a->cls)) { - which = 0; - } else if (is_snan(b->cls)) { - which = 1; - } else if (is_qnan(a->cls)) { - which = 0; - } else { - which = 1; + if (have_snan) { + which = is_snan(a->cls) ? 0 : 1; + break; } - break; - case float_2nan_prop_s_ba: - if (is_snan(b->cls)) { - which = 1; - } else if (is_snan(a->cls)) { - which = 0; - } else if (is_qnan(b->cls)) { - which = 1; - } else { - which = 0; - } - break; + /* fall through */ case float_2nan_prop_ab: which = is_nan(a->cls) ? 0 : 1; break; + case float_2nan_prop_s_ba: + if (have_snan) { + which = is_snan(b->cls) ? 1 : 0; + break; + } + /* fall through */ case float_2nan_prop_ba: which = is_nan(b->cls) ? 1 : 0; break; From patchwork Wed Dec 11 16:20:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849206 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp416858wry; Wed, 11 Dec 2024 08:27:00 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXoWfchMM4eLkCXRX53awog/CDxWmC4iCEwofBy+Fa+UdIYJL5hmAG0XuWN5lVv491gL9Qhmg==@linaro.org X-Google-Smtp-Source: AGHT+IFcCgS/Ij6MGwGxx5EuJw3bBoGJZ+NdNw/Zf+I0tdUOnYOicW3qQixBbbhD60USk4txo06o X-Received: by 2002:a05:6214:21c4:b0:6d8:a50f:b5f6 with SMTP id 6a1803df08f44-6d934b2ce8bmr77187346d6.25.1733934420320; Wed, 11 Dec 2024 08:27:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934420; cv=none; d=google.com; s=arc-20240605; b=ii/kWoVTWCuH+zThKh6+fV0KkhBwK6MDebaDd9FuQ80UW+ht3xlI1o7BQrXlWQmKrs OmaTSoZpyx8ufeXbva/aHkQXM+axZZdibk/+m1w7xJbVlSzL1Rfx7+EorcnHJBgSnmMp G905/HaKAUARLstll9f8vqkPDeQvoFh5e+nQQNR9KxYXpbmPwc6BHNtkFp5J1ZUQDEll hEq1hrN8O4J1xN8odQ0vQf1OkrBq7bSFwdpd5P4jARsGnQgehlPCvAPJU0C5hfbx6ogg 8HqVkVcONOjMHqp4mh/KiOFr4DuRFlmHqtKGs7zGu7M84ULD2CoEB6gIFJ6Xj7UphGhC dAvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=doRTkzLWp9CB3fDTzYDP5bn9+hyyRKBZGVgyCVKSal4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=cPq5IoF8Ic0M/c6I8AKePZbeToMGai9ZClmh1BfTRvqxOz7RW5KqdKIW+xAsJJX+SV t0U/WajYfn8XxeysWpUIUDBWpU/5+nVotbjSoZWKk9Pay6lVWluCjmY/CDVXckAww4Qw JCV4m3rFrWwzEtMS4bWngTEMV6fhSNz+u/JwwyuEjA1jC1uy00ztPNtMr6EbY9MEcD/p ywyD6o9XjRD3jhSuWpetQU7kmYgB/b6JUO1KSP8p27+xavLnaWWQejmbB4qLtcIdS+0C rUMu+wJ8faSJ0yxSHWSmx3wMV9I9kruC7IKzJkJUHwbC0ph/dETZg0v/DjX5RUgEahsk okRQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sBH+xyer; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed Date: Wed, 11 Dec 2024 16:20:01 +0000 Message-Id: <20241211162004.2795499-70-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Move the fractional comparison to the end of the float_2nan_prop_x87 case. This is not required for any other 2nan propagation rule. Reorganize the x87 case itself to break out of the switch when the fractional comparison is not required. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3c77dcbb154..abe24aeaa00 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -52,11 +52,6 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, return a; } - cmp = frac_cmp(a, b); - if (cmp == 0) { - cmp = a->sign < b->sign; - } - switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: if (have_snan) { @@ -89,20 +84,24 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, * return the NaN with the positive sign bit (if any). */ if (is_snan(a->cls)) { - if (is_snan(b->cls)) { - which = cmp > 0 ? 0 : 1; - } else { + if (!is_snan(b->cls)) { which = is_qnan(b->cls) ? 1 : 0; + break; } } else if (is_qnan(a->cls)) { if (is_snan(b->cls) || !is_qnan(b->cls)) { which = 0; - } else { - which = cmp > 0 ? 0 : 1; + break; } } else { which = 1; + break; } + cmp = frac_cmp(a, b); + if (cmp == 0) { + cmp = a->sign < b->sign; + } + which = cmp > 0 ? 0 : 1; break; default: g_assert_not_reached(); From patchwork Wed Dec 11 16:20:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849176 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp415315wry; Wed, 11 Dec 2024 08:24:11 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUWPATbejNKwGxQ+uPQGnjkVpb+R/dOqAnk9Yzr90GlnIGEuU6szI5K0wIMocOMf5ZwMWni4Q==@linaro.org X-Google-Smtp-Source: AGHT+IE9uRReoVM4iD3HZiwSAm+AXr5JTVF+wHeEyKXH7QHp6JSy9/F4qFmINLM4HO8y9CtYkaAU X-Received: by 2002:a05:620a:2402:b0:7b6:d241:3f0b with SMTP id af79cd13be357-7b6ebc5e2a4mr536208485a.14.1733934251359; Wed, 11 Dec 2024 08:24:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934251; cv=none; d=google.com; s=arc-20240605; b=B0nruW2i0A57Bu2wAJDZb4aH9znarNxElotaEtI9J7Tr/glsq21Wc9WAQXKBpbxnnu QunHdLn+6SgvgbP6KmxhbnuwcVqPxQ62yIn54BUdJs83tmQwTJAZJCUPL6unmDydM1Ih w1WDs9kidOsnMzDYaCC733OY+IEuvUHo9AtmzgWXX9Xkb3RKcLFejuJMnEDZbo88s6h7 Db8z6qWm2F03Th48lZwX/dhZSLkHHFJ6XImhSRA1CgHQi8yZnDP1t1QMNz0RkJ4t1u4r H4RQP/ZuzwbaiCrFRl0xEGYXAUAf7tPNUWShHExB53NLl6SXXhOZKH80RBimVoXQ5btg QeCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E85lj8XRhj/Fk3RQPB/aLYeRqkABA8VMdndxVbT9joA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=EqHPK3YBbDL9lRgBk4lE3ce0ahkorgsRnCYg6rEQBs5oeNgftnnhTf1EP/8fcfP1K1 qMR4KoA/QlXJeRoMRWUj8jcRZHxNs1m1ujp/7Sv2MCjPf7KDsvWloeI/eqs2JWdPuLpI s3B7PsiHfnZXBUjyzrZxxyLfY5HSLfBW9yhiXwX/oRodA7HFO8OOB86ZRvnLmBYLRU97 IyBCjDrV6ILHmn4IzfgVaoHWtO4mmko+NPs3U0lyJuQkwm9RnnWRqLKYem7eVyzt+mbr ItsJZV5Kip8rMAMMghY41pu6c12Q0ADzlRXfYbvvTq5IIkPIEeDsgH/16bRtGaaHq/DV XgyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="mqD6/oj+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan Date: Wed, 11 Dec 2024 16:20:02 +0000 Message-Id: <20241211162004.2795499-71-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Replace the "index" selecting between A and B with a result variable of the proper type. This improves clarity within the function. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index abe24aeaa00..ba8de7be76e 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -40,7 +40,8 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { bool have_snan = false; - int cmp, which; + FloatPartsN *ret; + int cmp; if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); @@ -55,21 +56,21 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: if (have_snan) { - which = is_snan(a->cls) ? 0 : 1; + ret = is_snan(a->cls) ? a : b; break; } /* fall through */ case float_2nan_prop_ab: - which = is_nan(a->cls) ? 0 : 1; + ret = is_nan(a->cls) ? a : b; break; case float_2nan_prop_s_ba: if (have_snan) { - which = is_snan(b->cls) ? 1 : 0; + ret = is_snan(b->cls) ? b : a; break; } /* fall through */ case float_2nan_prop_ba: - which = is_nan(b->cls) ? 1 : 0; + ret = is_nan(b->cls) ? b : a; break; case float_2nan_prop_x87: /* @@ -85,35 +86,32 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, */ if (is_snan(a->cls)) { if (!is_snan(b->cls)) { - which = is_qnan(b->cls) ? 1 : 0; + ret = is_qnan(b->cls) ? b : a; break; } } else if (is_qnan(a->cls)) { if (is_snan(b->cls) || !is_qnan(b->cls)) { - which = 0; + ret = a; break; } } else { - which = 1; + ret = b; break; } cmp = frac_cmp(a, b); if (cmp == 0) { cmp = a->sign < b->sign; } - which = cmp > 0 ? 0 : 1; + ret = cmp > 0 ? a : b; break; default: g_assert_not_reached(); } - if (which) { - a = b; + if (is_snan(ret->cls)) { + parts_silence_nan(ret, s); } - if (is_snan(a->cls)) { - parts_silence_nan(a, s); - } - return a; + return ret; } static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, From patchwork Wed Dec 11 16:20:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849216 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417266wry; Wed, 11 Dec 2024 08:27:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVg2nQdgJ8W3SKn3SJ/tmAhMAxkApnitIEHnNz3zPvHVXbZCtonKkEwG4OWaFM5aCZBgmCXrg==@linaro.org X-Google-Smtp-Source: AGHT+IENBudgEL4OgTH4XMisFsxOIpDr4+MGGAkCrzERYBKg8KeOu9Sb9wmZ80mRwZcYnR2evccL X-Received: by 2002:a05:620a:1729:b0:7b6:6ee8:6c06 with SMTP id af79cd13be357-7b6eb48f613mr602324085a.30.1733934466887; Wed, 11 Dec 2024 08:27:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934466; cv=none; d=google.com; s=arc-20240605; b=a0Am7vTTF+YiJpDtvenJEpDinb1+M9NFyXkLO16f05ZueIw1l+HmtRDfHiEF9Nxm/J r8onPiqazxXeavmoQnpFyAra21VoUEdvrvKoYx52ijnQVDYoeIkYkfWz6bnObeHoZsax TOMOoiiFnu/oO1J8p9H3nEbR1E0S6OhE0DI9x8HA4mbhbd9g0KkNEHEml+2GHkTGf5Ab uYCPda0C7jDZnx2/E4nr1JtAkpfmdEysAB30Mh+fZL4EBA7dRdcIlqfGPcoSV6JB7HlN Ej5e7JOU86dbcsBwQwfA75qwIbd8KOqbBPZhfKExo2DrE+0nMThKrVAVp5MNKALfL8YZ m1Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gSbZ33dYhUCvriB7gJIYOSjh0uJ7qwYxR0y7su+tpkc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=KjDdvMUXudjmGagQtIQL66xnMcyWcx/XOUgtUltSB7IgDwH876onkAV3azjKlYaxdH uTOLWWgFjcYoxjFCIOSG3ZzSEJMSv48CtcVdrX+r/U9kNYYuMNmvihrpFFTjkN/d1Ly7 rpqjE89XIoEYWAnFDx3nmvIq7LQK6Y4BfUlXSCv20cpbNgRJyB1Q57j8tTjLD9WcpXKe /wWWkT8YV5gfzORGdNb9xqppJHZ/j+k6Q64ZZ14xVZUftmQ8HQymUBwNicifuBq0aM6h zYWvk0lQHk1neYsyL2ZhGhAhxGQCd5m0mj0qZy6FmBfqxHnvrQCB8E3NTzj8CDpbCxXh hmOw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="KRE/1KwI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 71/72] MAINTAINERS: update email address for Leif Lindholm Date: Wed, 11 Dec 2024 16:20:03 +0000 Message-Id: <20241211162004.2795499-72-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Leif Lindholm I'm migrating to Qualcomm's new open source email infrastructure, so update my email address, and update the mailmap to match. Signed-off-by: Leif Lindholm Reviewed-by: Leif Lindholm Reviewed-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com Signed-off-by: Peter Maydell --- MAINTAINERS | 2 +- .mailmap | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index aaf0505a214..9ae6a78ae9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -915,7 +915,7 @@ F: include/hw/ssi/imx_spi.h SBSA-REF M: Radoslaw Biernacki M: Peter Maydell -R: Leif Lindholm +R: Leif Lindholm R: Marcin Juszkiewicz L: qemu-arm@nongnu.org S: Maintained diff --git a/.mailmap b/.mailmap index 727ce204b2d..5f6df414e1f 100644 --- a/.mailmap +++ b/.mailmap @@ -87,8 +87,9 @@ Huacai Chen Huacai Chen James Hogan Juan Quintela -Leif Lindholm -Leif Lindholm +Leif Lindholm +Leif Lindholm +Leif Lindholm Luc Michel Luc Michel Luc Michel From patchwork Wed Dec 11 16:20:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 849219 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp417386wry; Wed, 11 Dec 2024 08:28:02 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW2e0Zo61RBvkg540iqFrKS6KRPTMCno6Ux4hxDukv7e7mhojkB4ChdD0q7x933bTi8dVEGCw==@linaro.org X-Google-Smtp-Source: AGHT+IFDurIxoVJiLxYtF8hyEacbt/X9lzjup6v6o2DB9jQiKSUpIpyQJOag0/dCk0xDN115xaK9 X-Received: by 2002:ac8:5ad5:0:b0:466:a824:751c with SMTP id d75a77b69052e-4678936d23dmr50115971cf.29.1733934482700; Wed, 11 Dec 2024 08:28:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733934482; cv=none; d=google.com; s=arc-20240605; b=askQwfXl8lZavOOxuTxMAY7V8Bc8OUQYhcxVMaAzNhzoDglcFULmbfOmyQWO4VRQaI oGMVH8mCybTDZajeN1tB6NF6ZifO10N1uL2rmha8mH6HBRvQituoYYqtZCAJgYSap+4X Gxi5b30y8EwTHHoEwFAruySJ3gnMOAwoyIxMMC+/BYKdlYRXMUbY1XNsMYxTA6IRqWcq i4qEr5kMaSNjsSX3u0HpsisMncsWjj9XTKe7EY4SWq92IUNiIyklkRkfkh07lclUG+yv yfKSrrI1fYn9sh26v+lH5Exachxa9rrD4cnyiE4h+oSgc2GXC/KwlWjdbAUIrhG4elEQ vSzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ht1nZ84ts/9AMVIYYfAfz6P7yX4A1c2tCexcQoTh5N4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=HB02MN0N3wh7NKOd9RHNe4UEdE8uEqR9I1Nskj9ml3SWj84fr3Kka8XtSxRqv4jqXm FaKSxTsrayxM9mQPw0wSprh2S0WJS4uVhhPYCPWieFBbVz1rie7BDNpNLCzrmEvhU62S ww+3GEtc8tGuY1JVVSr+hB4Yg6seSzP9me4sUUoEdqkl5dP9wmGeqlSAeghSJg9+gKKh EnxrEP/Quy19n1b6ftjyyk9ZWZFOSrGvO5nWpA0NzKpqOEdBLjI5bAo2lzxZ1+JynqVB mJT3D09S/FQn2EK7y1o/3ZAB594tvkyKD1FysR9O8ZwlsZULz/N3mZz3R4JxIkdjfl62 8n4g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aZMCrW3s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal Date: Wed, 11 Dec 2024 16:20:04 +0000 Message-Id: <20241211162004.2795499-73-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vikram Garhwal Previously, maintainer role was paused due to inactive email id. Commit id: c009d715721861984c4987bcc78b7ee183e86d75. Signed-off-by: Vikram Garhwal Reviewed-by: Francisco Iglesias Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com Signed-off-by: Peter Maydell --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9ae6a78ae9c..1d2003a9a1d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1914,6 +1914,7 @@ F: tests/qtest/fuzz-sb16-test.c Xilinx CAN M: Francisco Iglesias +M: Vikram Garhwal S: Maintained F: hw/net/can/xlnx-* F: include/hw/net/xlnx-* @@ -2673,6 +2674,7 @@ F: include/hw/rx/ CAN bus subsystem and hardware M: Pavel Pisa M: Francisco Iglesias +M: Vikram Garhwal S: Maintained W: https://canbus.pages.fel.cvut.cz/ F: net/can/*