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[34.38.134.32]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38782514d35sm4462941f8f.74.2024.12.12.08.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2024 08:00:48 -0800 (PST) From: Tudor Ambarus Date: Thu, 12 Dec 2024 16:00:38 +0000 Subject: [PATCH v2 1/4] arm64: dts: exynos: gs101: add SRAM node Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241212-b4-acpm-v4-upstream-dts-v2-1-91b7a6f6d0b0@linaro.org> References: <20241212-b4-acpm-v4-upstream-dts-v2-0-91b7a6f6d0b0@linaro.org> In-Reply-To: <20241212-b4-acpm-v4-upstream-dts-v2-0-91b7a6f6d0b0@linaro.org> To: Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, peter.griffin@linaro.org, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734019247; l=979; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=g9Y6c/Lu4XdnwvVgrnVv9tKSFGDPtKMBC9QqU0RCKUw=; b=pe7nkbrj20qSYnrPkOzt+GqPA7lDUyR+IOiNPFAd4WlYXzbH8ZVMKRBtJ2AJ6BEWj54kNiXY8 XhWrSTkps7uBOgZLxbruYT2X/DmIRHZ7qF4C+mnzBjagKE9cPO7q4Im X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= SRAM is used by the ACPM protocol to retrieve the ACPM channels information, which includes the TX/RX rings among other channel configuration data. Add the SRAM node. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 302c5beb224a..1441e9a252c2 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -269,6 +269,14 @@ bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { }; }; + apm_sram: sram@2039000 { + compatible = "mmio-sram"; + reg = <0x0 0x2039000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2039000 0x40000>; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; From patchwork Thu Dec 12 16:00:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 849949 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A8F8229690 for ; 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[34.38.134.32]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38782514d35sm4462941f8f.74.2024.12.12.08.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2024 08:00:49 -0800 (PST) From: Tudor Ambarus Date: Thu, 12 Dec 2024 16:00:39 +0000 Subject: [PATCH v2 2/4] arm64: dts: exynos: gs101: add AP to APM mailbox node Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241212-b4-acpm-v4-upstream-dts-v2-2-91b7a6f6d0b0@linaro.org> References: <20241212-b4-acpm-v4-upstream-dts-v2-0-91b7a6f6d0b0@linaro.org> In-Reply-To: <20241212-b4-acpm-v4-upstream-dts-v2-0-91b7a6f6d0b0@linaro.org> To: Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, peter.griffin@linaro.org, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734019247; l=1282; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=ce1gfVKuhMWygYDqna0xFI3vmpwGiIISm4wS0eqE5Rg=; b=yKRS1dg8qQ9WdVmW4a6Zg6eAYV4MUjEMRK91aEUmMZbQw2ZHkn5kV9WpTw9VlRF1IDm6DHmUE SXlDqjTvmLxBx4qsFucA34eNpV9XbiYQVPyNFTyq1FYbsLz6NiLkKWg X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= GS101 has 14 mailbox controllers. Add the AP to APM mailbox node. Mailbox controllers have a shared register that can be used for passing the mailbox messages. The AP to APM mailbox controller is used just as a doorbell mechanism. It raises interrupt to the firmware after the mailbox message has been written to SRAM where the TX/RX rings are defined. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 1441e9a252c2..04561e15b96c 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1445,6 +1445,15 @@ wakeup-interrupt-controller { }; }; + ap2apm_mailbox: mailbox@17610000 { + compatible = "google,gs101-mbox"; + reg = <0x17610000 0x1000>; + clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; + clock-names = "pclk"; + interrupts = ; + #mbox-cells = <2>; + }; + pinctrl_gsactrl: pinctrl@17940000 { compatible = "google,gs101-pinctrl"; reg = <0x17940000 0x00001000>;