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Tue, 17 Dec 2024 07:32:52 -0800 From: Prathamesh Shete To: , , , , , , , Subject: [PATCH v2] pinctrl-tegra: Add config property GPIO mode Date: Tue, 17 Dec 2024 21:02:49 +0530 Message-ID: <20241217153249.5712-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|SJ1PR12MB6266:EE_ X-MS-Office365-Filtering-Correlation-Id: dee695ac-4371-45d0-1c80-08dd1eb0217a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: 1QH6fQKRs4NJ57x8ffrtnqaAF2xgPeJJ+qa3/FPW7G/Lk0iqsCNiYj/XxATfjPuF+DUVMfwhDcFt/8WHsn83nkYmwCMOD50JrJf2REb1hg3UOLnZNakRYyWfAYRXym2hAFRCD7fX6OWJk6NFsIZZXH7nG78EPCAva/hkBSAri7veo/uPOzYpZ3HO2/plGvcGxSpBVJo3hmZ75PTW207/yHixzZFX1A+UvrBsOURxC6uVY7ZajNQ25DUKGk8PTdQLC0iAsJN05hCmGFCZjJcu1Z+1fy2pWcDuOeoccpN18iffUWkHGzLOjN13JPZo78ZKMQ74R4pr8BzJj5qqzopQ8uqn/8RcgqAQGwhHCNL/3ylMBwGvj5+pIpImgb+xiwtAWuBRPSAn7eCQH8KrfmBtQRUhNU2+9T2yGKEItcleZezcR2xGdCzOfnKF8IGghlJU6cH166dNhUoqJuKrqz9VGHRTEVYMuBESpKLTivr95M+64OTAl9bUeXFk5Tv/mQ0tL1fLYPY6qMiY0dkpS5DrFYJ7I7NP90dJKF9RNsUZrD1NHNjIdVpTlJYTDx4eGE0ce7sdDc8FWfVtQP1KGa3KzL3K+3KDcoCtvf6LirhaxarY41WoB+xLPReABSq0GKlcF0vT4QkWvUT0E+bXuC7CC/8Tzq9TuhUMNnHDzNViZdQfukgUxHJrEstjF01007HprBg+OW9/ltVN77GXQolW7KMzsPAksIwQs7AIY2GfrxavWDG7AdXowA9L5bM8DPubwhbKYzq/bnsQ/QvCVfCnqlWtoBmLkxaHm3C32xmVtprkdUe5mB5ex9jYy2aDDSrZpjoCa+aE9XTw3s8ue8ruS18dwknj/ZtMhXCYcn0SCO7qAby9dkSNfghaJIf8NsDyK0YNrv7+iE/lwyXL0VJcbZI1Fd5L1YliU2MeZVfartRPbzmo9You8newuqLxJawJCV6/a4OZJCOOyVAlCooTjcGQMv0w0B2bKyCvKEYVqLotTSsgG4to8DQKX3HXJI+okpC+vPV8A5oysH/jA0SqkhR24BES0w+mH+VUJowmHZdBXM04nJqWaC0K/I8OcQ60WFH1Pv+XgpT8Ur4t8otyFYqDhhhEJ36inFaDx9jYqeSbslO15u+HYYwB1ZRWByr+u9J8A2h5jkzHqhnQ33hKxrQnvcN87PSpb54bN28mPBHs8J6vs00Tnmy7j5t7IGZqVHpa13oC9eT4gA2W0EsP9RfB9+VA/jgywiEebVpBXaU1LJio+NRt38NwU0Vzf0tnDIt57mwAiyreNaBZa7DV9lhSCirNojVnHarTTUfEvuMg41E+mWT7R4msGnU3SBe54iRvVXpS1F5Zq4gQ6SoLMEws0ntMML2Y85f/C35y7m204yey5YQZT2MoWCUAwDCmmTffbUNFGh9yPY/+lnjHMk7G+5GEw15afjPx/ZGlQhQf7HKhTQ/rV7vhREAAU9T984kRTPi6wKzDOtuRQNetpwLrqV6uLXVBmsH9/Q51tb4= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2024 15:33:17.9644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dee695ac-4371-45d0-1c80-08dd1eb0217a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6266 The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing system: - When set to 1, the pin operates in SFIO mode, controlled by the pin's assigned special function. - When set to 0, the pin operates as a general-purpose GPIO. This SFIO/GPIO select bit that is set for a given pin is not displayed, adding the support to retrieve this information from the pinmux set for each pin. Signed-off-by: Prathamesh Shete --- drivers/pinctrl/tegra/pinctrl-tegra.c | 11 +++++++++++ drivers/pinctrl/tegra/pinctrl-tegra.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 9523b93008d0..46728f19fa8e 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -96,6 +96,7 @@ static const struct cfg_param { {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, + {"nvidia,gpio-mode", TEGRA_PINCONF_PARAM_GPIO_MODE}, }; static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, @@ -476,6 +477,16 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *bit = g->drvtype_bit; *width = 2; break; + case TEGRA_PINCONF_PARAM_GPIO_MODE: + if (pmx->soc->sfsel_in_mux) { + *bank = g->mux_bank; + *reg = g->mux_reg; + *bit = g->sfsel_bit; + *width = 1; + } else { + *reg = -EINVAL; + } + break; default: dev_err(pmx->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index b97136685f7a..a47ac519f3ec 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -60,6 +60,8 @@ enum tegra_pinconf_param { TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, /* argument: Integer, range is HW-dependant */ TEGRA_PINCONF_PARAM_DRIVE_TYPE, + /* argument: Boolean */ + TEGRA_PINCONF_PARAM_GPIO_MODE, }; enum tegra_pinconf_pull {