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([94.131.202.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c4fcsm522807895e9.29.2025.01.04.08.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jan 2025 08:29:18 -0800 (PST) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sam Protsenko Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: soc: samsung: exynos-sysreg: add sysreg compatibles for exynos8895 Date: Sat, 4 Jan 2025 18:29:13 +0200 Message-ID: <20250104162915.332005-2-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250104162915.332005-1-ivo.ivanov.ivanov1@gmail.com> References: <20250104162915.332005-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Exynos8895 has four different SYSREG controllers, add dedicated compatibles for them to the documentation. They also require clocks. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 3ca220582..a75aef240 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -21,6 +21,10 @@ properties: - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg + - samsung,exynos8895-fsys0-sysreg + - samsung,exynos8895-fsys1-sysreg + - samsung,exynos8895-peric0-sysreg + - samsung,exynos8895-peric1-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg - tesla,fsd-cam-sysreg @@ -79,6 +83,10 @@ allOf: - samsung,exynos850-cmgp-sysreg - samsung,exynos850-peri-sysreg - samsung,exynos850-sysreg + - samsung,exynos8895-fsys0-sysreg + - samsung,exynos8895-fsys1-sysreg + - samsung,exynos8895-peric0-sysreg + - samsung,exynos8895-peric1-sysreg then: required: - clocks From patchwork Sat Jan 4 16:29:14 2025 Content-Type: text/plain; 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([94.131.202.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c4fcsm522807895e9.29.2025.01.04.08.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jan 2025 08:29:20 -0800 (PST) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sam Protsenko Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi Date: Sat, 4 Jan 2025 18:29:14 +0200 Message-ID: <20250104162915.332005-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250104162915.332005-1-ivo.ivanov.ivanov1@gmail.com> References: <20250104162915.332005-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add constants for choosing USIv1 configuration mode in device tree. Those are further used in the USI driver to figure out which value to write into SW_CONF register. Modify the current USI IP-core bindings to include information about USIv1 and a compatible for exynos8895. Signed-off-by: Ivaylo Ivanov --- .../bindings/soc/samsung/exynos-usi.yaml | 55 +++++++++++++++---- include/dt-bindings/soc/samsung,exynos-usi.h | 7 +++ 2 files changed, 50 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 5b046932f..6e32daa45 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -11,11 +11,21 @@ maintainers: - Krzysztof Kozlowski description: | - USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). - USI shares almost all internal circuits within each protocol, so only one - protocol can be chosen at a time. USI is modeled as a node with zero or more - child nodes, each representing a serial sub-node device. The mode setting - selects which particular function will be used. + The USI IP-core provides configurable support for serial protocols, enabling + different serial communication modes depending on the version. + + In USIv1, configurations are available to enable either one or two protocols + simultaneously in select combinations - High-Speed I2C0, High-Speed + I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed + I2C1 and UART. + + In USIv2, only one protocol can be active at a time, either UART, SPI, or + High-Speed I2C. + + The USI core shares internal circuits across protocols, meaning only the + selected configuration is active at any given time. USI is modeled as a node + with zero or more child nodes, each representing a serial sub-node device. The + mode setting selects which particular function will be used. properties: $nodename: @@ -31,6 +41,7 @@ properties: - const: samsung,exynos850-usi - enum: - samsung,exynos850-usi + - samsung,exynos8895-usi reg: maxItems: 1 @@ -64,7 +75,6 @@ properties: samsung,mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] description: Selects USI function (which serial protocol to use). Refer to for valid USI mode values. @@ -101,18 +111,42 @@ required: - samsung,sysreg - samsung,mode +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-usi + then: + properties: + reg: + maxItems: 1 + + samsung,mode: + enum: [0, 1, 2, 3] + + required: + - reg + + else: + properties: + reg: false + samsung,clkreq-on: false + + samsung,mode: + enum: [4, 5, 6, 7, 8, 9, 10] + if: properties: compatible: contains: enum: - samsung,exynos850-usi + - samsung,exynos8895-usi then: properties: - reg: - maxItems: 1 - clocks: items: - description: Bus (APB) clock @@ -122,16 +156,13 @@ then: maxItems: 2 required: - - reg - clocks - clock-names else: properties: - reg: false clocks: false clock-names: false - samsung,clkreq-on: false additionalProperties: false diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h index a01af169d..4c077c9a8 100644 --- a/include/dt-bindings/soc/samsung,exynos-usi.h +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -13,5 +13,12 @@ #define USI_V2_UART 1 #define USI_V2_SPI 2 #define USI_V2_I2C 3 +#define USI_V1_NONE 4 +#define USI_V1_I2C0 5 +#define USI_V1_I2C1 6 +#define USI_V1_I2C0_1 7 +#define USI_V1_SPI 8 +#define USI_V1_UART 9 +#define USI_V1_UART_I2C1 10 #endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ From patchwork Sat Jan 4 16:29:15 2025 Content-Type: text/plain; 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([94.131.202.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c4fcsm522807895e9.29.2025.01.04.08.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jan 2025 08:29:22 -0800 (PST) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Sam Protsenko Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] soc: samsung: usi: implement support for USIv1 Date: Sat, 4 Jan 2025 18:29:15 +0200 Message-ID: <20250104162915.332005-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250104162915.332005-1-ivo.ivanov.ivanov1@gmail.com> References: <20250104162915.332005-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 USIv1 IP-core is found on some ARM64 Exynos SoCs (like Exynos8895) and provides selectable serial protocols (one of: HSI2C0, HSI2C1, HSI2C0_1, SPI, UART, UART_HSI2C1). USIv1, unlike USIv2, doesn't have any known register map. Underlying protocols that it implements have no offset, like with Exynos850. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. In order to select a particular protocol, the protocol has to be selected via the System Register. Unlike USIv2, there's no need for any setup before the given protocol becomes accessible apart from enabling the APB clock and the protocol operating clock. Modify the existing driver in order to allow USIv1 to probe and set its protocol. Signed-off-by: Ivaylo Ivanov --- drivers/soc/samsung/exynos-usi.c | 42 +++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c index 114352695..e57d2c274 100644 --- a/drivers/soc/samsung/exynos-usi.c +++ b/drivers/soc/samsung/exynos-usi.c @@ -16,6 +16,18 @@ #include +/* USIv1: System Register: SW_CONF register bits */ +#define USI_V1_SW_CONF_NONE 0x0 +#define USI_V1_SW_CONF_I2C0 0x1 +#define USI_V1_SW_CONF_I2C1 0x2 +#define USI_V1_SW_CONF_I2C0_1 0x3 +#define USI_V1_SW_CONF_SPI 0x4 +#define USI_V1_SW_CONF_UART 0x8 +#define USI_V1_SW_CONF_UART_I2C1 0xa +#define USI_V1_SW_CONF_MASK (USI_V1_SW_CONF_I2C0 | USI_V1_SW_CONF_I2C1 | \ + USI_V1_SW_CONF_I2C0_1 | USI_V1_SW_CONF_SPI | \ + USI_V1_SW_CONF_UART | USI_V1_SW_CONF_UART_I2C1) + /* USIv2: System Register: SW_CONF register bits */ #define USI_V2_SW_CONF_NONE 0x0 #define USI_V2_SW_CONF_UART BIT(0) @@ -34,7 +46,8 @@ #define USI_OPTION_CLKSTOP_ON BIT(2) enum exynos_usi_ver { - USI_VER2 = 2, + USI_VER1 = 1, + USI_VER2, }; struct exynos_usi_variant { @@ -71,6 +84,13 @@ static const struct exynos_usi_mode exynos_usi_modes[] = { [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, + [USI_V1_NONE] = { .name = "none", .val = USI_V1_SW_CONF_NONE }, + [USI_V1_I2C0] = { .name = "i2c0", .val = USI_V1_SW_CONF_I2C0 }, + [USI_V1_I2C1] = { .name = "i2c1", .val = USI_V1_SW_CONF_I2C1 }, + [USI_V1_I2C0_1] = { .name = "i2c0_1", .val = USI_V1_SW_CONF_I2C0_1 }, + [USI_V1_SPI] = { .name = "spi", .val = USI_V1_SW_CONF_SPI }, + [USI_V1_UART] = { .name = "uart", .val = USI_V1_SW_CONF_UART }, + [USI_V1_UART_I2C1] = { .name = "uart_i2c1", .val = USI_V1_SW_CONF_UART_I2C1 }, }; static const char * const exynos850_usi_clk_names[] = { "pclk", "ipclk" }; @@ -83,11 +103,24 @@ static const struct exynos_usi_variant exynos850_usi_data = { .clk_names = exynos850_usi_clk_names, }; +static const struct exynos_usi_variant exynos8895_usi_data = { + .ver = USI_VER1, + .sw_conf_mask = USI_V1_SW_CONF_MASK, + .min_mode = USI_V1_NONE, + .max_mode = USI_V1_UART_I2C1, + .num_clks = ARRAY_SIZE(exynos850_usi_clk_names), + .clk_names = exynos850_usi_clk_names, +}; + static const struct of_device_id exynos_usi_dt_match[] = { { .compatible = "samsung,exynos850-usi", .data = &exynos850_usi_data, }, + { + .compatible = "samsung,exynos8895-usi", + .data = &exynos8895_usi_data, + }, { } /* sentinel */ }; MODULE_DEVICE_TABLE(of, exynos_usi_dt_match); @@ -169,9 +202,12 @@ static int exynos_usi_configure(struct exynos_usi *usi) return ret; if (usi->data->ver == USI_VER2) - return exynos_usi_enable(usi); + ret = exynos_usi_enable(usi); + else + ret = clk_bulk_prepare_enable(usi->data->num_clks, + usi->clks); - return 0; + return ret; } static int exynos_usi_parse_dt(struct device_node *np, struct exynos_usi *usi)