From patchwork Thu Dec 19 16:30:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 182133 Delivered-To: patch@linaro.org Received: by 2002:a92:d0a:0:0:0:0:0 with SMTP id 10csp702237iln; Thu, 19 Dec 2019 08:31:25 -0800 (PST) X-Google-Smtp-Source: APXvYqz/VsWXxKmcgivURK9s4ZSINH3h89xuNGt7GpMme/gu/iPwVhpE49SSo88LeShHUYkDarkK X-Received: by 2002:aca:df07:: with SMTP id w7mr2656363oig.145.1576773085308; Thu, 19 Dec 2019 08:31:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576773085; cv=none; d=google.com; s=arc-20160816; b=gjqn5lagHUNzMVCARgfE5HN2AGxPBkKYOOHtpiXU6+ZDqE88G3K/+LSPCYdTqR4cox NdLoGFBHGgQp22dp7byVmTGnnegdSzt3iTMvMSkp7y5/Bij/xwnINpuWAjHG9LfA8q7j 9sBErwA73SUsELwoXBlPxl8EEXk9PpjBjAaxUYglZc4TL5vdPg8LKhNVR7WR4ZUYJmxQ vmO4wQuDoWQVwCZOzVmpF67O23mun+WMS4RTs/sfadi/oIlI8a3EB1ASWCJ472c/dUlN vuaLNtY473Zn2jp6mRZ9th7V499OLD6cxhde6kpO+3tbDATHD15eBwMgl88prllwI/Hd r9mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+Rlh4fuYqJBRp2jOU8B0MlV1M4d0Kd3bn04JlNplJUI=; b=kik35fxX3bz0lUgEmJQNFSh7qb8yi5AHECquddzfhkpXRIVOfoeb6Ov2EieFxAasl5 N18oba4xdVPkC/kKt+tDJteGvpC38FnmaGYmKpbbJ689xSpSIOpGusboXqSES7giG76c v40srbB/S7O4CIQGKZR7IV5A1b2z7jz9DMC9lb0A0oWHyrdr3aCnZuQD3/sqPuHXHcaI gH0NN7HQfCFgnu7Az3yV/gStl0gpm2PoR7tsz9G3S5itVprItgvT5NQXscgg2FWWGU0/ WwdJp1gW8GAIybbSgYdeEr4YtUgW3k/hyrLFZ3/0uRFyLYUEP2xiKdxzXlNLoIdJk6v4 cVXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DZ1mQvkj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[84.227.176.239]) by smtp.gmail.com with ESMTPSA id u22sm7092068wru.30.2019.12.19.08.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 08:31:20 -0800 (PST) From: Jean-Philippe Brucker To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com, eric.auger@redhat.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org Subject: [PATCH v4 02/13] dt-bindings: document PASID property for IOMMU masters Date: Thu, 19 Dec 2019 17:30:22 +0100 Message-Id: <20191219163033.2608177-3-jean-philippe@linaro.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219163033.2608177-1-jean-philippe@linaro.org> References: <20191219163033.2608177-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Arm systems, some platform devices behind an SMMU may support the PASID feature, which offers multiple address space. Let the firmware tell us when a device supports PASID. Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Reviewed-by: Rob Herring Signed-off-by: Jean-Philippe Brucker --- Documentation/devicetree/bindings/iommu/iommu.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.24.1 diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt index 5a8b4624defc..3c36334e4f94 100644 --- a/Documentation/devicetree/bindings/iommu/iommu.txt +++ b/Documentation/devicetree/bindings/iommu/iommu.txt @@ -86,6 +86,12 @@ have a means to turn off translation. But it is invalid in such cases to disable the IOMMU's device tree node in the first place because it would prevent any driver from properly setting up the translations. +Optional properties: +-------------------- +- pasid-num-bits: Some masters support multiple address spaces for DMA, by + tagging DMA transactions with an address space identifier. By default, + this is 0, which means that the device only has one address space. + Notes: ====== From patchwork Thu Dec 19 16:30:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 182134 Delivered-To: patch@linaro.org Received: by 2002:a92:d0a:0:0:0:0:0 with SMTP id 10csp702307iln; Thu, 19 Dec 2019 08:31:28 -0800 (PST) X-Google-Smtp-Source: APXvYqxOCR6ue1EMxcDcywhCghxO2W6D5utiVuI8Xq1hNJOgiScLrCF4gLSwJHIysstNPtvWO6IM X-Received: by 2002:aca:b344:: with SMTP id c65mr2601646oif.88.1576773088413; Thu, 19 Dec 2019 08:31:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576773088; cv=none; d=google.com; s=arc-20160816; b=q5K+wsem0oKaOX4F2k8q/LwhAZMaDES2XpV4mTFBM53t2oQnbZbKulLMXcQhwFpW6G /+LSUoUTAhpWxU0BdcsKycMg5jwZOvrsOintCho9+MmY4hhPnqw/4MayyTy9ZCK3+Wkv /+UHTbtmMC/TkaPB81XweG1AEG1IECun/RgWYZtMtAp5WKXv1iVAZiY3sH0utTudE16x KdeOMA6eAQhQY0Ngo2fQPjWisz+aab2WOFUyCQjo5EMsjFOzSWsGZC1E85oHuZYvXmmN ebYgAxy59BAQ2jQXuXyEc9qmPsvGPkMO92z/3vEwZNHxbsuVMG7QASQcPX+pbAkcb+rD jY6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Q4JsCWxXHC8YjpStG5e1vl4meeR6Q/c6EwcKRZXnP4g=; b=VgWRpnDoWGko5zLWYP0M0Q0yVcIk4SQ3JB7feFC4Q2wZLyEQewngi50bxxXUgxZ0DH CbQ1r6IezaTeQOIXytIQ11nPIHDdssljbDbiwPzdjNcsNtS2lkIhH3g202nP6/51b3ae ShpAfArtipcU/25+iji1BMvr8YJVnbVOMC8QjGIu58h0O/781+1+iXqFr9yOen8OLy0v tpl9JGctBoxEspSCpeOudW+fp4Lv79kw3AqqSzzeuaWbzRMliLN8ieCmrWoAy2BR1rbL btwUuGm936UetvZ3Cw7yG8ba+4vUE1GvtDGUNydM5sCaCFEEN1SwraQTQ46W0zToNUIY 9SQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sTqcWUok; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[84.227.176.239]) by smtp.gmail.com with ESMTPSA id u22sm7092068wru.30.2019.12.19.08.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 08:31:22 -0800 (PST) From: Jean-Philippe Brucker To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com, eric.auger@redhat.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org Subject: [PATCH v4 03/13] iommu/arm-smmu-v3: Parse PASID devicetree property of platform devices Date: Thu, 19 Dec 2019 17:30:23 +0100 Message-Id: <20191219163033.2608177-4-jean-philippe@linaro.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219163033.2608177-1-jean-philippe@linaro.org> References: <20191219163033.2608177-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For platform devices that support SubstreamID (SSID), firmware provides the number of supported SSID bits. Restrict it to what the SMMU supports and cache it into master->ssid_bits, which will also be used for PCI PASID. Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 13 +++++++++++++ drivers/iommu/of_iommu.c | 6 +++++- include/linux/iommu.h | 2 ++ 3 files changed, 20 insertions(+), 1 deletion(-) -- 2.24.1 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index d4e8b7f8d9f4..837b4283b4dc 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -292,6 +292,12 @@ #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) +/* + * When the SMMU only supports linear context descriptor tables, pick a + * reasonable size limit (64kB). + */ +#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3)) + /* Convert between AArch64 (CPU) TCR format and SMMU CD format */ #define ARM_SMMU_TCR2CD(tcr, fld) FIELD_PREP(CTXDESC_CD_0_TCR_##fld, \ FIELD_GET(ARM64_TCR_##fld, tcr)) @@ -638,6 +644,7 @@ struct arm_smmu_master { u32 *sids; unsigned int num_sids; bool ats_enabled; + unsigned int ssid_bits; }; /* SMMU private data for an IOMMU domain */ @@ -2571,6 +2578,12 @@ static int arm_smmu_add_device(struct device *dev) } } + master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits); + + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) + master->ssid_bits = min_t(u8, master->ssid_bits, + CTXDESC_LINEAR_CDMAX); + group = iommu_group_get_for_dev(dev); if (!IS_ERR(group)) { iommu_group_put(group); diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 026ad2b29dcd..b3ccb2f7f1c7 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -196,8 +196,12 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, if (err) break; } - } + fwspec = dev_iommu_fwspec_get(dev); + if (!err && fwspec) + of_property_read_u32(master_np, "pasid-num-bits", + &fwspec->num_pasid_bits); + } /* * Two success conditions can be represented by non-negative err here: diff --git a/include/linux/iommu.h b/include/linux/iommu.h index f2223cbb5fd5..956031eab3ef 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -570,6 +570,7 @@ struct iommu_group *fsl_mc_device_group(struct device *dev); * @ops: ops for this device's IOMMU * @iommu_fwnode: firmware handle for this device's IOMMU * @iommu_priv: IOMMU driver private data for this device + * @num_pasid_bits: number of PASID bits supported by this device * @num_ids: number of associated device IDs * @ids: IDs which this device may present to the IOMMU */ @@ -578,6 +579,7 @@ struct iommu_fwspec { struct fwnode_handle *iommu_fwnode; void *iommu_priv; u32 flags; + u32 num_pasid_bits; unsigned int num_ids; u32 ids[1]; }; From patchwork Thu Dec 19 16:30:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 182139 Delivered-To: patch@linaro.org Received: by 2002:a92:d0a:0:0:0:0:0 with SMTP id 10csp702465iln; Thu, 19 Dec 2019 08:31:34 -0800 (PST) X-Google-Smtp-Source: APXvYqwdrvZLTCGoRJmCapHMA4cJs+NMEfeLpS2mwWJkTQOsJUYdkP2bxRfEwFNGUaAX252evLkJ X-Received: by 2002:a9d:70cb:: with SMTP id w11mr9831131otj.157.1576773094513; Thu, 19 Dec 2019 08:31:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576773094; cv=none; d=google.com; s=arc-20160816; b=VU+E9pkVgpnTXIba8svdh+JsC28LgcRS0fGpH/Mg5Pt2uZR6rDTY8JvJBp080Xq1A+ 2/EVuujv454dzoOF6ENxgyiUmqyMj1JiFPGR/2aet18pBKmQoylm7aGySNCqPX8tFalH iR3G6wLAUwmgz5JJF3bSLHS76U9V/F/g3F86moUlterIm6zBi+JPMfxTkD1vOh8g30bq g0lvEITFx+6gHhIojhFJPADxhlLZnS2dL+IMzYbN+RdoNJhZN4rgRH3mlDbgyCzKGyez oE/oN3iYAR+o+Fz/Sl+Qz2z758l837M7xPKR83YtG2k+EIdAQenN2ed2aqQPi/42QwuW 62kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FYioDhZ/j/78qMyUi+NbeqzegCC3zzPggnOI7+kacPU=; b=zw5SAa6IgxWr05cGwtiewA+gJhnAVT1V3m3yfH0lt16he6CvdcWd4K0couK2xT5bdF 986fitH+MRTBRbMK6mbxS0DqWLpbwlkqVbi2tq8gCvVizd+F+ma3ogwlo/sNAq7gdzNZ UfPVzViQ89V1Vo1PIkzQNiJHXbxvxQzEgdDxB41IxxkAGLIM6Cgbh/RhEgvftsAHAWeM 3oLSD0HcqnTrjO7+PUl01yUBa80Iap8BKUsWCuZnhfcmgQtCV5EVDHo6w1oGhy3sYB1V ttn7IkHAiTSY1vf+PBSOs7r9ynyGw9y3hlo4RYLIhrQRQdIjP8l32tQRsg2LmaE9mVti 622Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E5aFBHpx; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[84.227.176.239]) by smtp.gmail.com with ESMTPSA id u22sm7092068wru.30.2019.12.19.08.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 08:31:29 -0800 (PST) From: Jean-Philippe Brucker To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com, eric.auger@redhat.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org Subject: [PATCH v4 08/13] iommu/arm-smmu-v3: Propagate ssid_bits Date: Thu, 19 Dec 2019 17:30:28 +0100 Message-Id: <20191219163033.2608177-9-jean-philippe@linaro.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219163033.2608177-1-jean-philippe@linaro.org> References: <20191219163033.2608177-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that we support substream IDs, initialize s1cdmax with the number of SSID bits supported by a master and the SMMU. Context descriptor tables are allocated once for the first master attached to a domain. Therefore attaching multiple devices with different SSID sizes is tricky, and we currently don't support it. As a future improvement it would be nice to at least support attaching a SSID-capable device to a domain that isn't using SSID, by reallocating the SSID table. This would allow supporting a SSID-capable device that is in the same IOMMU group as a bridge, for example. Varying SSID size is less of a concern, since the PCIe specification "highly recommends" that devices supporting PASID implement all 20 bits of it. Tested-by: Zhangfei Gao Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) -- 2.24.1 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e1bec7e552b9..e147087198ef 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2279,6 +2279,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) } static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { int ret; @@ -2290,6 +2291,8 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (asid < 0) return asid; + cfg->s1cdmax = master->ssid_bits; + ret = arm_smmu_alloc_cd_tables(smmu_domain); if (ret) goto out_free_asid; @@ -2306,6 +2309,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, } static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { int vmid; @@ -2322,7 +2326,8 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, return 0; } -static int arm_smmu_domain_finalise(struct iommu_domain *domain) +static int arm_smmu_domain_finalise(struct iommu_domain *domain, + struct arm_smmu_master *master) { int ret; unsigned long ias, oas; @@ -2330,6 +2335,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain) struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; int (*finalise_stage_fn)(struct arm_smmu_domain *, + struct arm_smmu_master *, struct io_pgtable_cfg *); struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; @@ -2384,7 +2390,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain) domain->geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; domain->geometry.force_aperture = true; - ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg); + ret = finalise_stage_fn(smmu_domain, master, &pgtbl_cfg); if (ret < 0) { free_io_pgtable_ops(pgtbl_ops); return ret; @@ -2537,7 +2543,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) if (!smmu_domain->smmu) { smmu_domain->smmu = smmu; - ret = arm_smmu_domain_finalise(domain); + ret = arm_smmu_domain_finalise(domain, master); if (ret) { smmu_domain->smmu = NULL; goto out_unlock; @@ -2549,6 +2555,13 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) dev_name(smmu->dev)); ret = -ENXIO; goto out_unlock; + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && + master->ssid_bits != smmu_domain->s1_cfg.s1cdmax) { + dev_err(dev, + "cannot attach to incompatible domain (%u SSID bits != %u)\n", + smmu_domain->s1_cfg.s1cdmax, master->ssid_bits); + ret = -EINVAL; + goto out_unlock; } master->domain = smmu_domain; From patchwork Thu Dec 19 16:30:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 182140 Delivered-To: patch@linaro.org Received: by 2002:a92:d0a:0:0:0:0:0 with SMTP id 10csp702476iln; Thu, 19 Dec 2019 08:31:34 -0800 (PST) X-Google-Smtp-Source: APXvYqyxNpt1fqUUSyfnLHOz0CSmUrb+9fy9fYhb052FYXYsZJPNYFIi7Y7jPSJJdABRp2rb8Zd6 X-Received: by 2002:a9d:754a:: with SMTP id b10mr9737698otl.273.1576773094906; Thu, 19 Dec 2019 08:31:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576773094; cv=none; d=google.com; s=arc-20160816; b=RoNClveHbZpWhKTiVR/B9+taUPGMpvfPn0YoGZCeCXdqWUXZHXXM79Bo6VS+wwIMQh 8lyX1kzG/jp1pt+iPwzMoZv9jQ9fnIDY29XmAJ6QCd0QAiw72V8dGjAh9C3xB2UcFqCr p/pzKC99ls0kOQgAeM15ZWfvOIDGu4dQe6UfQ2MNXIy1wbQy3x6FS3n7mttqyd3yO1Yl MTfLVd/1+CcvQ1fVYN6WWH1mA/0sV2j8rw9a6jaHtCiIu9CZhwN5Um6wJY2rgmhIN8QJ YcJkIeHg9OauoeGJFNHo+Owq/q9x2XO4NrWNaOvEhgdZAr6sZCzWjJMLCjiDsoQ8B3tq bXAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0nQT4ayYi2icUCghAPJFv/Sszvlp8khOsvgAay7NA80=; b=QQxazRHKf+JIUxDtW1YtOUd5mrejH+oeTMGWdZDVefansaH4bKRnWXPs/Q/YXR//7J Wqm0Mw+EqFB7bzIrJG9ltfyMkKA0XEqmpKe/+AORJPHjvbJjydk72kaM9Mi2R8r30rAJ RZWGNzeYtNAENaDrtoGkOfdhmxfwbP6DchedxuUeEIsBEb+rreQWPcwLRVM+BIGEcLRS ciNL26AF9H7mczAUPTUfYDPlyJTs35a5gHE1EAipa/F2HgyyG5Bt0QiVNgZGQSR4adMu caEEuzLoVLmRbIOcflDQDQ4jx1tP7u3scef5kSI1mMraN4gbH0QVIEOrBgrEM5cwTCkT TBNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=npHKtHQy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[84.227.176.239]) by smtp.gmail.com with ESMTPSA id u22sm7092068wru.30.2019.12.19.08.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 08:31:30 -0800 (PST) From: Jean-Philippe Brucker To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com, eric.auger@redhat.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org Subject: [PATCH v4 09/13] iommu/arm-smmu-v3: Prepare for handling arm_smmu_write_ctx_desc() failure Date: Thu, 19 Dec 2019 17:30:29 +0100 Message-Id: <20191219163033.2608177-10-jean-philippe@linaro.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219163033.2608177-1-jean-philippe@linaro.org> References: <20191219163033.2608177-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Second-level context descriptor tables will be allocated lazily in arm_smmu_write_ctx_desc(). Help with handling allocation failure by moving the CD write into arm_smmu_domain_finalise_s1(). Reviewed-by: Eric Auger Reviewed-by: Jonathan Cameron Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.24.1 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e147087198ef..b825a5639afc 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2301,8 +2301,15 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; + + ret = arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd); + if (ret) + goto out_free_tables; + return 0; +out_free_tables: + arm_smmu_free_cd_tables(smmu_domain); out_free_asid: arm_smmu_bitmap_free(smmu->asid_map, asid); return ret; @@ -2569,10 +2576,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) if (smmu_domain->stage != ARM_SMMU_DOMAIN_BYPASS) master->ats_enabled = arm_smmu_ats_supported(master); - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) - arm_smmu_write_ctx_desc(smmu_domain, 0, - &smmu_domain->s1_cfg.cd); - arm_smmu_install_ste_for_dev(master); spin_lock_irqsave(&smmu_domain->devices_lock, flags); From patchwork Thu Dec 19 16:30:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 182141 Delivered-To: patch@linaro.org Received: by 2002:a92:d0a:0:0:0:0:0 with SMTP id 10csp702539iln; Thu, 19 Dec 2019 08:31:38 -0800 (PST) X-Google-Smtp-Source: APXvYqypitfdUqiyrOAmcHB435FmkQRvj3Me249lnOZm7K7q4D/vkfF9vTzO7+LvU9qGzaBfnMrz X-Received: by 2002:aca:ad11:: with SMTP id w17mr2736946oie.85.1576773097939; Thu, 19 Dec 2019 08:31:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576773097; cv=none; d=google.com; s=arc-20160816; b=RIBmDpX0+5Eg+inlXiYJyugp4+l3dEC8FiO0HW4Axtd3SWyCAAM28ok4KRevKYYBFz POchUrUTbFhXTG+xlgZLP4qtas83PF1T2P8k00hMF5GC+0l/CLHbwiST47MbTEO66aoC MhLV1APURF1h7SRKbuV9jCYK8Zr0OmepdTTd5Zi/EZPQID76Hyzcox8pJsxJviLk2HiG m3UksLF8yGaFg1wvmTK60XfaSevT/GqN9z9bqFxjvG3myn9lAfF7cMr+G9ekgrz2FldI VYP/BZeWeijqas6rKuHtPvyblcGLzeMOjM8AcKnN5MrOuRqxO5XmufBP2BHuMaBXMPFZ D0FA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FClVKTteeYiGIMx90m+9aFZ0WcdcaYLYnXI1Jq7jvMc=; b=pK78vG2oD4+mqMjNvvz9fnAQv7//1sxc7hzYyGeHwhdQn/F8FeN3JZ6D8/nsUXfOdD 2aWWiAPNwqYed9lJKCYWrJx/vhh6K/UDepoNyvZNasOSlEbyoeuNe0lrtj5b2qKtBl6C Cg04JLitndNuGccWB0L0fxeHX80g2ciLnNRfhlCbWOiBjxUalnJfaanw4ENIQ/RQ6kz7 DpcyL+O0piUEnMWstaQPUGftUkhqL15tOQd4rLR3p5Wvfn2EBgWANTROFmJUk0NfmCQ2 +06ABWI2dQghLY2SntRxUgGsaNiYZ16VQNmdD34wcbC9u5dtW/IqYQ4ZPzCKszEuTMhN Ag/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dVa09UAo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[84.227.176.239]) by smtp.gmail.com with ESMTPSA id u22sm7092068wru.30.2019.12.19.08.31.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 08:31:31 -0800 (PST) From: Jean-Philippe Brucker To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com, eric.auger@redhat.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org Subject: [PATCH v4 10/13] iommu/arm-smmu-v3: Add second level of context descriptor table Date: Thu, 19 Dec 2019 17:30:30 +0100 Message-Id: <20191219163033.2608177-11-jean-philippe@linaro.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219163033.2608177-1-jean-philippe@linaro.org> References: <20191219163033.2608177-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SMMU can support up to 20 bits of SSID. Add a second level of page tables to accommodate this. Devices that support more than 1024 SSIDs now have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context descriptors (64kB), allocated on demand. Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 154 +++++++++++++++++++++++++++++++++--- 1 file changed, 144 insertions(+), 10 deletions(-) -- 2.24.1 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index b825a5639afc..bf106a7b53eb 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -224,6 +224,7 @@ #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 +#define STRTAB_STE_0_S1FMT_64K_L2 2 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) @@ -263,7 +264,20 @@ #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) -/* Context descriptor (stage-1 only) */ +/* + * Context descriptors. + * + * Linear: when less than 1024 SSIDs are supported + * 2lvl: at most 1024 L1 entries, + * 1024 lazy entries per table. + */ +#define CTXDESC_SPLIT 10 +#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT) + +#define CTXDESC_L1_DESC_DWORDS 1 +#define CTXDESC_L1_DESC_VALID 1 +#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) + #define CTXDESC_CD_DWORDS 8 #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) #define ARM64_TCR_T0SZ GENMASK_ULL(5, 0) @@ -575,7 +589,12 @@ struct arm_smmu_cd_table { }; struct arm_smmu_s1_cfg { - struct arm_smmu_cd_table table; + /* Leaf tables or linear table */ + struct arm_smmu_cd_table *tables; + size_t num_tables; + /* First level tables, when two levels are used */ + __le64 *l1ptr; + dma_addr_t l1ptr_dma; struct arm_smmu_ctx_desc cd; u8 s1fmt; u8 s1cdmax; @@ -1521,9 +1540,48 @@ static void arm_smmu_free_cd_leaf_table(struct arm_smmu_device *smmu, { size_t size = num_entries * (CTXDESC_CD_DWORDS << 3); + if (!table->ptr) + return; dmam_free_coherent(smmu->dev, size, table->ptr, table->ptr_dma); } +static void arm_smmu_write_cd_l1_desc(__le64 *dst, + struct arm_smmu_cd_table *table) +{ + u64 val = (table->ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) | + CTXDESC_L1_DESC_VALID; + + WRITE_ONCE(*dst, cpu_to_le64(val)); +} + +static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain, + u32 ssid) +{ + __le64 *l1ptr; + unsigned int idx; + struct arm_smmu_cd_table *table; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + + if (cfg->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) + return cfg->tables[0].ptr + ssid * CTXDESC_CD_DWORDS; + + idx = ssid >> CTXDESC_SPLIT; + table = &cfg->tables[idx]; + if (!table->ptr) { + if (arm_smmu_alloc_cd_leaf_table(smmu, table, + CTXDESC_L2_ENTRIES)) + return NULL; + + l1ptr = cfg->l1ptr + idx * CTXDESC_L1_DESC_DWORDS; + arm_smmu_write_cd_l1_desc(l1ptr, table); + /* An invalid L1CD can be cached */ + arm_smmu_sync_cd(smmu_domain, ssid, false); + } + idx = ssid & (CTXDESC_L2_ENTRIES - 1); + return table->ptr + idx * CTXDESC_CD_DWORDS; +} + static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) { u64 val = 0; @@ -1556,8 +1614,14 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, u64 val; bool cd_live; struct arm_smmu_device *smmu = smmu_domain->smmu; - __le64 *cdptr = smmu_domain->s1_cfg.table.ptr + ssid * - CTXDESC_CD_DWORDS; + __le64 *cdptr; + + if (WARN_ON(ssid >= (1 << smmu_domain->s1_cfg.s1cdmax))) + return -E2BIG; + + cdptr = arm_smmu_get_cd_ptr(smmu_domain, ssid); + if (!cdptr) + return -ENOMEM; val = le64_to_cpu(cdptr[0]); cd_live = !!(val & CTXDESC_CD_0_V); @@ -1604,20 +1668,87 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) { + int ret; + size_t size = 0; + size_t max_contexts; struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; - cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; - return arm_smmu_alloc_cd_leaf_table(smmu, &cfg->table, - 1 << cfg->s1cdmax); + max_contexts = 1 << cfg->s1cdmax; + + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || + max_contexts <= CTXDESC_L2_ENTRIES) { + cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; + cfg->num_tables = 1; + } else { + cfg->s1fmt = STRTAB_STE_0_S1FMT_64K_L2; + cfg->num_tables = DIV_ROUND_UP(max_contexts, + CTXDESC_L2_ENTRIES); + + size = cfg->num_tables * (CTXDESC_L1_DESC_DWORDS << 3); + cfg->l1ptr = dmam_alloc_coherent(smmu->dev, size, + &cfg->l1ptr_dma, + GFP_KERNEL); + if (!cfg->l1ptr) { + dev_warn(smmu->dev, + "failed to allocate L1 context table\n"); + return -ENOMEM; + } + } + + cfg->tables = devm_kzalloc(smmu->dev, sizeof(struct arm_smmu_cd_table) * + cfg->num_tables, GFP_KERNEL); + if (!cfg->tables) { + ret = -ENOMEM; + goto err_free_l1; + } + + /* + * Only allocate a leaf table for linear case. With two levels, leaf + * tables are allocated lazily. + */ + if (cfg->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) { + ret = arm_smmu_alloc_cd_leaf_table(smmu, &cfg->tables[0], + max_contexts); + if (ret) + goto err_free_tables; + } + + return 0; + +err_free_tables: + devm_kfree(smmu->dev, cfg->tables); + cfg->tables = NULL; +err_free_l1: + if (cfg->l1ptr) { + dmam_free_coherent(smmu->dev, size, cfg->l1ptr, cfg->l1ptr_dma); + cfg->l1ptr = NULL; + cfg->l1ptr_dma = 0; + } + return ret; } static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) { + int i; struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + size_t num_leaf_entries = 1 << cfg->s1cdmax; + struct arm_smmu_cd_table *table = cfg->tables; + + if (cfg->l1ptr) { + size_t size = cfg->num_tables * (CTXDESC_L1_DESC_DWORDS << 3); - arm_smmu_free_cd_leaf_table(smmu, &cfg->table, 1 << cfg->s1cdmax); + dmam_free_coherent(smmu->dev, size, cfg->l1ptr, cfg->l1ptr_dma); + cfg->l1ptr = NULL; + cfg->l1ptr_dma = 0; + num_leaf_entries = CTXDESC_L2_ENTRIES; + } + + for (i = 0; i < cfg->num_tables; i++, table++) + arm_smmu_free_cd_leaf_table(smmu, table, num_leaf_entries); + devm_kfree(smmu->dev, cfg->tables); + cfg->tables = NULL; } /* Stream table manipulation functions */ @@ -1737,6 +1868,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, } if (s1_cfg) { + dma_addr_t ptr_dma = s1_cfg->l1ptr ? s1_cfg->l1ptr_dma : + s1_cfg->tables[0].ptr_dma; + BUG_ON(ste_live); dst[1] = cpu_to_le64( FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | @@ -1749,7 +1883,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); - val |= (s1_cfg->table.ptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + val |= (ptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); @@ -2265,7 +2399,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; - if (cfg->table.ptr) { + if (cfg->tables) { arm_smmu_free_cd_tables(smmu_domain); arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid); }