From patchwork Wed Jan 29 16:37:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 860969 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BF5C51E0DB5; Wed, 29 Jan 2025 16:51:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169521; cv=none; b=F7rvXZkCrZ2+/nNDEYAaOY1yWl7rVMSntRdNE2ycv41yt8svL5s+1zEBd5woFTGCGXzVT1q9cy4q34e8yxYtgog3Kktf3J2KR0v5Nan2lyJMAjlp0o9gyZ7swRB09aDqu9J7q7YsB5p31h+BXWa8QTUZDJsHo76rbLLgUx0RfIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169521; c=relaxed/simple; bh=CUH9n+oPHOWyM3u6BZlgaSX/u3UOlrz9vO5jpb8oU30=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D7jJFxRtnb6oohp8GwwpERhAFXnS6lGIGLqRXltqf5qTX4SgFoPVAbgxZmLn3F/1WwdH8rSNW7cSVqWqgPxjUUfxVepefvhZBslx0sQC3LCAMnpr0LJVe08jHXHP3kUXXdlYCPKaSVzSJR4sQYAfvYCYvjhdEzaZyNy0ZTS4nR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: hShsvux3TAmY5SDmWSSOGA== X-CSE-MsgGUID: CJI+EUM4RICmJ+c+MDvTyQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Jan 2025 01:51:58 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9567F402EEE6; Thu, 30 Jan 2025 01:51:46 +0900 (JST) From: Thierry Bultel To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Thierry Bultel Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC Date: Wed, 29 Jan 2025 16:37:38 +0000 Message-ID: <20250129165122.2980-3-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document RZ/T2H (a.k.a r9a09g077) in SCI binding. Signed-off-by: Thierry Bultel --- .../bindings/serial/renesas,rzsci.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzsci.yaml diff --git a/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml new file mode 100644 index 000000000000..70e83bbcc79d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Serial Communication Interface + +maintainers: + - Thierry Bultel + - Geert Uytterhoeven + +allOf: + - $ref: serial.yaml# + +description: | + The SCI is configurable to asynchronous and synchronous serial + interfaces: + - Asynchronous interfaces (UART and Asynchronous Communications Interface + Adapter (ACIA)) + - 8-bit clock synchronous interface + - Simple I2C (master-only) + - Simple SPI + - Smart card interface + - Manchester mode + - Asynchronous interfaces (UART, RS485 and Asynchronous Communications + Interface Adapter (ACIA)) + The smart card interface complies with the ISO/IEC 7816-3 standard for + electronic signals and transmission protocol. Each SCI has FIFO buffers to + enable continuous and full-duplex communication, and the data transfer speed + can be configured independently using a baud rate generator. + +properties: + compatible: + const: renesas,r9a09g077-sci # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit end interrupt + + interrupt-names: + items: + - const: eri + - const: rxi + - const: txi + - const: tei + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - fck # UART functional clock + - sck # optional external clock input + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + + aliases { + serial0 = &sci0; + }; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-sci"; + reg = <0x80005000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A09G077_SCI0_CLK>; + clock-names = "fck"; + power-domains = <&cpg>; + }; From patchwork Wed Jan 29 16:37:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 860968 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 919C91E282D; Wed, 29 Jan 2025 16:52:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169556; cv=none; b=YeZa9v9Y75Z8rutOuzzetAeYwHVFnA3QJOZR7x9utUgG52QrUjDS6KOYhj3Ui9pqqDMpEjoGX3io3S4MdB+rS67M5T/ez/k4JGXjpeQrVH9DGsl7C/kO8d0473jhhjvQVeYJSV6k+XX8xbbW2Gwhxsi75qnQ3iZS3quD7qifIOI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169556; c=relaxed/simple; bh=xn/J2ZZEURyrCoODGcYuD1ceH289yvenvAXtFXdyBtE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O/nBWAFgusCsIwurdatETbL7KgeFn/x9IWPz66tXjETEL7k6gXVWXHVqskdERAbMRUKVlww01RZS6UGEWWTsaupOqYEd4wPu8BugHBR5RJpSVzQdoL4S8a3rtQwJnD+uc8+wUaH2qtVFK0t5hqulAzV/VnsAVbuxp3F41vxFTSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: c0TsLQ3bQl2mIuPtm3FWEg== X-CSE-MsgGUID: 8H9hB2pVR/KZSaRoPohoqw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:33 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0E8FF402F520; Thu, 30 Jan 2025 01:52:20 +0900 (JST) From: Thierry Bultel To: Greg Kroah-Hartman , Jiri Slaby Cc: Thierry Bultel , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 08/14] serial: sh-sci: Fix a comment about SCIFA Date: Wed, 29 Jan 2025 16:37:44 +0000 Message-ID: <20250129165122.2980-9-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 RZ/T1 has SCIFA, 'T' is not relevant. Signed-off-by: Thierry Bultel --- drivers/tty/serial/sh-sci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 924b803af440..5ba25a6a5432 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -291,7 +291,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { }, /* - * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. + * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1 * It looks like a normal SCIF with FIFO data, but with a * compressed address space. Also, the break out of interrupts * are different: ERI/BRI, RXI, TXI, TEI, DRI. From patchwork Wed Jan 29 16:37:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 860804 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 718371E2614; Wed, 29 Jan 2025 16:52:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169557; cv=none; b=IhsDSsRwdazZ0zJmjblxWokNEiyi1q3YtOINXxUOD5WvKt+cPRPfwHe738AmiGXMnLcrH/dycaDj2EqjvDAANVmobJ4MkCXWDphW0CCVIc4W+V4BPmkVlNoeUzLubMbEEq7cqX/9XSns3v2MCepVYch1QXrI/LuBYOula3Nwypc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169557; c=relaxed/simple; bh=9W0EFD/YrkAIX4U9bqCUpt1Pz2dLaGvLwVhXYvCD1MA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mC3+bejQfwZWN0iZqcvjgkgEDwBfE4p0L9CtMYJ+wQlOI/Ev5DSuFvNLjgpyA60uZ4Hb82T0PXLB7hx7RIdj02BMX7jGMuCQvLj+AMDJYLi6BmAHizTjw/ulv3O3lKPWTGrTl4xqKJ0hRtAwLnTn5zuxTNTBqipLV7Rpo5s1w0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 3Lrl+SbvTbiKukIu0zXbEQ== X-CSE-MsgGUID: SvNL5YtMTUy/0TeeKlncrA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:34 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B084D402F02E; Thu, 30 Jan 2025 01:52:25 +0900 (JST) From: Thierry Bultel To: Greg Kroah-Hartman , Jiri Slaby Cc: Thierry Bultel , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 09/14] serial: sh-sci: Introduced function pointers Date: Wed, 29 Jan 2025 16:37:45 +0000 Message-ID: <20250129165122.2980-10-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The aim here is to prepare support for new sci controllers like the T2H/RSCI whose registers are too much different for being handled in common code. This named serial controller also has 32 bits register, so some return types had to be changed. The needed generic functions are no longer static, with prototypes defined in sh-sci-common.h so that they can be used from specific implementation in a separate file, to keep this driver as little changed as possible. For doing so, a set of 'ops' is added to struct sci_port. Signed-off-by: Thierry Bultel --- drivers/tty/serial/sh-sci.c | 339 +++++++++++++++-------------- drivers/tty/serial/sh-sci_common.h | 178 +++++++++++++++ 2 files changed, 349 insertions(+), 168 deletions(-) create mode 100644 drivers/tty/serial/sh-sci_common.h diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 5ba25a6a5432..1b83a246c7ed 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -56,19 +56,7 @@ #include "serial_mctrl_gpio.h" #include "sh-sci.h" - -/* Offsets into the sci_port->irqs array */ -enum { - SCIx_ERI_IRQ, - SCIx_RXI_IRQ, - SCIx_TXI_IRQ, - SCIx_BRI_IRQ, - SCIx_DRI_IRQ, - SCIx_TEI_IRQ, - SCIx_NR_IRQS, - - SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ -}; +#include "sh-sci_common.h" #define SCIx_IRQ_IS_MUXED(port) \ ((port)->irqs[SCIx_ERI_IRQ] == \ @@ -76,101 +64,39 @@ enum { ((port)->irqs[SCIx_ERI_IRQ] && \ ((port)->irqs[SCIx_RXI_IRQ] < 0)) -enum SCI_CLKS { - SCI_FCK, /* Functional Clock */ - SCI_SCK, /* Optional External Clock */ - SCI_BRG_INT, /* Optional BRG Internal Clock Source */ - SCI_SCIF_CLK, /* Optional BRG External Clock Source */ - SCI_NUM_CLKS -}; - -/* Bit x set means sampling rate x + 1 is supported */ -#define SCI_SR(x) BIT((x) - 1) #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ SCI_SR(19) | SCI_SR(27) -#define min_sr(_port) ffs((_port)->sampling_rate_mask) -#define max_sr(_port) fls((_port)->sampling_rate_mask) - /* Iterate over all supported sampling rates, from high to low */ #define for_each_sr(_sr, _port) \ for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ if ((_port)->sampling_rate_mask & SCI_SR((_sr))) -struct plat_sci_reg { - u8 offset, size; -}; - -struct sci_port_params { - const struct plat_sci_reg regs[SCIx_NR_REGS]; - unsigned int fifosize; - unsigned int overrun_reg; - unsigned int overrun_mask; - unsigned int sampling_rate_mask; - unsigned int error_mask; - unsigned int error_clear; -}; - -struct sci_port { - struct uart_port port; - - /* Platform configuration */ - const struct sci_port_params *params; - const struct plat_sci_port *cfg; - unsigned int sampling_rate_mask; - resource_size_t reg_size; - struct mctrl_gpios *gpios; - - /* Clocks */ - struct clk *clks[SCI_NUM_CLKS]; - unsigned long clk_rates[SCI_NUM_CLKS]; - - int irqs[SCIx_NR_IRQS]; - char *irqstr[SCIx_NR_IRQS]; - - struct dma_chan *chan_tx; - struct dma_chan *chan_rx; - -#ifdef CONFIG_SERIAL_SH_SCI_DMA - struct dma_chan *chan_tx_saved; - struct dma_chan *chan_rx_saved; - dma_cookie_t cookie_tx; - dma_cookie_t cookie_rx[2]; - dma_cookie_t active_rx; - dma_addr_t tx_dma_addr; - unsigned int tx_dma_len; - struct scatterlist sg_rx[2]; - void *rx_buf[2]; - size_t buf_len_rx; - struct work_struct work_tx; - struct hrtimer rx_timer; - unsigned int rx_timeout; /* microseconds */ -#endif - unsigned int rx_frame; - int rx_trigger; - struct timer_list rx_fifo_timer; - int rx_fifo_timeout; - u16 hscif_tot; - - bool has_rtscts; - bool autorts; - bool tx_occurred; -}; - #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS static struct sci_port sci_ports[SCI_NPORTS]; static unsigned long sci_ports_in_use; static struct uart_driver sci_uart_driver; -static inline struct sci_port * -to_sci_port(struct uart_port *uart) -{ - return container_of(uart, struct sci_port, port); -} +static const struct sci_port_params_bits sci_sci_port_params_bits = { + .rxtx_enable = SCSCR_RE | SCSCR_TE, + .te_clear = SCSCR_TE | SCSCR_TEIE, + .poll_sent_bits = SCI_FER | SCI_TEND +}; + +static const struct sci_port_params_bits sci_scix_port_params_bits = { + .rxtx_enable = SCSCR_RE | SCSCR_TE, + .te_clear = SCSCR_TE | SCSCR_TEIE, + .poll_sent_bits = SCIF_TDFE | SCIF_TEND +}; + +static const struct sci_common_regs sci_common_regs = { + .status = SCxSR, + .control = SCSCR, +}; static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { /* @@ -192,6 +118,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, + .param_bits = sci_sci_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -214,6 +142,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -238,6 +168,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR_SCIFAB, .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -263,6 +195,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR_SCIFAB, .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -288,6 +222,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -316,6 +252,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -347,6 +285,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -369,6 +309,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -393,6 +335,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -420,6 +364,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -449,6 +395,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR_RANGE(8, 32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -473,6 +421,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -500,6 +450,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(32), .error_mask = SCIF_DEFAULT_ERROR_MASK, .error_clear = SCIF_ERROR_CLEAR, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, /* @@ -523,6 +475,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .sampling_rate_mask = SCI_SR(16), .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, + .param_bits = sci_scix_port_params_bits, + .common_regs = &sci_common_regs, }, }; @@ -560,7 +514,7 @@ static void sci_serial_out(struct uart_port *p, int offset, int value) WARN(1, "Invalid register access\n"); } -static void sci_port_enable(struct sci_port *sci_port) +void sci_port_enable(struct sci_port *sci_port) { unsigned int i; @@ -576,7 +530,7 @@ static void sci_port_enable(struct sci_port *sci_port) sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; } -static void sci_port_disable(struct sci_port *sci_port) +void sci_port_disable(struct sci_port *sci_port) { unsigned int i; @@ -713,15 +667,16 @@ static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) defined(CONFIG_SERIAL_SH_SCI_EARLYCON) #ifdef CONFIG_CONSOLE_POLL -static int sci_poll_get_char(struct uart_port *port) +int sci_poll_get_char(struct uart_port *port) { unsigned short status; + struct sci_port *s = to_sci_port(port); int c; do { status = sci_serial_in(port, SCxSR); if (status & SCxSR_ERRORS(port)) { - sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); continue; } break; @@ -734,7 +689,7 @@ static int sci_poll_get_char(struct uart_port *port) /* Dummy read */ sci_serial_in(port, SCxSR); - sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); return c; } @@ -742,14 +697,16 @@ static int sci_poll_get_char(struct uart_port *port) static void sci_poll_put_char(struct uart_port *port, unsigned char c) { - unsigned short status; + struct sci_port *s = to_sci_port(port); + const struct sci_common_regs *regs = s->params->common_regs; + unsigned int status; do { - status = sci_serial_in(port, SCxSR); + status = s->ops->read_reg(port, regs->status); } while (!(status & SCxSR_TDxE(port))); sci_serial_out(port, SCxTDR, c); - sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); + s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); } #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ @@ -892,7 +849,7 @@ static void sci_transmit_chars(struct uart_port *port) port->icount.tx++; } while (--count > 0); - sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) uart_write_wakeup(port); @@ -911,6 +868,7 @@ static void sci_transmit_chars(struct uart_port *port) static void sci_receive_chars(struct uart_port *port) { struct tty_port *tport = &port->state->port; + struct sci_port *s = to_sci_port(port); int i, count, copied = 0; unsigned short status; unsigned char flag; @@ -965,7 +923,7 @@ static void sci_receive_chars(struct uart_port *port) } sci_serial_in(port, SCxSR); /* dummy read */ - sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); copied += count; port->icount.rx += count; @@ -978,16 +936,17 @@ static void sci_receive_chars(struct uart_port *port) /* TTY buffers full; read from RX reg to prevent lockup */ sci_serial_in(port, SCxRDR); sci_serial_in(port, SCxSR); /* dummy read */ - sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); } } static int sci_handle_errors(struct uart_port *port) { int copied = 0; - unsigned short status = sci_serial_in(port, SCxSR); - struct tty_port *tport = &port->state->port; struct sci_port *s = to_sci_port(port); + const struct sci_common_regs *regs = s->params->common_regs; + unsigned int status = s->ops->read_reg(port, regs->status); + struct tty_port *tport = &port->state->port; /* Handle overruns */ if (status & s->params->overrun_mask) { @@ -1146,7 +1105,7 @@ static void rx_fifo_timer_fn(struct timer_list *t) struct uart_port *port = &s->port; dev_dbg(port->dev, "Rx timed out\n"); - scif_set_rtrg(port, 1); + s->ops->set_rtrg(port, 1); } static ssize_t rx_fifo_trigger_show(struct device *dev, @@ -1171,9 +1130,9 @@ static ssize_t rx_fifo_trigger_store(struct device *dev, if (ret) return ret; - sci->rx_trigger = scif_set_rtrg(port, r); + sci->rx_trigger = sci->ops->set_rtrg(port, r); if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) - scif_set_rtrg(port, 1); + sci->ops->set_rtrg(port, 1); return count; } @@ -1216,7 +1175,7 @@ static ssize_t rx_fifo_timeout_store(struct device *dev, sci->hscif_tot = r << HSSCR_TOT_SHIFT; } else { sci->rx_fifo_timeout = r; - scif_set_rtrg(port, 1); + sci->ops->set_rtrg(port, 1); if (r > 0) timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); } @@ -1341,7 +1300,7 @@ static void sci_dma_rx_reenable_irq(struct sci_port *s) s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { enable_irq(s->irqs[SCIx_RXI_IRQ]); if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) - scif_set_rtrg(port, s->rx_trigger); + s->ops->set_rtrg(port, s->rx_trigger); else scr &= ~SCSCR_RDRQE; } @@ -1623,7 +1582,7 @@ static struct dma_chan *sci_request_dma_chan(struct uart_port *port, return chan; } -static void sci_request_dma(struct uart_port *port) +void sci_request_dma(struct uart_port *port) { struct sci_port *s = to_sci_port(port); struct tty_port *tport = &port->state->port; @@ -1711,7 +1670,7 @@ static void sci_request_dma(struct uart_port *port) } } -static void sci_free_dma(struct uart_port *port) +void sci_free_dma(struct uart_port *port) { struct sci_port *s = to_sci_port(port); @@ -1721,7 +1680,7 @@ static void sci_free_dma(struct uart_port *port) sci_dma_rx_release(s); } -static void sci_flush_buffer(struct uart_port *port) +void sci_flush_buffer(struct uart_port *port) { struct sci_port *s = to_sci_port(port); @@ -1750,11 +1709,11 @@ static void sci_dma_check_tx_occurred(struct sci_port *s) s->tx_occurred = true; } #else /* !CONFIG_SERIAL_SH_SCI_DMA */ -static inline void sci_request_dma(struct uart_port *port) +inline void sci_request_dma(struct uart_port *port) { } -static inline void sci_free_dma(struct uart_port *port) +inline void sci_free_dma(struct uart_port *port) { } @@ -1762,7 +1721,9 @@ static void sci_dma_check_tx_occurred(struct sci_port *s) { } -#define sci_flush_buffer NULL +inline void sci_flush_buffer(struct uart_port *port) +{ +} #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) @@ -1780,7 +1741,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { - scif_set_rtrg(port, 1); + s->ops->set_rtrg(port, 1); scr |= SCSCR_RIE; } else { scr |= SCSCR_RDRQE; @@ -1806,8 +1767,8 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) #endif if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { - if (!scif_rtrg_enabled(port)) - scif_set_rtrg(port, s->rx_trigger); + if (!s->ops->rtrg_enabled(port)) + s->ops->set_rtrg(port, s->rx_trigger); mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); @@ -1817,7 +1778,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) * of whether the I_IXOFF is set, otherwise, how is the interrupt * to be disabled? */ - sci_receive_chars(port); + s->ops->receive_chars(port); return IRQ_HANDLED; } @@ -1826,9 +1787,10 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr) { struct uart_port *port = ptr; unsigned long flags; + struct sci_port *s = to_sci_port(port); uart_port_lock_irqsave(port, &flags); - sci_transmit_chars(port); + s->ops->transmit_chars(port); uart_port_unlock_irqrestore(port, flags); return IRQ_HANDLED; @@ -1837,16 +1799,19 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr) static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) { struct uart_port *port = ptr; + struct sci_port *s = to_sci_port(port); + const struct sci_common_regs *regs = s->params->common_regs; unsigned long flags; - unsigned short ctrl; + u32 ctrl; if (port->type != PORT_SCI) return sci_tx_interrupt(irq, ptr); uart_port_lock_irqsave(port, &flags); - ctrl = sci_serial_in(port, SCSCR); - ctrl &= ~(SCSCR_TE | SCSCR_TEIE); - sci_serial_out(port, SCSCR, ctrl); + ctrl = s->ops->read_reg(port, regs->control); + + ctrl &= ~(s->params->param_bits.te_clear); + s->ops->write_reg(port, regs->control, ctrl); uart_port_unlock_irqrestore(port, flags); return IRQ_HANDLED; @@ -1855,6 +1820,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) static irqreturn_t sci_br_interrupt(int irq, void *ptr) { struct uart_port *port = ptr; + struct sci_port *s = to_sci_port(port); /* Handle BREAKs */ sci_handle_breaks(port); @@ -1862,7 +1828,7 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr) /* drop invalid character received before break was detected */ sci_serial_in(port, SCxRDR); - sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); return IRQ_HANDLED; } @@ -1890,15 +1856,15 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr) if (sci_handle_errors(port)) { /* discard character in rx buffer */ sci_serial_in(port, SCxSR); - sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); } } else { sci_handle_fifo_overrun(port); if (!s->chan_rx) - sci_receive_chars(port); + s->ops->receive_chars(port); } - sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); + s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); /* Kick the transmission */ if (!s->chan_tx) @@ -2059,7 +2025,7 @@ static int sci_request_irq(struct sci_port *port) return ret; } -static void sci_free_irq(struct sci_port *port) +void sci_free_irq(struct sci_port *port) { int i, j; @@ -2232,7 +2198,7 @@ static unsigned int sci_get_mctrl(struct uart_port *port) return mctrl; } -static void sci_enable_ms(struct uart_port *port) +void sci_enable_ms(struct uart_port *port) { mctrl_gpio_enable_ms(to_sci_port(port)->gpios); } @@ -2268,7 +2234,17 @@ static void sci_break_ctl(struct uart_port *port, int break_state) uart_port_unlock_irqrestore(port, flags); } -static int sci_startup(struct uart_port *port) +static void sci_shutdown_complete(struct uart_port *port) +{ + struct sci_port *s = to_sci_port(port); + u16 scr; + + scr = sci_serial_in(port, SCSCR); + sci_serial_out(port, SCSCR, + scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); +} + +int sci_startup(struct uart_port *port) { struct sci_port *s = to_sci_port(port); int ret; @@ -2291,7 +2267,6 @@ static void sci_shutdown(struct uart_port *port) { struct sci_port *s = to_sci_port(port); unsigned long flags; - u16 scr; dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); @@ -2301,13 +2276,7 @@ static void sci_shutdown(struct uart_port *port) uart_port_lock_irqsave(port, &flags); sci_stop_rx(port); sci_stop_tx(port); - /* - * Stop RX and TX, disable related interrupts, keep clock source - * and HSCIF TOT bits - */ - scr = sci_serial_in(port, SCSCR); - sci_serial_out(port, SCSCR, - scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); + s->ops->shutdown_complete(port); uart_port_unlock_irqrestore(port, flags); #ifdef CONFIG_SERIAL_SH_SCI_DMA @@ -2383,9 +2352,9 @@ static int sci_brg_calc(struct sci_port *s, unsigned int bps, } /* calculate sample rate, BRR, and clock select */ -static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, - unsigned int *brr, unsigned int *srr, - unsigned int *cks) +int sci_scbrr_calc(struct sci_port *s, unsigned int bps, + unsigned int *brr, unsigned int *srr, + unsigned int *cks) { unsigned long freq = s->clk_rates[SCI_FCK]; unsigned int sr, br, prediv, scrate, c; @@ -2462,9 +2431,9 @@ static void sci_reset(struct uart_port *port) if (reg->size) sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); - sci_clear_SCxSR(port, - SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & - SCxSR_BREAK_CLEAR(port)); + s->ops->clear_SCxSR(port, + SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & + SCxSR_BREAK_CLEAR(port)); if (sci_getreg(port, SCLSR)->size) { status = sci_serial_in(port, SCLSR); status &= ~(SCLSR_TO | SCLSR_ORER); @@ -2473,14 +2442,14 @@ static void sci_reset(struct uart_port *port) if (s->rx_trigger > 1) { if (s->rx_fifo_timeout) { - scif_set_rtrg(port, 1); + s->ops->set_rtrg(port, 1); timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); } else { if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) - scif_set_rtrg(port, 1); + s->ops->set_rtrg(port, 1); else - scif_set_rtrg(port, s->rx_trigger); + s->ops->set_rtrg(port, s->rx_trigger); } } } @@ -2740,7 +2709,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, sci_enable_ms(port); } -static void sci_pm(struct uart_port *port, unsigned int state, +void sci_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) { struct sci_port *sci_port = to_sci_port(port); @@ -2803,7 +2772,7 @@ static int sci_remap_port(struct uart_port *port) return 0; } -static void sci_release_port(struct uart_port *port) +void sci_release_port(struct uart_port *port) { struct sci_port *sport = to_sci_port(port); @@ -2815,7 +2784,7 @@ static void sci_release_port(struct uart_port *port) release_mem_region(port->mapbase, sport->reg_size); } -static int sci_request_port(struct uart_port *port) +int sci_request_port(struct uart_port *port) { struct resource *res; struct sci_port *sport = to_sci_port(port); @@ -2837,7 +2806,7 @@ static int sci_request_port(struct uart_port *port) return 0; } -static void sci_config_port(struct uart_port *port, int flags) +void sci_config_port(struct uart_port *port, int flags) { if (flags & UART_CONFIG_TYPE) { struct sci_port *sport = to_sci_port(port); @@ -2847,7 +2816,7 @@ static void sci_config_port(struct uart_port *port, int flags) } } -static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) +int sci_verify_port(struct uart_port *port, struct serial_struct *ser) { if (ser->baud_base < 2400) /* No paper tape reader for Mitch.. */ @@ -2856,6 +2825,18 @@ static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) return 0; } +static u32 sci_get_ctrl_temp(struct uart_port *port, unsigned int ctrl) +{ + struct sci_port *s = to_sci_port(port); + unsigned int ctrl_temp; + + ctrl_temp = s->params->param_bits.rxtx_enable; + ctrl_temp |= + (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | + (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); + return ctrl_temp; +} + static const struct uart_ops sci_uart_ops = { .tx_empty = sci_tx_empty, .set_mctrl = sci_set_mctrl, @@ -2881,6 +2862,19 @@ static const struct uart_ops sci_uart_ops = { #endif }; +static const struct sci_port_ops sci_port_ops = { + .read_reg = sci_serial_in, + .write_reg = sci_serial_out, + .receive_chars = sci_receive_chars, + .transmit_chars = sci_transmit_chars, + .poll_put_char = sci_poll_put_char, + .clear_SCxSR = sci_clear_SCxSR, + .set_rtrg = scif_set_rtrg, + .rtrg_enabled = scif_rtrg_enabled, + .shutdown_complete = sci_shutdown_complete, + .get_ctrl_temp = sci_get_ctrl_temp, +}; + static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) { const char *clk_names[] = { @@ -2974,6 +2968,7 @@ static int sci_init_single(struct platform_device *dev, int ret; sci_port->cfg = p; + sci_port->ops = &sci_port_ops; port->ops = &sci_uart_ops; port->iotype = UPIO_MEM; @@ -3095,7 +3090,7 @@ static void sci_cleanup_single(struct sci_port *port) defined(CONFIG_SERIAL_SH_SCI_EARLYCON) static void serial_console_putchar(struct uart_port *port, unsigned char ch) { - sci_poll_put_char(port, ch); + to_sci_port(port)->ops->poll_put_char(port, ch); } /* @@ -3107,7 +3102,9 @@ static void serial_console_write(struct console *co, const char *s, { struct sci_port *sci_port = &sci_ports[co->index]; struct uart_port *port = &sci_port->port; - unsigned short bits, ctrl, ctrl_temp; + const struct sci_common_regs *regs = sci_port->params->common_regs; + unsigned int bits; + u32 ctrl, ctrl_temp; unsigned long flags; int locked = 1; @@ -3119,21 +3116,22 @@ static void serial_console_write(struct console *co, const char *s, uart_port_lock_irqsave(port, &flags); /* first save SCSCR then disable interrupts, keep clock source */ - ctrl = sci_serial_in(port, SCSCR); - ctrl_temp = SCSCR_RE | SCSCR_TE | - (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | - (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); - sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); + ctrl = sci_port->ops->read_reg(port, regs->control); + ctrl_temp = sci_port->ops->get_ctrl_temp(port, ctrl); + + sci_port->ops->write_reg(port, regs->control, ctrl_temp | sci_port->hscif_tot); uart_console_write(port, s, count, serial_console_putchar); /* wait until fifo is empty and last bit has been transmitted */ - bits = SCxSR_TDxE(port) | SCxSR_TEND(port); - while ((sci_serial_in(port, SCxSR) & bits) != bits) + + bits = sci_ports->params->param_bits.poll_sent_bits; + + while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits) cpu_relax(); /* restore the SCSCR */ - sci_serial_out(port, SCSCR, ctrl); + sci_port->ops->write_reg(port, regs->control, ctrl); if (locked) uart_port_unlock_irqrestore(port, flags); @@ -3268,7 +3266,6 @@ static void sci_remove(struct platform_device *dev) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); } - #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) @@ -3564,9 +3561,11 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver, #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON static struct plat_sci_port port_cfg __initdata; -static int __init early_console_setup(struct earlycon_device *device, +int __init early_console_setup(struct earlycon_device *device, int type) { + const struct sci_common_regs *regs; + if (!device->port.membase) return -ENODEV; @@ -3574,10 +3573,14 @@ static int __init early_console_setup(struct earlycon_device *device, memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); port_cfg.type = type; sci_ports[0].cfg = &port_cfg; + sci_ports[0].ops = &sci_port_ops; sci_ports[0].params = sci_probe_regmap(&port_cfg); - port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); - sci_serial_out(&sci_ports[0].port, SCSCR, - SCSCR_RE | SCSCR_TE | port_cfg.scscr); + regs = sci_ports[0].params->common_regs; + + port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control); + sci_ports[0].ops->write_reg(&sci_ports[0].port, + regs->control, + sci_ports[0].params->param_bits.rxtx_enable | port_cfg.scscr); device->con->write = serial_console_write; return 0; diff --git a/drivers/tty/serial/sh-sci_common.h b/drivers/tty/serial/sh-sci_common.h new file mode 100644 index 000000000000..cbfacdc1a836 --- /dev/null +++ b/drivers/tty/serial/sh-sci_common.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __SH_SCI_COMMON_H__ +#define __SH_SCI_COMMON_H__ + +#define SCI_MAJOR 204 +#define SCI_MINOR_START 8 + +#include + +enum SCI_CLKS { + SCI_FCK, /* Functional Clock */ + SCI_SCK, /* Optional External Clock */ + SCI_BRG_INT, /* Optional BRG Internal Clock Source */ + SCI_SCIF_CLK, /* Optional BRG External Clock Source */ + SCI_NUM_CLKS +}; + +/* Offsets into the sci_port->irqs array */ +enum { + SCIx_ERI_IRQ, + SCIx_RXI_IRQ, + SCIx_TXI_IRQ, + SCIx_BRI_IRQ, + SCIx_DRI_IRQ, + SCIx_TEI_IRQ, + SCIx_NR_IRQS, + + SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ +}; + +/* Bit x set means sampling rate x + 1 is supported */ +#define SCI_SR(x) BIT((x) - 1) + +extern void sci_release_port(struct uart_port *port); +extern int sci_request_port(struct uart_port *port); +extern void sci_config_port(struct uart_port *port, int flags); +extern int sci_verify_port(struct uart_port *port, struct serial_struct *ser); +extern void sci_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate); +extern void sci_enable_ms(struct uart_port *port); + +#ifdef CONFIG_CONSOLE_POLL +extern int sci_poll_get_char(struct uart_port *port); +extern void sci_poll_put_char(struct uart_port *port, unsigned char c); +#endif /* CONFIG_CONSOLE_POLL */ + +struct plat_sci_reg { + u8 offset, size; +}; + +/* The actual number of needed registers depends on the sci controller; + * using this value as a max covers both sci and rsci cases + */ +#define SCI_NR_REGS 20 + +struct sci_port_params_bits { + unsigned int rxtx_enable; + unsigned int te_clear; + unsigned int poll_sent_bits; +}; + +struct sci_common_regs { + unsigned int status; + unsigned int control; +}; + +struct sci_port_params { + const struct plat_sci_reg regs[SCI_NR_REGS]; + const struct sci_common_regs *common_regs; + unsigned int fifosize; + unsigned int overrun_reg; + unsigned int overrun_mask; + unsigned int sampling_rate_mask; + unsigned int error_mask; + unsigned int error_clear; + struct sci_port_params_bits param_bits; +}; + +struct sci_port_ops { + u32 (*read_reg)(struct uart_port *port, int reg); + void (*write_reg)(struct uart_port *port, int reg, int value); + void (*clear_SCxSR)(struct uart_port *port, unsigned int mask); + + void (*transmit_chars)(struct uart_port *port); + void (*receive_chars)(struct uart_port *port); + + void (*poll_put_char)(struct uart_port *port, unsigned char c); + + int (*set_rtrg)(struct uart_port *port, int rx_trig); + int (*rtrg_enabled)(struct uart_port *port); + + void (*shutdown_complete)(struct uart_port *port); + + unsigned int (*get_ctrl_temp)(struct uart_port *port, unsigned int ctrl); +}; + +struct sci_of_data { + const struct sci_port_params *params; + const struct uart_ops *uart_ops; + const struct sci_port_ops *ops; + unsigned short regtype; + unsigned short type; +}; + +struct sci_port { + struct uart_port port; + + /* Platform configuration */ + const struct sci_port_params *params; + const struct plat_sci_port *cfg; + + unsigned int sampling_rate_mask; + resource_size_t reg_size; + struct mctrl_gpios *gpios; + + /* Clocks */ + struct clk *clks[SCI_NUM_CLKS]; + unsigned long clk_rates[SCI_NUM_CLKS]; + + int irqs[SCIx_NR_IRQS]; + char *irqstr[SCIx_NR_IRQS]; + + struct dma_chan *chan_tx; + struct dma_chan *chan_rx; + +#ifdef CONFIG_SERIAL_SH_SCI_DMA + struct dma_chan *chan_tx_saved; + struct dma_chan *chan_rx_saved; + dma_cookie_t cookie_tx; + dma_cookie_t cookie_rx[2]; + dma_cookie_t active_rx; + dma_addr_t tx_dma_addr; + unsigned int tx_dma_len; + struct scatterlist sg_rx[2]; + void *rx_buf[2]; + size_t buf_len_rx; + struct work_struct work_tx; + struct hrtimer rx_timer; + unsigned int rx_timeout; /* microseconds */ +#endif + unsigned int rx_frame; + int rx_trigger; + struct timer_list rx_fifo_timer; + int rx_fifo_timeout; + u16 hscif_tot; + + const struct sci_port_ops *ops; + + bool has_rtscts; + bool autorts; + bool tx_occurred; +}; + +#define to_sci_port(uart) container_of((uart), struct sci_port, port) + +extern int sci_scbrr_calc(struct sci_port *s, unsigned int bps, + unsigned int *brr, unsigned int *srr, + unsigned int *cks); + +extern void sci_port_disable(struct sci_port *sci_port); +extern void sci_port_enable(struct sci_port *sci_port); + +extern int sci_startup(struct uart_port *port); +extern void sci_free_irq(struct sci_port *port); + +extern void sci_request_dma(struct uart_port *port); +extern void sci_free_dma(struct uart_port *port); +extern void sci_flush_buffer(struct uart_port *port); + +#define min_sr(_port) ffs((_port)->sampling_rate_mask) +#define max_sr(_port) fls((_port)->sampling_rate_mask) + +#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON +extern int __init early_console_setup(struct earlycon_device *device, int); +#endif + +#endif /* __SH_SCI_COMMON_H__ */ From patchwork Wed Jan 29 16:37:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 860805 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 438E91E25FF; Wed, 29 Jan 2025 16:52:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169554; cv=none; b=i4KwO+Fc7e9DUkRdCEDb8gzSG0xezoDTWL8Pf5kolAKrquF3CjfJ0WzTDEMOOUKxavSPX6e41Xo1jF4DaOoyoXZ4h/P0StdVGWl848bK46JqnnhhDN7pCbJ8g9rOxyJ9qMXO9h0G3J4PP78qMFVCahYCU3X8Uj9smIqJhBwuIAY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169554; c=relaxed/simple; bh=NEZcXEKcNfK0D22Bwje0WD2wbRhNaJxAFpSiFUDyiFE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s+Xi3wWM3SBA4AIsUBodhRbVjjV08ucT6SqObUd0rnb51zwc/9Fh6zU1q6gF5JsP8Hm1OhZIpvq4Xmvgh8mFeR8H4StcVjt7TP4oDRgjyYT7WurQV6GStN0INbeyOU+cDGspSCWx7PTej2FxJqz3wVwQJLa2mOlbTqDj78kBfgw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: g9b1VeC9QeqO89iBSK4eHA== X-CSE-MsgGUID: pz/FqopDTDC2N5YY+9oKmQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:32 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1A633402E096; Thu, 30 Jan 2025 01:52:29 +0900 (JST) From: Thierry Bultel To: Greg Kroah-Hartman , Jiri Slaby Cc: Thierry Bultel , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 10/14] serial: sh-sci: Introduced sci_of_data Date: Wed, 29 Jan 2025 16:37:46 +0000 Message-ID: <20250129165122.2980-11-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The aim here is to provide an easier support to more different SCI controllers, like the RZ/T2H one. The existing .data field of_sci_match is changed to a structure containing all what that can be statically initialized, and avoid a call to 'sci_probe_regmap', in both 'sci_init_single', and 'early_console_setup'. 'sci_probe_regmap' is now assumed to be called in the only case where the device description is from a board file instead of a dts. In this way, there is no need to patch 'sci_probe_regmap' for adding new SCI type, and also, the specific sci_port_params for a new SCI type can be provided by an external file. Signed-off-by: Thierry Bultel --- drivers/tty/serial/sh-sci.c | 64 +++++++++++++++++++----------- drivers/tty/serial/sh-sci_common.h | 3 +- 2 files changed, 43 insertions(+), 24 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 1b83a246c7ed..c58c0793c521 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2968,9 +2968,7 @@ static int sci_init_single(struct platform_device *dev, int ret; sci_port->cfg = p; - sci_port->ops = &sci_port_ops; - port->ops = &sci_uart_ops; port->iotype = UPIO_MEM; port->line = index; port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); @@ -3010,7 +3008,16 @@ static int sci_init_single(struct platform_device *dev, for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) sci_port->irqs[i] = sci_port->irqs[0]; - sci_port->params = sci_probe_regmap(p); + /* + * sci_port->params params can be NULL when using a board file instead + * of a dts. + */ + if (sci_port->params == NULL) { + sci_port->params = sci_probe_regmap(p); + if (unlikely(sci_port->params == NULL)) + return -EINVAL; + } + if (unlikely(sci_port->params == NULL)) return -EINVAL; @@ -3266,9 +3273,14 @@ static void sci_remove(struct platform_device *dev) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); } -#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) -#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) -#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) +#define SCI_OF_DATA(_type, _regtype) (\ +&(struct sci_of_data) {\ + .type = (_type), \ + .regtype = (_regtype),\ + .ops = &sci_port_ops,\ + .uart_ops = &sci_uart_ops,\ + .params = &sci_port_params[_regtype],\ +}) static const struct of_device_id of_sci_match[] __maybe_unused = { /* SoC-specific types */ @@ -3336,7 +3348,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, struct reset_control *rstc; struct plat_sci_port *p; struct sci_port *sp; - const void *data; + const struct sci_of_data *data; int id, ret; if (!IS_ENABLED(CONFIG_OF) || !np) @@ -3382,8 +3394,12 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, sp = &sci_ports[id]; *dev_id = id; - p->type = SCI_OF_TYPE(data); - p->regtype = SCI_OF_REGTYPE(data); + p->type = data->type; + p->regtype = data->regtype; + + sp->ops = data->ops; + sp->port.ops = data->uart_ops; + sp->params = data->params; sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); @@ -3562,19 +3578,23 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver, static struct plat_sci_port port_cfg __initdata; int __init early_console_setup(struct earlycon_device *device, - int type) + const struct sci_of_data *data) { const struct sci_common_regs *regs; if (!device->port.membase) return -ENODEV; - device->port.type = type; + device->port.type = data->type; memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); - port_cfg.type = type; + + port_cfg.type = data->type; + port_cfg.regtype = data->regtype; + sci_ports[0].cfg = &port_cfg; - sci_ports[0].ops = &sci_port_ops; - sci_ports[0].params = sci_probe_regmap(&port_cfg); + sci_ports[0].params = data->params; + sci_ports[0].ops = data->ops; + sci_ports[0].port.ops = data->uart_ops; regs = sci_ports[0].params->common_regs; port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control); @@ -3588,41 +3608,39 @@ int __init early_console_setup(struct earlycon_device *device, static int __init sci_early_console_setup(struct earlycon_device *device, const char *opt) { - return early_console_setup(device, PORT_SCI); + return early_console_setup(device, SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE)); } static int __init scif_early_console_setup(struct earlycon_device *device, const char *opt) { - return early_console_setup(device, PORT_SCIF); + return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE)); } static int __init rzscifa_early_console_setup(struct earlycon_device *device, const char *opt) { - port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; - return early_console_setup(device, PORT_SCIF); + return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE)); } static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, const char *opt) { - port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE; - return early_console_setup(device, PORT_SCIF); + return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE)); } static int __init scifa_early_console_setup(struct earlycon_device *device, const char *opt) { - return early_console_setup(device, PORT_SCIFA); + return early_console_setup(device, SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE)); } static int __init scifb_early_console_setup(struct earlycon_device *device, const char *opt) { - return early_console_setup(device, PORT_SCIFB); + return early_console_setup(device, SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE)); } static int __init hscif_early_console_setup(struct earlycon_device *device, const char *opt) { - return early_console_setup(device, PORT_HSCIF); + return early_console_setup(device, SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE)); } OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); diff --git a/drivers/tty/serial/sh-sci_common.h b/drivers/tty/serial/sh-sci_common.h index cbfacdc1a836..f75c185079dd 100644 --- a/drivers/tty/serial/sh-sci_common.h +++ b/drivers/tty/serial/sh-sci_common.h @@ -172,7 +172,8 @@ extern void sci_flush_buffer(struct uart_port *port); #define max_sr(_port) fls((_port)->sampling_rate_mask) #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON -extern int __init early_console_setup(struct earlycon_device *device, int); +extern int __init early_console_setup(struct earlycon_device *device, + const struct sci_of_data *data); #endif #endif /* __SH_SCI_COMMON_H__ */ From patchwork Wed Jan 29 16:37:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 860967 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 980111DFE00; Wed, 29 Jan 2025 16:52:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169573; cv=none; b=Chgq9IV6D5IXS9wyEWXDPKdzj37PaIZBmljrvFFup3dhXMO/PbcS+hs/u/X/lYxKxKd7nvp6pEAwOGzCOcJSIdYVm4xhg1RtbV44tkHHo9eHSiirTdU1nKXFxf09kpdCOKc1NZPSpmq3cEk80m5B8FXfXLfPnpaL6EDra4hOdes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169573; c=relaxed/simple; bh=JtZF8ugO/61EyziPZ0gtYSMUvhyvDZKGJxzPvfsM6HA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nyFw48X8LF0kGJTQsBgJbr+PuWwoQS/yRwv7DENOem5xk7jJuaL3D9zwwzHIpLjSjFChtf44aXDTiUoKzxvmQSlHIGF15ykEnxgwgSNEGQG9emyJZspJJok7aaF5vpkMshPH+8J1Qj4UX2BcoYjU1wFVXh2jQPlNFF7NqHS8QPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: r0C+xfkESVemYdAI28xLBQ== X-CSE-MsgGUID: 6APepqd8TLOvZc05OxeGLQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:49 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E5CD7402D14A; Thu, 30 Jan 2025 01:52:35 +0900 (JST) From: Thierry Bultel To: Greg Kroah-Hartman , Jiri Slaby , Geert Uytterhoeven , Magnus Damm Cc: Thierry Bultel , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 11/14] serial: sh-sci: Add support for RZ/T2H SCI Date: Wed, 29 Jan 2025 16:37:47 +0000 Message-ID: <20250129165122.2980-12-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define a new RZSCI port type, and the RSCI 32 bits registers set. The RZ/T2H SCI has a a fifo, and a quite different set of registers from the orginal SH SCI ones. DMA is not supported yet. Signed-off-by: Thierry Bultel --- drivers/tty/serial/Kconfig | 7 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/rzsci.c | 484 +++++++++++++++++++++++++++++++ drivers/tty/serial/rzsci.h | 12 + drivers/tty/serial/sh-sci.c | 20 +- include/linux/serial_sci.h | 3 +- include/uapi/linux/serial_core.h | 3 + 7 files changed, 524 insertions(+), 6 deletions(-) create mode 100644 drivers/tty/serial/rzsci.c create mode 100644 drivers/tty/serial/rzsci.h diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 45f0f779fbf9..72b563f2e9ba 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -671,6 +671,13 @@ config SERIAL_SH_SCI_DMA depends on SERIAL_SH_SCI && DMA_ENGINE default ARCH_RENESAS +config SERIAL_RZ_SCI + tristate "Support for Renesas RZ/T2H SCI variant" + depends on SERIAL_SH_SCI + help + Support for the RZ/T2H SCI variant with fifo. + Say Y if you want to be able to the RZ/T2H SCI serial port. + config SERIAL_HS_LPC32XX tristate "LPC32XX high speed serial port support" depends on ARCH_LPC32XX || COMPILE_TEST diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 6ff74f0a9530..537e0a0fc047 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o obj-$(CONFIG_SERIAL_QE) += ucc_uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o obj-$(CONFIG_SERIAL_RP2) += rp2.o +obj-$(CONFIG_SERIAL_RZ_SCI) += rzsci.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o diff --git a/drivers/tty/serial/rzsci.c b/drivers/tty/serial/rzsci.c new file mode 100644 index 000000000000..7a6452600123 --- /dev/null +++ b/drivers/tty/serial/rzsci.c @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include "rzsci.h" + +/* RSCI registers */ +#define RDR 0x00 +#define TDR 0x04 +#define CCR0 0x08 +#define CCR1 0x0C +#define CCR2 0x10 +#define CCR3 0x14 +#define CCR4 0x18 +#define FCR 0x24 +#define DCR 0x30 +#define CSR 0x48 +#define FRSR 0x50 +#define FTSR 0x54 +#define CFCLR 0x68 +#define FFCLR 0x70 + +/* RDR (Receive Data Register) */ +#define RDR_FER BIT(28) /* Framing Error */ +#define RDR_PER BIT(27) /* Parity Error */ +#define RDR_ORER BIT(24) /* Overrun Error */ +#define RDR_FFER BIT(12) /* FIFO Framing Error */ +#define RDR_FPER BIT(11) /* FIFO Parity Error */ +#define RDR_DR BIT(10) /* Incoming Data Ready */ +#define RDR_MPB BIT(9) /* Multiprocessor Bit */ +#define RDR_RDAT_MSK GENMASK(8, 0) + +/* TDR (Transmit Data Register) */ +#define TDR_MPBT BIT(9) /* Multiprocessor Transfer */ +#define TDR_TDAT_9BIT_LSHIFT 0 +#define TDR_TDAT_9BIT_VAL 0x1FF +#define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT) + +/* CCR0 (Common Control Register 0) */ +#define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ +#define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ +#define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */ +#define CCR0_RIE BIT(16) /* Receive Interrupt Enable */ +#define CCR0_IDSEL BIT(10) /* ID Frame Select */ +#define CCR0_DCME BIT(9) /* Data Compare Match Enable */ +#define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */ +#define CCR0_TE BIT(4) /* Transmit Enable */ +#define CCR0_RE BIT(0) /* Receive Enable */ + +/* CCR1 (Common Control Register 1) */ +#define CCR1_NFEN BIT(28) /* Digital Noise Filter Function */ +#define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */ +#define CCR1_SPLP BIT(16) /* Loopback Control */ +#define CCR1_RINV BIT(13) /* RxD invert */ +#define CCR1_TINV BIT(12) /* TxD invert */ +#define CCR1_PM BIT(9) /* Parity Mode */ +#define CCR1_PE BIT(8) /* Parity Enable */ +#define CCR1_SPB2IO BIT(5) /* Serial Port Break I/O */ +#define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */ +#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ +#define CCR1_CTSE BIT(0) /* CTS Enable */ + +/* CCR2 (Common Control Register 2) */ +#define CCR2_INIT 0xFF000004 +#define CCR2_CKS_TCLK (0) /* TCLK clock */ +#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ +#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ +#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ +#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ +#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */ +#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ +#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */ + +/* CCR3 (Common Control Register 3) */ +#define CCR3_INIT 0x1283 +#define CCR3_BLK BIT(29) /* Block Transfer Mode */ +#define CCR3_GM BIT(28) /* GSM Mode */ +#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ +#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ +#define CCR3_DEN BIT(21) /* Driver Enabled */ +#define CCR3_FM BIT(20) /* FIFO Mode Select */ +#define CCR3_MP BIT(19) /* Multi-Processor Mode */ +#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ +#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */ +#define CCR3_STP BIT(14) /* Stop bit Length */ +#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ +#define CCR3_LSBF BIT(12) /* LSB First select */ +#define CCR3_CHR1 BIT(9) /* Character Length */ +#define CCR3_CHR0 BIT(8) /* Character Length */ +#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ +#define CCR3_CPOL BIT(1) /* Clock Polarity Select */ +#define CCR3_CPHA BIT(0) /* Clock Phase Select */ + +/* FCR (FIFO Control Register) */ +#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ +#define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ +#define FCR_DRES BIT(0) /* Incoming Data Ready Error Select */ +#define FCR_RTRG4_0 GENMASK(20, 16) +#define FCR_TTRG GENMASK(12, 8) + +/* CSR (Common Status Register) */ +#define CSR_RDRF BIT(31) /* Receive Data Full */ +#define CSR_TEND BIT(30) /* Transmit End Flag */ +#define CSR_TDRE BIT(29) /* Transmit Data Empty */ +#define CSR_FER BIT(28) /* Framing Error */ +#define CSR_PER BIT(27) /* Parity Error */ +#define CSR_MFF BIT(26) /* Mode Fault Error */ +#define CSR_ORER BIT(24) /* Overrun Error */ +#define CSR_DFER BIT(18) /* Data Compare Match Framing Error */ +#define CSR_DPER BIT(17) /* Data Compare Match Parity Error */ +#define CSR_DCMF BIT(16) /* Data Compare Match */ +#define CSR_RXDMON BIT(15) /* Serial Input Data Monitor */ +#define CSR_ERS BIT(4) /* Error Signal Status */ + +#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) +#define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear) + +#define RSCI_DEFAULT_ERROR_MASK (CSR_PER | CSR_FER) + +#define RSCI_RDxF_CLEAR (CFCLR_RDRFC) +#define RSCI_ERROR_CLEAR (CFCLR_PERC | CFCLR_FERC) +#define RSCI_TDxE_CLEAR (CFCLR_TDREC) +#define RSCI_BREAK_CLEAR (CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC) + +/* FRSR (FIFO Receive Status Register) */ +#define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */ +#define FRSR_DR BIT(0) /* Receive Data Ready */ + +/* CFCLR (Common Flag CLear Register) */ +#define CFCLR_RDRFC BIT(31) /* RDRF Clear */ +#define CFCLR_TDREC BIT(29) /* TDRE Clear */ +#define CFCLR_FERC BIT(28) /* FER Clear */ +#define CFCLR_PERC BIT(27) /* PER Clear */ +#define CFCLR_MFFC BIT(26) /* MFF Clear */ +#define CFCLR_ORERC BIT(24) /* ORER Clear */ +#define CFCLR_DFERC BIT(18) /* DFER Clear */ +#define CFCLR_DPERC BIT(17) /* DPER Clear */ +#define CFCLR_DCMFC BIT(16) /* DCMF Clear */ +#define CFCLR_ERSC BIT(4) /* ERS Clear */ +#define CFCLR_CLRFLAG (CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \ + CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \ + CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC) + +/* FFCLR (FIFO Flag CLear Register) */ +#define FFCLR_DRC BIT(0) /* DR Clear */ + +#define DCR_DEPOL BIT(0) + +static u32 rzsci_serial_in(struct uart_port *p, int offset) +{ + return ioread32(p->membase + offset); +} + +static void rzsci_serial_out(struct uart_port *p, int offset, int value) +{ + iowrite32(value, p->membase + offset); +} + +static void rzsci_clear_DRxC(struct uart_port *port) +{ + rzsci_serial_out(port, CFCLR, CFCLR_RDRFC); + rzsci_serial_out(port, FFCLR, FFCLR_DRC); +} + +static void rzsci_clear_SCxSR(struct uart_port *port, unsigned int mask) +{ + rzsci_serial_out(port, CFCLR, mask); +} + +static void rzsci_start_rx(struct uart_port *port) +{ + unsigned int ctrl; + + ctrl = rzsci_serial_in(port, CCR0); + ctrl |= CCR0_RIE; + rzsci_serial_out(port, CCR0, ctrl); +} + +static void rzsci_set_termios(struct uart_port *port, struct ktermios *termios, + const struct ktermios *old) +{ + struct sci_port *s = to_sci_port(port); + unsigned long flags; + + /* + * For now, only RX enabling is supported + */ + + sci_port_enable(s); + uart_port_lock_irqsave(port, &flags); + + if (termios->c_cflag & CREAD) + rzsci_start_rx(port); + + uart_port_unlock_irqrestore(port, flags); + sci_port_disable(s); +} + +static int rzsci_txfill(struct uart_port *port) +{ + return rzsci_serial_in(port, FTSR); +} + +static int rzsci_rxfill(struct uart_port *port) +{ + u32 val = rzsci_serial_in(port, FRSR); + return FIELD_GET(FRSR_R5_0, val); +} + +static unsigned int rzsci_tx_empty(struct uart_port *port) +{ + unsigned int status = rzsci_serial_in(port, CSR); + unsigned int in_tx_fifo = rzsci_txfill(port); + + return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0; +} + +static void rzsci_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + /* not supported yet */ + return; +} + +static unsigned int rzsci_get_mctrl(struct uart_port *port) +{ + /* not supported yet */ + return 0; +} + +static void rzsci_clear_CFC(struct uart_port *port, unsigned int mask) +{ + rzsci_serial_out(port, CFCLR, mask); +} + +static void rzsci_start_tx(struct uart_port *port) +{ + struct sci_port *sp = to_sci_port(port); + u32 ctrl; + + if (sp->chan_tx) + return; + + /* + * TE (Transmit Enable) must be set after setting TIE + * (Transmit Interrupt Enable) or in the same instruction + * to start the transmit process. + */ + ctrl = rzsci_serial_in(port, CCR0); + ctrl |= CCR0_TIE | CCR0_TE; + rzsci_serial_out(port, CCR0, ctrl); +} + +static void rzsci_stop_tx(struct uart_port *port) +{ + u32 ctrl; + + ctrl = rzsci_serial_in(port, CCR0); + ctrl &= ~CCR0_TIE; + + rzsci_serial_out(port, CCR0, ctrl); +} + +static void rzsci_stop_rx(struct uart_port *port) +{ + u32 ctrl; + + ctrl = rzsci_serial_in(port, CCR0); + ctrl &= ~CCR0_RIE; + + rzsci_serial_out(port, CCR0, ctrl); +} + +static int rzsci_txroom(struct uart_port *port) +{ + return port->fifosize - rzsci_txfill(port); +} + +static void rzsci_transmit_chars(struct uart_port *port) +{ + struct tty_port *tport = &port->state->port; + unsigned int stopped = uart_tx_stopped(port); + u32 status, ctrl; + int count; + + status = rzsci_serial_in(port, CSR); + if (!(status & CSR_TDRE)) { + ctrl = rzsci_serial_in(port, CCR0); + if (kfifo_is_empty(&tport->xmit_fifo)) + ctrl &= ~CCR0_TIE; + else + ctrl |= CCR0_TIE; + rzsci_serial_out(port, CCR0, ctrl); + return; + } + + count = rzsci_txroom(port); + + do { + unsigned char c; + + if (port->x_char) { + c = port->x_char; + port->x_char = 0; + } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) + break; + + rzsci_clear_CFC(port, CFCLR_TDREC); + rzsci_serial_out(port, TDR, c); + + port->icount.tx++; + } while (--count > 0); + + if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (kfifo_is_empty(&tport->xmit_fifo)) { + ctrl = rzsci_serial_in(port, CCR0); + ctrl &= ~CCR0_TIE; + ctrl |= CCR0_TEIE; + rzsci_serial_out(port, CCR0, ctrl); + } +} + +static void rzsci_receive_chars(struct uart_port *port) +{ + struct tty_port *tport = &port->state->port; + int i, count, copied = 0; + u32 status, frsr_status = 0; + unsigned char flag; + + status = rzsci_serial_in(port, CSR); + frsr_status = rzsci_serial_in(port, FRSR); + + if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR)) + return; + + while (1) { + /* Don't copy more bytes than there is room for in the buffer */ + count = tty_buffer_request_room(tport, rzsci_rxfill(port)); + + /* If for any reason we can't copy more data, we're done! */ + if (count == 0) + break; + + for (i = 0; i < count; i++) { + char c; + + status = rzsci_serial_in(port, CSR); + c = rzsci_serial_in(port, RDR) & RDR_RDAT_MSK; + + if (uart_handle_sysrq_char(port, c)) { + count--; + i--; + continue; + } + + /* Store data and status */ + if (status & CSR_FER) { + flag = TTY_FRAME; + port->icount.frame++; + } else if (status & CSR_PER) { + flag = TTY_PARITY; + port->icount.parity++; + } else + flag = TTY_NORMAL; + + tty_insert_flip_char(tport, c, flag); + } + + rzsci_serial_in(port, CSR); /* dummy read */ + rzsci_clear_DRxC(port); + + copied += count; + port->icount.rx += count; + } + + if (copied) { + /* Tell the rest of the system the news. New characters! */ + tty_flip_buffer_push(tport); + } else { + /* TTY buffers full; read from RX reg to prevent lockup */ + rzsci_serial_in(port, RDR); + rzsci_serial_in(port, CSR); /* dummy read */ + rzsci_clear_DRxC(port); + } +} + +static void rzsci_poll_put_char(struct uart_port *port, unsigned char c) +{ + u32 status; + + do { + status = rzsci_serial_in(port, CSR); + } while (!(status & CSR_TDRE)); + + rzsci_serial_out(port, TDR, c); + rzsci_clear_SCxSR(port, CFCLR_TDREC); + return; +} + +static unsigned int rzci_get_ctrl_temp(struct uart_port *port, unsigned int) +{ + struct sci_port *s = to_sci_port(port); + + return s->params->param_bits.rxtx_enable | CCR0_TIE; +} + +static const char *rzsci_type(struct uart_port *port) +{ + return "rzsci"; +} + +static const struct sci_common_regs rzsci_common_regs = { + .status = CSR, + .control = CCR0, +}; + +static const struct sci_port_params_bits rzsci_port_param_bits = { + .rxtx_enable = CCR0_RE | CCR0_TE, + .te_clear = CCR0_TE | CCR0_TEIE, + .poll_sent_bits = CSR_TDRE | CSR_TEND, +}; + +static const struct sci_port_params rzsci_port_params = { + .fifosize = 16, + .overrun_reg = CSR, + .overrun_mask = CSR_ORER, + .sampling_rate_mask = SCI_SR(32), + .error_mask = RSCI_DEFAULT_ERROR_MASK, + .error_clear = RSCI_ERROR_CLEAR, + .param_bits = rzsci_port_param_bits, + .common_regs = &rzsci_common_regs, +}; + +static const struct uart_ops rzt2_sci_uart_ops = { + .tx_empty = rzsci_tx_empty, + .set_mctrl = rzsci_set_mctrl, + .get_mctrl = rzsci_get_mctrl, + .start_tx = rzsci_start_tx, + .stop_tx = rzsci_stop_tx, + .stop_rx = rzsci_stop_rx, + .startup = sci_startup, + .flush_buffer = sci_flush_buffer, + .set_termios = rzsci_set_termios, + .pm = sci_pm, + .type = rzsci_type, + .release_port = sci_release_port, + .request_port = sci_request_port, + .config_port = sci_config_port, + .verify_port = sci_verify_port, +}; + +static const struct sci_port_ops rzsci_port_ops = { + .read_reg = rzsci_serial_in, + .write_reg = rzsci_serial_out, + .clear_SCxSR = rzsci_clear_SCxSR, + .transmit_chars = rzsci_transmit_chars, + .receive_chars = rzsci_receive_chars, + .poll_put_char = rzsci_poll_put_char, + .get_ctrl_temp = rzci_get_ctrl_temp, +}; + +struct sci_of_data sci_r9a09g077_data = { + .type = PORT_RZSCI, + .regtype = SCIx_RZT2H_SCI_REGTYPE, + .ops = &rzsci_port_ops, + .uart_ops = &rzt2_sci_uart_ops, + .params = &rzsci_port_params, +}; + +#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON + +static int __init rzt2hsci_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + return early_console_setup(device, &sci_r9a09g077_data); +} + +OF_EARLYCON_DECLARE(rzsci, "renesas,r9a09g077-sci", rzt2hsci_early_console_setup); + +#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ diff --git a/drivers/tty/serial/rzsci.h b/drivers/tty/serial/rzsci.h new file mode 100644 index 000000000000..2840b65e7010 --- /dev/null +++ b/drivers/tty/serial/rzsci.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __RZT2_SCI_H__ +#define __RZT2_SCI_H__ + +#include "sh-sci_common.h" + +#ifdef CONFIG_SERIAL_RZ_SCI +extern struct sci_of_data sci_r9a09g077_data; +#endif + +#endif /* __RZT2_SCI_H__ */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index c58c0793c521..3c0e503295e9 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -54,6 +54,7 @@ #include #endif +#include "rzsci.h" #include "serial_mctrl_gpio.h" #include "sh-sci.h" #include "sh-sci_common.h" @@ -1804,7 +1805,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) unsigned long flags; u32 ctrl; - if (port->type != PORT_SCI) + if (port->type != PORT_SCI && port->type != PORT_RZSCI) return sci_tx_interrupt(irq, ptr); uart_port_lock_irqsave(port, &flags); @@ -2988,10 +2989,10 @@ static int sci_init_single(struct platform_device *dev, } /* - * The fourth interrupt on SCI port is transmit end interrupt, so + * The fourth interrupt on SCI and RZSCI port is transmit end interrupt, so * shuffle the interrupts. */ - if (p->type == PORT_SCI) + if (p->type == PORT_SCI || p->type == PORT_RZSCI) swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); /* The SCI generates several interrupts. They can be muxed together or @@ -3038,6 +3039,9 @@ static int sci_init_single(struct platform_device *dev, else sci_port->rx_trigger = 8; break; + case PORT_RZSCI: + sci_port->rx_trigger = 15; + break; default: sci_port->rx_trigger = 1; break; @@ -3269,7 +3273,7 @@ static void sci_remove(struct platform_device *dev) if (port->port.fifosize > 1) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); - if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) + if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF || type == PORT_RZSCI) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); } @@ -3300,6 +3304,12 @@ static const struct of_device_id of_sci_match[] __maybe_unused = { .compatible = "renesas,scif-r9a09g057", .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE), }, +#ifdef CONFIG_SERIAL_RZ_SCI + { + .compatible = "renesas,r9a09g077-sci", + .data = &sci_r9a09g077_data, + }, +#endif /* CONFIG_SERIAL_RZ_SCI */ /* Family-specific types */ { .compatible = "renesas,rcar-gen1-scif", @@ -3504,7 +3514,7 @@ static int sci_probe(struct platform_device *dev) return ret; } if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || - sp->port.type == PORT_HSCIF) { + sp->port.type == PORT_HSCIF || sp->port.type == PORT_RZSCI) { ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { if (sp->port.fifosize > 1) { diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h index 0f2f50b8d28e..787fd9a96711 100644 --- a/include/linux/serial_sci.h +++ b/include/linux/serial_sci.h @@ -38,6 +38,7 @@ enum { SCIx_HSCIF_REGTYPE, SCIx_RZ_SCIFA_REGTYPE, SCIx_RZV2H_SCIF_REGTYPE, + SCIx_RZT2H_SCI_REGTYPE, SCIx_NR_REGTYPES, }; @@ -50,7 +51,7 @@ struct plat_sci_port_ops { * Platform device specific platform_data struct */ struct plat_sci_port { - unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ + unsigned int type; /* SCI / SCIF / IRDA / HSCIF / RZSCI */ upf_t flags; /* UPF_* flags */ unsigned int sampling_rate; diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 9c007a106330..30fbbef599f4 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -231,6 +231,9 @@ /* Sunplus UART */ #define PORT_SUNPLUS 123 +/* SH-SCI */ +#define PORT_RZSCI 124 + /* Generic type identifier for ports which type is not important to userspace. */ #define PORT_GENERIC (-1)