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Thu, 30 Jan 2025 06:34:41 -0800 From: Kartik Rajput To: , , , , , , , , , , , , Subject: [PATCH v2 1/5] dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C Date: Thu, 30 Jan 2025 20:04:20 +0530 Message-ID: <20250130143424.52389-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130143424.52389-1-kkartik@nvidia.com> References: <20250130143424.52389-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|DM3PR12MB9435:EE_ X-MS-Office365-Filtering-Correlation-Id: 42c8f6b0-5252-4b5a-1325-08dd413b4ad1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|7416014|36860700013|82310400026|376014|921020; X-Microsoft-Antispam-Message-Info: tHNbP+M6r/y3hs44LayYXMi9OBKZYrBVj816b9y4LPBUfIzTNhGdvLZwbEiSO9n7khsV+x1lJgIqVU90M7Y9twlLNqudLvooI6+2Y10wWeYAHMAmaI0EPtU/Fk+YLtGJzfRWjX5FyGz3Yf3h3wFgMqnHu8AriLEOAg8x1dcEWLrDX8SaP1QEVTJaA0Im3XWwhkIBm5pqdIz1Hpksc4sN1ZYbpbf5cigY2kFhLH4lZnLQVLrIaA0DDKTvLVJLDEQghC+fzjPHw/qdM+OpcR8bAfMqDsvfkeepb5h+YuHxQoHBioPJjCl/kuJG4gskuiEve9yGWEEBL/EBt/hDwU7DCDLs4BUFyzMzy63PBSnS+JppyRhIvWGV6inoVwH8ZpK6X4vf7U9khgpjrsvmOeSF48uwiPT4fjkbb3+i/8e8YZKMruAZmlQYwYfxOvqosPvIuY0lqgUVpOIpLCLPlyIuTyf5QAzSm20ZDnqDTYu2k8WoiKDEK4XQ3r9pIDQyjkZ799yoWemb/HM8Isokbs/tYXYhq2v67p6OAQjPQZnWUY6ulZrCMpLJy8ohsvLtRdnhoFQmrOHEsn9J6GfddsdwAuOMrrfPORvIbW6cP5WxDrNNNq8kPWAEiJMfXHtftpmODHYH8ZihXO4vZCgwL+yhq1CkiFyimjtqlZZCcppRQOnhzn2NM2o/A2r4Ko690B6mSqZkeO/WGyltuXjRFvz7OX4tZa/PgQThbmUwTkgO4vpp5ZemJA5yLlz5QSzuXP+F0Mrur+mJjvPc4oSVio3ausfb36O1I+J0dfZlrElFHSQlMdYaujWv8AQMIA7WI3IcsHKwcvE2xVmnT404pGRYfkSuKPA2A5KDpTRMEnRzkQOlSPXzJT1WULn3IOVuB46eRDCFzk57UHrXLvbPExC1PCbCvg+Ghx8zxg//C1d9YYp1htxVtqGXxTtyAHMOHVJNp5e1KprNH/dctbxpscd1qrVr8ehP2k1b1Fz3bbb6i6E+gvScPsjZ7d7k9WCQ2W8iwMmEjfIRFoNkJSdi1gcKunX4Pq0xOq5CzzFw4R+pIG8yTxuk+ZbEU5ZPsCt1uQi7jLMehM1s4AZnUkR3eTRaFi87Kym1/dusKfPTW21gu9acOsCwJLOecgcQVQhZNWSkTYDy+vXKsLj+D+rLlkRsU+HJFe2F9yJW5wY+g7E3hjy8AtT5aiVNop8ZbHYG1N8zhXO42ytW5LRFtcpRiwd/Dyfx/kk4LX+w52K4YHsfrDxNT3bP+veEhe9Gc/Aa7iaxJ+i0fpvp436sKT+krJT/9SIpf6I39CnEUBGioUTu13MR5Silv8rzCAPYQ8Z1tE6LGEu7VQ7BNQHMvnfj8fmq6oyWmX4fhZYK9hNipqTkYiDjAstMYSlVOrtkEcHnyxhteV9CQpq52EjYf6aL5jN8RZ+5D0uSOllcr3YWQFzhANxNh7gxBSnt8Us+wBMS0U3ZNW5pNxs1/4IBWVGyMDvpTwf4hDzM4ET3r8p6ZbhzDetEcNo2dJ8DzNVDaVQ/w9ZN X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(7416014)(36860700013)(82310400026)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 14:35:06.9164 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42c8f6b0-5252-4b5a-1325-08dd413b4ad1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9435 Tegra264 has 17 generic I2C controllers, two of which are in always-on partition of the SoC. In addition to the features supported by Tegra194 it also supports a SW mutex register to allow sharing the same I2C instance across multiple firmware. Document compatible string "nvidia,tegra264-i2c" for Tegra264 I2C. Signed-off-by: Kartik Rajput --- v1 -> v2: * Fixed typos. --- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index b57ae6963e62..89138384517e 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -80,6 +80,12 @@ properties: support for 64 KiB transactions whereas earlier chips supported no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: + Tegra264 has 17 generic I2C controllers, two of which are in the AON + (always-on) partition of the SoC. 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 14:35:10.6042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93380b55-b7b6-4629-b709-08dd413b4d0f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB59.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5802 On Tegra264, not all I2C controllers have the necessary interface to GPC DMA, this causes failures when function tegra_i2c_init_dma() is called. Ensure that "dmas" device-tree property is present before initializing DMA in function tegra_i2c_init_dma(). Signed-off-by: Kartik Rajput --- v1 -> v2: * Update commit message to clarify that some I2C controllers may not have the necessary interface to GPC DMA. --- drivers/i2c/busses/i2c-tegra.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 87976e99e6d0..b0dd129714a2 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -442,6 +442,9 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) if (IS_VI(i2c_dev)) return 0; + if (!device_property_present(i2c_dev->dev, "dmas")) + return 0; + if (i2c_dev->hw->has_apb_dma) { if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); From patchwork Thu Jan 30 14:34:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kartik Rajput X-Patchwork-Id: 861656 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2072.outbound.protection.outlook.com [40.107.95.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A951E9B3F; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 14:35:13.2836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a216b733-10a0-4dcb-2e34-08dd413b4ea6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7092 From: Akhil R Add support for HS (High Speed) mode transfers, which is supported by Tegra194 onwards. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v1 -> v2: * Document has_hs_mode_support. * Add a check to set the frequency to fastmode+ if the device does not support HS mode but the requested frequency is more than fastmode+. --- drivers/i2c/busses/i2c-tegra.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index b0dd129714a2..7c8b76406e2e 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -91,6 +91,7 @@ #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_HS_MODE BIT(22) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -201,6 +202,7 @@ enum msg_end_type { * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the tuned * timing settings. + * @has_hs_mode_support: Has support for high speed (HS) mode transfers. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -220,10 +222,13 @@ struct tegra_i2c_hw_feature { u32 thigh_std_mode; u32 tlow_fast_fastplus_mode; u32 thigh_fast_fastplus_mode; + u32 tlow_hs_mode; + u32 thigh_hs_mode; u32 setup_hold_time_std_mode; u32 setup_hold_time_fast_fast_plus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_hs_mode_support; }; /** @@ -684,6 +689,20 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); + /* Write HS mode registers. These will get used only for HS mode*/ + if (i2c_dev->hw->has_hs_mode_support) { + tlow = i2c_dev->hw->tlow_hs_mode; + thigh = i2c_dev->hw->thigh_hs_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode; + + val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + } else if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { + t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ; + } + clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); err = clk_set_rate(i2c_dev->div_clk, @@ -1181,6 +1200,9 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, if (msg->flags & I2C_M_RD) packet_header |= I2C_HEADER_READ; + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) + packet_header |= I2C_HEADER_HS_MODE; + if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ = packet_header; else @@ -1621,10 +1643,13 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .thigh_std_mode = 0x7, .tlow_fast_fastplus_mode = 0x2, .thigh_fast_fastplus_mode = 0x2, + .tlow_hs_mode = 0x8, + .thigh_hs_mode = 0x3, .setup_hold_time_std_mode = 0x08080808, .setup_hold_time_fast_fast_plus_mode = 0x02020202, .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, + .has_hs_mode_support = true, }; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014)(7416014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 14:35:17.6885 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f92fc60d-7c12-45a4-2890-08dd413b513f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8315 From: Akhil R Add support for SW mutex register introduced in Tegra264 to provide an option to share the interface between multiple firmwares and/or VMs. However, the hardware does not ensure any protection based on the values. The driver/firmware should honor the peer who already holds the mutex. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v1 -> v2: * Fixed typos. * Fix tegra_i2c_mutex_lock() logic. * Add a timeout in tegra_i2c_mutex_lock() instead of polling for mutex indefinitely. --- drivers/i2c/busses/i2c-tegra.c | 132 +++++++++++++++++++++++++++++---- 1 file changed, 117 insertions(+), 15 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 7c8b76406e2e..aa92faa6f5cb 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -135,6 +135,14 @@ #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) +#define I2C_SW_MUTEX 0x0ec +#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) +#define I2C_SW_MUTEX_GRANT GENMASK(7, 4) +#define I2C_SW_MUTEX_ID 9 + +/* SW mutex acquire timeout value in milliseconds. */ +#define I2C_SW_MUTEX_TIMEOUT 25 + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 @@ -203,6 +211,7 @@ enum msg_end_type { * @has_interface_timing_reg: Has interface timing register to program the tuned * timing settings. * @has_hs_mode_support: Has support for high speed (HS) mode transfers. + * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VM. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -229,6 +238,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_hs_mode_support; + bool has_mutex; }; /** @@ -372,6 +382,103 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } +static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, + u32 reg, u32 mask, u32 delay_us, + u32 timeout_us) +{ + void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); + u32 val; + + if (!i2c_dev->atomic_mode) + return readl_relaxed_poll_timeout(addr, val, !(val & mask), + delay_us, timeout_us); + + return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), + delay_us, timeout_us); +} + +static int tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) +{ + u32 val, id; + + val = i2c_readl(i2c_dev, I2C_SW_MUTEX); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id != 0 && id != I2C_SW_MUTEX_ID) + return 0; + + val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID); + i2c_writel(i2c_dev, val, I2C_SW_MUTEX); + + val = i2c_readl(i2c_dev, I2C_SW_MUTEX); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + if (id != I2C_SW_MUTEX_ID) + return 0; + + return 1; +} + +static void tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int num_retries = I2C_SW_MUTEX_TIMEOUT; + + /* Poll until mutex is acquired or timeout. */ + while (--num_retries && !tegra_i2c_mutex_trylock(i2c_dev)) + usleep_range(1000, 2000); + + WARN_ON(!num_retries); +} + +static void tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) +{ + u32 val, id; + + val = i2c_readl(i2c_dev, I2C_SW_MUTEX); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + if (WARN_ON(id != I2C_SW_MUTEX_ID)) + return; + + i2c_writel(i2c_dev, 0, I2C_SW_MUTEX); +} + +static void tegra_i2c_bus_lock(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); + + rt_mutex_lock_nested(&adapter->bus_lock, i2c_adapter_depth(adapter)); + tegra_i2c_mutex_lock(i2c_dev); +} + +static int tegra_i2c_bus_trylock(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); + int ret; + + ret = rt_mutex_trylock(&adapter->bus_lock); + if (ret) + ret = tegra_i2c_mutex_trylock(i2c_dev); + + return ret; +} + +static void tegra_i2c_bus_unlock(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); + + rt_mutex_unlock(&adapter->bus_lock); + tegra_i2c_mutex_unlock(i2c_dev); +} + +static const struct i2c_lock_operations tegra_i2c_lock_ops = { + .lock_bus = tegra_i2c_bus_lock, + .trylock_bus = tegra_i2c_bus_trylock, + .unlock_bus = tegra_i2c_bus_unlock, +}; + static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; @@ -550,21 +657,6 @@ static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); } -static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, - u32 reg, u32 mask, u32 delay_us, - u32 timeout_us) -{ - void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); - u32 val; - - if (!i2c_dev->atomic_mode) - return readl_relaxed_poll_timeout(addr, val, !(val & mask), - delay_us, timeout_us); - - return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), - delay_us, timeout_us); -} - static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) { u32 mask, val, offset; @@ -1503,6 +1595,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { @@ -1527,6 +1620,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { @@ -1551,6 +1645,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { @@ -1575,6 +1670,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = true, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { @@ -1599,6 +1695,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0, .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { @@ -1623,6 +1720,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0, .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { @@ -1650,6 +1748,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, .has_hs_mode_support = true, + .has_mutex = false, }; static const struct of_device_id tegra_i2c_of_match[] = { @@ -1853,6 +1952,9 @@ static int tegra_i2c_probe(struct platform_device *pdev) i2c_dev->adapter.nr = pdev->id; ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); + if (i2c_dev->hw->has_mutex) + i2c_dev->adapter.lock_ops = &tegra_i2c_lock_ops; + if (i2c_dev->hw->supports_bus_clear) i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; From patchwork Thu Jan 30 14:34:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kartik Rajput X-Patchwork-Id: 861655 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2052.outbound.protection.outlook.com [40.107.243.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 064291BB6BC; Thu, 30 Jan 2025 14:35:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 14:35:26.9166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6802beb5-79cf-42ff-c699-08dd413b56c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7174 From: Akhil R Add support for Tegra264 SoC which supports 17 generic I2C controllers, two of which are in the AON (always-on) partition of the SoC. Tegra264 I2C supports all the features supported by Tegra194 I2C controllers. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- drivers/i2c/busses/i2c-tegra.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index aa92faa6f5cb..415337e069f5 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1751,7 +1751,36 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_mutex = false, }; +static const struct tegra_i2c_hw_feature tegra264_i2c_hw = { + .has_continue_xfer_support = true, + .has_per_pkt_xfer_complete_irq = true, + .clk_divisor_hs_mode = 1, + .clk_divisor_std_mode = 0x1d, + .clk_divisor_fast_mode = 0x15, + .clk_divisor_fast_plus_mode = 0x8, + .has_config_load_reg = true, + .has_multi_master_mode = true, + .has_slcg_override_reg = true, + .has_mst_fifo = true, + .quirks = &tegra194_i2c_quirks, + .supports_bus_clear = true, + .has_apb_dma = false, + .tlow_std_mode = 0x8, + .thigh_std_mode = 0x7, + .tlow_fast_fastplus_mode = 0x2, + .thigh_fast_fastplus_mode = 0x2, + .tlow_hs_mode = 0x4, + .thigh_hs_mode = 0x2, + .setup_hold_time_std_mode = 0x08080808, + .setup_hold_time_fast_fast_plus_mode = 0x02020202, + .setup_hold_time_hs_mode = 0x090909, + .has_interface_timing_reg = true, + .has_hs_mode_support = true, + .has_mutex = true, +}; + static const struct of_device_id tegra_i2c_of_match[] = { + { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, }, { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)