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Wed, 05 Feb 2025 14:25:19 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 1/9] dt-bindings: clock: samsung,exynos990-clock: add PERIC0/1 clock management unit Date: Wed, 5 Feb 2025 22:22:15 +0000 Message-Id: <20250205222223.613-2-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add dt-schema documentation for the Connectivity Peripheral 0 / 1 (PERIC0/1) clock management unit. Signed-off-by: Denzeel Oliva --- .../clock/samsung,exynos990-clock.yaml | 24 +++ include/dt-bindings/clock/samsung,exynos990.h | 178 +++++++++++++++++- 2 files changed, 201 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml index 9e7944b5f..6b053d1bc 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -30,6 +30,8 @@ description: | properties: compatible: enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 - samsung,exynos990-cmu-hsi0 - samsung,exynos990-cmu-top @@ -55,6 +57,28 @@ required: - reg allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 307215a3f..97cb5e8d2 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -233,4 +233,180 @@ #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 -#endif +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_USI00_USI_USER 2 +#define CLK_MOUT_PERIC0_USI01_USI_USER 3 +#define CLK_MOUT_PERIC0_USI02_USI_USER 4 +#define CLK_MOUT_PERIC0_USI03_USI_USER 5 +#define CLK_MOUT_PERIC0_USI04_USI_USER 6 +#define CLK_MOUT_PERIC0_USI05_USI_USER 7 +#define CLK_MOUT_PERIC0_USI_I2C_USER 8 +#define CLK_MOUT_PERIC0_UART_DBG 9 +#define CLK_MOUT_PERIC0_USI13_USI_USER 10 +#define CLK_MOUT_PERIC0_USI14_USI_USER 11 +#define CLK_MOUT_PERIC0_USI15_USI_USER 12 +#define CLK_DOUT_PERIC0_USI00_USI 13 +#define CLK_DOUT_PERIC0_USI01_USI 14 +#define CLK_DOUT_PERIC0_USI02_USI 15 +#define CLK_DOUT_PERIC0_USI03_USI 16 +#define CLK_DOUT_PERIC0_USI04_USI 17 +#define CLK_DOUT_PERIC0_USI05_USI 18 +#define CLK_DOUT_PERIC0_USI_I2C 19 +#define CLK_DOUT_PERIC0_UART_DBG 20 +#define CLK_DOUT_PERIC0_USI13_USI 21 +#define CLK_DOUT_PERIC0_USI14_USI 22 +#define CLK_DOUT_PERIC0_USI15_USI 23 +#define CLK_GOUT_PERIC0_GPIO_PCLK 24 +#define CLK_GOUT_PERIC0_SYSREG_PCLK 25 +#define CLK_GOUT_PERIC0_CMU_PCLK 26 +#define CLK_GOUT_PERIC0_BUSP_CLK 27 +#define CLK_GOUT_PERIC0_OSCCLK_CLK 28 +#define CLK_GOUT_PERIC0_USI00_USI_CLK 29 +#define CLK_GOUT_PERIC0_USI_I2C_CLK 30 +#define CLK_GOUT_PERIC0_USI01_USI_CLK 31 +#define CLK_GOUT_PERIC0_USI02_USI_CLK 32 +#define CLK_GOUT_PERIC0_USI03_USI_CLK 33 +#define CLK_GOUT_PERIC0_USI04_USI_CLK 34 +#define CLK_GOUT_PERIC0_USI05_USI_CLK 35 +#define CLK_GOUT_PERIC0_UART_DBG_CLK 36 +#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 37 +#define CLK_GOUT_PERIC0_USI13_USI_CLK 38 +#define CLK_GOUT_PERIC0_USI14_USI_CLK 39 +#define CLK_GOUT_PERIC0_D_TZPC_PCLK 40 +#define CLK_GOUT_PERIC0_USI15_USI_CLK 41 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 42 +#define CLK_GOUT_PERIC0_TOP0_PCLK_4 43 +#define CLK_GOUT_PERIC0_TOP0_PCLK_5 44 +#define CLK_GOUT_PERIC0_TOP0_PCLK_6 45 +#define CLK_GOUT_PERIC0_TOP0_PCLK_7 46 +#define CLK_GOUT_PERIC0_TOP0_PCLK_8 47 +#define CLK_GOUT_PERIC0_TOP0_PCLK_9 48 +#define CLK_GOUT_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 55 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 56 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 57 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 58 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 59 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 60 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 61 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 62 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 63 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 64 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 65 +#define CLK_GOUT_PERIC0_TOP1_PCLK_0 66 +#define CLK_GOUT_PERIC0_TOP1_PCLK_3 67 +#define CLK_GOUT_PERIC0_TOP1_PCLK_4 68 +#define CLK_GOUT_PERIC0_TOP1_PCLK_5 69 +#define CLK_GOUT_PERIC0_TOP1_PCLK_6 70 +#define CLK_GOUT_PERIC0_TOP1_PCLK_7 71 +#define CLK_GOUT_PERIC0_TOP1_PCLK_8 72 +#define CLK_GOUT_PERIC0_TOP1_PCLK_15 73 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 74 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 75 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 76 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 77 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 78 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 79 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 80 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_UART_BT_USER 2 +#define CLK_MOUT_PERIC1_USI_I2C_USER 3 +#define CLK_MOUT_PERIC1_USI06_USI_USER 4 +#define CLK_MOUT_PERIC1_USI07_USI_USER 5 +#define CLK_MOUT_PERIC1_USI08_USI_USER 6 +#define CLK_MOUT_PERIC1_USI09_USI_USER 7 +#define CLK_MOUT_PERIC1_USI10_USI_USER 8 +#define CLK_MOUT_PERIC1_USI11_USI_USER 9 +#define CLK_MOUT_PERIC1_USI12_USI_USER 10 +#define CLK_MOUT_PERIC1_USI18_USI_USER 11 +#define CLK_MOUT_PERIC1_USI16_USI_USER 12 +#define CLK_MOUT_PERIC1_USI17_USI_USER 13 +#define CLK_DOUT_PERIC1_UART_BT 14 +#define CLK_DOUT_PERIC1_USI_I2C 15 +#define CLK_DOUT_PERIC1_USI06_USI 16 +#define CLK_DOUT_PERIC1_USI07_USI 17 +#define CLK_DOUT_PERIC1_USI08_USI 18 +#define CLK_DOUT_PERIC1_USI18_USI 19 +#define CLK_DOUT_PERIC1_USI12_USI 20 +#define CLK_DOUT_PERIC1_USI09_USI 21 +#define CLK_DOUT_PERIC1_USI10_USI 22 +#define CLK_DOUT_PERIC1_USI11_USI 23 +#define CLK_DOUT_PERIC1_USI16_USI 24 +#define CLK_DOUT_PERIC1_USI17_USI 25 +#define CLK_GOUT_PERIC1_GPIO_PCLK 26 +#define CLK_GOUT_PERIC1_SYSREG_PCLK 27 +#define CLK_GOUT_PERIC1_CMU_PCLK 28 +#define CLK_GOUT_PERIC1_BUSP_CLK 29 +#define CLK_GOUT_PERIC1_USI06_USI_CLK 30 +#define CLK_GOUT_PERIC1_USI07_USI_CLK 31 +#define CLK_GOUT_PERIC1_USI08_USI_CLK 32 +#define CLK_GOUT_PERIC1_USI09_USI_CLK 33 +#define CLK_GOUT_PERIC1_USI10_USI_CLK 34 +#define CLK_GOUT_PERIC1_USI_I2C_CLK 35 +#define CLK_GOUT_PERIC1_UART_BT_CLK 36 +#define CLK_GOUT_PERIC1_USI12_USI_CLK 37 +#define CLK_GOUT_PERIC1_USI18_USI_CLK 38 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 39 +#define CLK_GOUT_PERIC1_USI11_USI_CLK 40 +#define CLK_GOUT_PERIC1_D_TZPC_PCLK 41 +#define CLK_GOUT_PERIC1_USI16_USI_CLK 42 +#define CLK_GOUT_PERIC1_USI17_USI_CLK 43 +#define CLK_GOUT_PERIC1_TOP0_PCLK_4 44 +#define CLK_GOUT_PERIC1_TOP0_PCLK_10 45 +#define CLK_GOUT_PERIC1_TOP0_PCLK_11 46 +#define CLK_GOUT_PERIC1_TOP0_PCLK_12 47 +#define CLK_GOUT_PERIC1_TOP0_PCLK_13 48 +#define CLK_GOUT_PERIC1_TOP0_PCLK_14 49 +#define CLK_GOUT_PERIC1_TOP0_PCLK_15 50 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 51 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 52 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 53 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 54 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 55 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 56 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 57 +#define CLK_GOUT_PERIC1_TOP1_PCLK_1 58 +#define CLK_GOUT_PERIC1_TOP1_PCLK_0 59 +#define CLK_GOUT_PERIC1_TOP1_PCLK_2 60 +#define CLK_GOUT_PERIC1_TOP1_PCLK_3 61 +#define CLK_GOUT_PERIC1_TOP1_PCLK_4 62 +#define CLK_GOUT_PERIC1_TOP1_PCLK_5 63 +#define CLK_GOUT_PERIC1_TOP1_PCLK_6 64 +#define CLK_GOUT_PERIC1_TOP1_PCLK_7 65 +#define CLK_GOUT_PERIC1_TOP1_PCLK_9 66 +#define CLK_GOUT_PERIC1_TOP1_PCLK_10 67 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 68 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 69 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 70 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 71 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 72 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 73 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 74 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 75 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 76 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 77 +#define CLK_GOUT_PERIC1_OSCCLK_CLK 78 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 79 +#define CLK_GOUT_PERIC1_XIU_P_ACLK 80 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 81 +#define CLK_GOUT_PERIC1_TOP1_PCLK_12 82 +#define CLK_GOUT_PERIC1_TOP1_PCLK_13 83 +#define CLK_GOUT_PERIC1_TOP1_PCLK_14 84 +#define CLK_GOUT_PERIC1_TOP1_PCLK_15 85 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 86 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 87 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 88 +#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 89 +#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 90 +#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91 +#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 92 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS990_H */ From patchwork Wed Feb 5 22:22:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 862915 Received: from mail-vs1-f46.google.com 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<20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add samsung,exynos990-hsi2c dedicated compatible for representing I2C of Exynos990 SoC. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 70cc2ee9e..b05d1e9e2 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -36,6 +36,7 @@ properties: - enum: - google,gs101-hsi2c - samsung,exynos850-hsi2c + - samsung,exynos990-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 deprecated: true From patchwork Wed Feb 5 22:22:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 862363 Received: from mail-ua1-f42.google.com (mail-ua1-f42.google.com [209.85.222.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34A45218E99; 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Wed, 05 Feb 2025 14:25:25 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:24 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 3/9] dt-bindings: serial: samsung: add Exynos990 compatible Date: Wed, 5 Feb 2025 22:22:17 +0000 Message-Id: <20250205222223.613-4-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add samsung,exynos990-uart compatible. It falls back to samsung,exynos8895-uart since FIFO size is defined in DT. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 070eba9f1..f38be8e95 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -28,6 +28,7 @@ properties: - samsung,exynos5433-uart - samsung,exynos850-uart - samsung,exynos8895-uart + - samsung,exynos990-uart - items: - enum: - samsung,exynos7-uart @@ -42,6 +43,10 @@ properties: - samsung,exynosautov9-uart - samsung,exynosautov920-uart - const: samsung,exynos850-uart + - items: + - enum: + - samsung,exynos990-uart + - const: samsung,exynos8895-uart reg: maxItems: 1 @@ -162,6 +167,7 @@ allOf: enum: - google,gs101-uart - samsung,exynos8895-uart + - samsung,exynos990-uart then: required: - samsung,uart-fifosize From patchwork Wed Feb 5 22:22:18 2025 Content-Type: text/plain; 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Wed, 05 Feb 2025 14:25:27 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 4/9] dt-bindings: samsung: usi: add exynos990-usi compatible Date: Wed, 5 Feb 2025 22:22:18 +0000 Message-Id: <20250205222223.613-5-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add samsung,exynos990-usi dedicated compatible for representing USI of Exynos990. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 5b046932f..4283d35f5 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - google,gs101-usi + - samsung,exynos990-usi - samsung,exynosautov9-usi - samsung,exynosautov920-usi - const: samsung,exynos850-usi From patchwork Wed Feb 5 22:22:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 862362 Received: from mail-ua1-f41.google.com (mail-ua1-f41.google.com [209.85.222.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E50E6218E99; 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Wed, 05 Feb 2025 14:25:29 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:29 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 5/9] spi: dt-bindings: samsung: add samsung,exynos990-spi compatible Date: Wed, 5 Feb 2025 22:22:19 +0000 Message-Id: <20250205222223.613-6-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 According to the Exynos 990 downstream kernel, almost all of them do not use the same 64 bytes depth. Some SPI nodes using a depth of 256 bytes (SPI 9/8/10). But in the end these nodes work. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index 3c206a64d..1d3c95bd2 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -24,6 +24,7 @@ properties: - samsung,exynos4210-spi - samsung,exynos5433-spi - samsung,exynos850-spi + - samsung,exynos990-spi - samsung,exynosautov9-spi - tesla,fsd-spi - items: From patchwork Wed Feb 5 22:22:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 862913 Received: from mail-vs1-f48.google.com (mail-vs1-f48.google.com [209.85.217.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3289021E08A; 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Wed, 05 Feb 2025 14:25:32 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:31 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 6/9] dt-bindings: soc: samsung: exynos-sysreg: add compatibles peric0/1 sysreg for Exynos990 Date: Wed, 5 Feb 2025 22:22:20 +0000 Message-Id: <20250205222223.613-7-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Downstream from the Exynos990 kernel source it has more sysreg in flexpmu, but for now only those two will be added Signed-off-by: Denzeel Oliva --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index a75aef240..6ca3862b1 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -25,6 +25,8 @@ properties: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynos990-peric0-sysreg + - samsung,exynos990-peric1-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg - tesla,fsd-cam-sysreg From patchwork Wed Feb 5 22:22:21 2025 Content-Type: text/plain; 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Wed, 05 Feb 2025 14:25:34 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 7/9] clk: samsung: exynos990: add support for CMU_PERIC0/1 Date: Wed, 5 Feb 2025 22:22:21 +0000 Message-Id: <20250205222223.613-8-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CMU_PERIC0/1 is the clock management unit used for the peric0/1 block which is used for USI and I2C. Add support for all cmu_peric0 clocks but CLK_GOUT_PERIC0|1_IP (not enough info in the datasheet). None of the clocks are marked as critical. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 1079 +++++++++++++++++++++++++++ 1 file changed, 1079 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c index 8e2a2e8ec..9ba17f360 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -19,6 +19,8 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_TOP1_IPCLK_8 + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_USI17_I3C_PCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -1305,6 +1307,1077 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = { .clk_name = "bus", }; +/* ---- CMU_PERIC0 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10400000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a4 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI 0x1824 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e4 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x2094 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3 0x209c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4 0x20a0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6 0x20a8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7 0x20ac +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15 0x2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3 0x207c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4 0x2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5 0x2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6 0x2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7 0x208c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8 0x2090 + +static const unsigned long peric0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG, + PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG, + PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER, + CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, + CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, +}; + +PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; +PNAME(mout_peric0_usi00_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi01_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi02_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi03_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi04_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi05_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_uart_dbg_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi13_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi14_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi15_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user", + mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user", + mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user", + mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user", + mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user", + mout_peric0_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user", + mout_peric0_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI_I2C_USER, "mout_peric0_usi_i2c_user", + mout_peric0_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg", + mout_peric0_uart_dbg_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG, 4, 1), + MUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user", + mout_peric0_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user", + mout_peric0_usi14_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user", + mout_peric0_usi15_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi", "mout_peric0_usi00_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi", "mout_peric0_usi01_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi", "mout_peric0_usi02_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi", "mout_peric0_usi03_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi", "mout_peric0_usi04_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi", "mout_peric0_usi05_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c", "mout_peric0_usi_i2c_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC0_UART_DBG, "dout_peric0_uart_dbg", "mout_peric0_uart_dbg", + CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, 0, 4), + DIV(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi", "mout_peric0_usi13_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi", "mout_peric0_usi15_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERIC0_GPIO_PCLK, "gout_peric0_gpio_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_SYSREG_PCLK, "gout_peric0_sysreg_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CMU_PCLK, "gout_peric0_cmu_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_BUSP_CLK, "gout_peric0_busp_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_OSCCLK_CLK, "gout_peric0_oscclk_pclk", + "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI00_USI_CLK, "gout_peric0_usi00_usi_clk", + "dout_peric0_usi00_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI_I2C_CLK, "gout_peric0_usi_i2c_clk", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI01_USI_CLK, "gout_peric0_usi01_usi_clk", + "dout_peric0_usi01_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI02_USI_CLK, "gout_peric0_usi02_usi_clk", + "dout_peric0_usi02_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI03_USI_CLK, "gout_peric0_usi03_usi_clk", + "dout_peric0_usi03_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI04_USI_CLK, "gout_peric0_usi04_usi_clk", + "dout_peric0_usi04_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI05_USI_CLK, "gout_peric0_usi05_usi_clk", + "dout_peric0_usi05_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_UART_DBG_CLK, "gout_peric0_uart_dbg_clk", + "dout_peric0_uart_dbg", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_CLK, "gout_peric0_lhm_axi_p_clk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI13_USI_CLK, "gout_peric0_usi13_usi_clk", + "dout_peric0_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI14_USI_CLK, "gout_peric0_usi14_usi_clk", + "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_D_TZPC_PCLK, "gout_peric0_d_tpzc_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI15_USI_CLK, "gout_peric0_usi15_usi_clk", + "dout_peric0_usi15_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_4, "gout_peric0_top0_ipclk_4", + "dout_peric0_uart_dbg", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_4, "gout_peric0_top0_pclk_4", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_5, "gout_peric0_top0_pclk_5", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_6, "gout_peric0_top0_pclk_6", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_7, "gout_peric0_top0_pclk_7", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_8, "gout_peric0_top0_pclk_8", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_9, "gout_peric0_top0_pclk_9", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_10, "gout_peric0_top0_pclk_10", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_11, "gout_peric0_top0_pclk_11", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_12, "gout_peric0_top0_pclk_12", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_13, "gout_peric0_top0_pclk_13", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_14, "gout_peric0_top0_pclk_14", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_15, "gout_peric0_top0_pclk_15", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_5, "gout_peric0_top0_ipclk_5", + "dout_peric0_usi00_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_6, "gout_peric0_top0_ipclk_6", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_7, "gout_peric0_top0_ipclk_7", + "dout_peric0_usi01_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_8, "gout_peric0_top0_ipclk_8", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_9, "gout_peric0_top0_ipclk_9", + "dout_peric0_usi02_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_10, "gout_peric0_top0_ipclk_10", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_11, "gout_peric0_top0_ipclk_11", + "dout_peric0_usi03_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_12, "gout_peric0_top0_ipclk_12", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_13, "gout_peric0_top0_ipclk_13", + "dout_peric0_usi04_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_14, "gout_peric0_top0_ipclk_14", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_15, "gout_peric0_top0_ipclk_15", + "dout_peric0_usi05_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_0, "gout_peric0_top1_pclk_0", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_3, "gout_peric0_top1_pclk_3", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_4, "gout_peric0_top1_pclk_4", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_5, "gout_peric0_top1_pclk_5", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_6, "gout_peric0_top1_pclk_6", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_7, "gout_peric0_top1_pclk_7", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_8, "gout_peric0_top1_pclk_8", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_15, "gout_peric0_top1_pclk_15", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_0, "gout_peric0_top1_ipclk_0", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_3, "gout_peric0_top1_ipclk_3", + "dout_peric0_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_4, "gout_peric0_top1_ipclk_4", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_5, "gout_peric0_top1_ipclk_5", + "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_6, "gout_peric0_top1_ipclk_6", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_7, "gout_peric0_top1_ipclk_7", + "dout_peric0_usi15_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_8, "gout_peric0_top1_ipclk_8", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst = { + .mux_clks = peric0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), + .div_clks = peric0_div_clks, + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), + .gate_clks = peric0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC0, + .clk_regs = peric0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), + .clk_name = "bus", +}; + +/* ---- CMU_PERIC1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10700000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c4 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a4 +#define CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x182c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2108 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK 0x20e8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK 0x20ec +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK 0x20f0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x20f4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK 0x2104 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x200c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x20f8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK 0x20fc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK 0x2100 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1 0x20a0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0 0x209c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2 0x207c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3 0x2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4 0x2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5 0x2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6 0x208c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7 0x2090 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9 0x2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x211c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12 0x20ac +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15 0x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK 0x210c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK 0x2110 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK 0x2118 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK 0x2114 + +static const unsigned long peric1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER, + CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, +}; + +PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" }; +PNAME(mout_peric1_uart_bt_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi06_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi07_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi08_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi09_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi10_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi11_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi12_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi18_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi16_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi17_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", + mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user", + mout_peric1_uart_bt_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI_I2C_USER, "mout_peric1_usi_i2c_user", + mout_peric1_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user", + mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user", + mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user", + mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user", + mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user", + mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user", + mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user", + mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user", + mout_peric1_usi18_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user", + mout_peric1_usi16_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user", + mout_peric1_usi17_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC1_UART_BT, "dout_peric1_uart_bt", "mout_peric1_uart_bt_user", + CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, 0, 4), + DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c", "mout_peric1_usi_i2c_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi", "mout_peric1_usi06_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi", "mout_peric1_usi07_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi", "mout_peric1_usi08_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi", "mout_peric1_usi18_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi", "mout_peric1_usi09_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi", "mout_peric1_usi16_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi", "mout_peric1_usi17_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERIC1_GPIO_PCLK, "gout_peric1_gpio_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_SYSREG_PCLK, "gout_peric1_sysreq_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CMU_PCLK, "gout_peric1_cmu_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_BUSP_CLK, "gout_peric1_busp_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI06_USI_CLK, "gout_peric1_usi06_usi_clk", + "dout_peric1_usi06_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI07_USI_CLK, "gout_peric1_usi07_usi_clk", + "dout_peric1_usi07_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI08_USI_CLK, "gout_peric1_usi08_usi_clk", + "dout_peric1_usi08_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI09_USI_CLK, "gout_peric1_usi09_usi_clk", + "dout_peric1_usi09_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI10_USI_CLK, "gout_peric1_usi10_usi_clk", + "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI_I2C_CLK, "gout_peric1_usi_i2c_clk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_UART_BT_CLK, "gout_peric1_uart_bt_clk", + "dout_peric1_uart_bt", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI12_USI_CLK, "gout_peric1_usi12_usi_clk", + "dout_peric1_usi12_usi", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI18_USI_CLK, "gout_peric1_usi18_usi_clk", + "dout_peric1_usi18_usi", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CLK, "gout_peric1_lhm_axi_p_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI11_USI_CLK, "gout_peric1_usi11_usi_clk", + "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_D_TZPC_PCLK, "gout_peric1_d_tzpc_pclk", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_USI_CLK, "gout_peric1_usi16_usi_clk", + "dout_peric1_usi16_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_USI_CLK, "gout_peric1_usi17_usi_clk", + "dout_peric1_usi17_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_4, "gout_peric1_top0_pclk_4", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_10, "gout_peric1_top0_pclk_10", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_11, "gout_peric1_top0_pclk_11", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_12, "gout_peric1_top0_pclk_12", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_13, "gout_peric1_top0_pclk_13", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_14, "gout_peric1_top0_pclk_14", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_15, "gout_peric1_top0_pclk_15", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_4, "gout_peric1_top0_ipclk_4", + "dout_peric1_uart_bt", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_10, "gout_peric1_top0_ipclk_10", + "dout_peric1_usi06_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_11, "gout_peric1_top0_ipclk_11", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_12, "gout_peric1_top0_ipclk_12", + "dout_peric1_usi07_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_13, "gout_peric1_top0_ipclk_13", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_14, "gout_peric1_top0_ipclk_14", + "dout_peric1_usi08_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_15, "gout_peric1_top0_ipclk_15", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_1, "gout_peric1_top1_pclk_1", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_0, "gout_peric1_top1_pclk_0", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_2, "gout_peric1_top1_pclk_2", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_3, "gout_peric1_top1_pclk_3", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_4, "gout_peric1_top1_pclk_4", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_5, "gout_peric1_top1_pclk_5", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_6, "gout_peric1_top1_pclk_6", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_7, "gout_peric1_top1_pclk_7", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_9, "gout_peric1_top1_pclk_9", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_10, "gout_peric1_top1_pclk_10", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_0, "gout_peric1_top1_ipclk_0", + "dout_peric1_usi09_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_1, "gout_peric1_top1_ipclk_1", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_2, "gout_peric1_top1_ipclk_2", + "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_3, "gout_peric1_top1_ipclk_3", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_4, "gout_peric1_top1_ipclk_4", + "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_5, "gout_peric1_top1_ipclk_5", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_6, "gout_peric1_top1_ipclk_6", + "dout_peric1_usi16_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_7, "gout_peric1_top1_ipclk_7", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_9, "gout_peric1_top1_ipclk_9", + "dout_peric1_usi17_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_10, "gout_peric1_top1_ipclk_10", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_OSCCLK_CLK, "gout_peric1_oscclk_clk", + "oscclk", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK, "gout_peric1_lhm_axi_p_csis_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_XIU_P_ACLK, "gout_peric1_xiu_p_aclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_12, "gout_peric1_top1_ipclk_12", + "dout_peric1_usi12_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_12, "gout_peric1_top1_pclk_12", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_13, "gout_peric1_top1_pclk_13", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_14, "gout_peric1_top1_pclk_14", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_15, "gout_peric1_top1_pclk_15", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_13, "gout_peric1_top1_ipclk_13", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_14, "gout_peric1_top1_ipclk_14", + "dout_peric1_usi18_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_15, "gout_peric1_top1_ipclk_15", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_I3C_PCLK, "gout_peric1_usi16_i3c_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_I3C_SCLK, "gout_peric1_usi16_i3c_sclk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_I3C_SCLK, "gout_peric1_usi17_i3c_sclk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_I3C_PCLK, "gout_peric1_usi17_i3c_pclk", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst = { + .mux_clks = peric1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), + .div_clks = peric1_div_clks, + .nr_div_clks = ARRAY_SIZE(peric1_div_clks), + .gate_clks = peric1_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC1, + .clk_regs = peric1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), + .clk_name = "bus", +}; + /* ----- platform_driver ----- */ static int __init exynos990_cmu_probe(struct platform_device *pdev) @@ -1322,6 +2395,12 @@ static const struct of_device_id exynos990_cmu_of_match[] = { { .compatible = "samsung,exynos990-cmu-hsi0", .data = &hsi0_cmu_info, + }, { + .compatible = "samsung,exynos990-cmu-peric0", + .data = &peric0_cmu_info, + }, { + .compatible = "samsung,exynos990-cmu-peric1", + .data = &peric1_cmu_info, }, { }, }; From patchwork Wed Feb 5 22:22:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 862912 Received: from mail-ua1-f53.google.com (mail-ua1-f53.google.com [209.85.222.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client 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Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:36 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 8/9] spi: s3c64xx: add support exynos990-spi to new port config data Date: Wed, 5 Feb 2025 22:22:22 +0000 Message-Id: <20250205222223.613-9-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Exynos990 has the same version of USI SPI (v2.1) as GS101. Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Exynoos990 data for SPI: - the FIFO depth is always the same size for exynos990 (64 bytes and 256 bytes), sizes of 256 bytes will be put in DT. - Exynos990 allows only accesses to 32-bit registers; otherwise, An error interrupt is generated. Perform write register accesses in 32 bits. Signed-off-by: Denzeel Oliva --- drivers/spi/spi-s3c64xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 389275dbc..d4cbbaa9a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1586,6 +1586,19 @@ static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config exynos990_spi_port_config = { + .fifo_depth = 64, + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, @@ -1664,6 +1677,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos850-spi", .data = &exynos850_spi_port_config, }, + { .compatible = "samsung,exynos990-spi", + .data = &exynos990_spi_port_config, + }, { .compatible = "samsung,exynosautov9-spi", .data = &exynosautov9_spi_port_config, }, From patchwork Wed Feb 5 22:22:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 862360 Received: from mail-ua1-f52.google.com (mail-ua1-f52.google.com [209.85.222.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E47C92206AD; Wed, 5 Feb 2025 22:25:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.52 ARC-Seal: i=1; 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Wed, 05 Feb 2025 14:25:39 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:38 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 9/9] arm64: dts: exynos990: define all PERIC USI nodes Date: Wed, 5 Feb 2025 22:22:23 +0000 Message-Id: <20250205222223.613-10-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Universal Serial Interface (USI) supports three types of serial interface such as Universal Asynchronous Receiver and Transmitter (UART), Serial Peripheral Interface (SPI), and Inter-Integrated Circuit (I2C). Each protocols can be working independently and configured as one of those using external configuration inputs. Exynos990 SoC defines 18 USI nodes in PERIC0/1 blocks. Nodes have different depths from 64-256 bytes. Signed-off-by: Denzeel Oliva --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 1711 +++++++++++++++++++++ 1 file changed, 1711 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index 9d017dbed..adecad582 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -201,12 +201,1723 @@ pinctrl_peric0: pinctrl@10430000 { interrupts = ; }; + cmu_peric0: clock-controller@10400000 { + compatible = "samsung,exynos990-cmu-peric0"; + reg = <0x10400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + + sysreg_peric0: syscon@10420000 { + compatible = "samsung,exynos990-peric0-sysreg", "syscon"; + reg = <0x10420000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PCLK>; + }; + + usi_uart: usi@105400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105400c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@10540000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10540000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi0: usi@105500c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1004>; + status = "disabled"; + + hsi2c_0: i2c@10550000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10550000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_0: spi@10550000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10550000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_2: serial@10550000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10550000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_0: usi@105600c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105600c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1008>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_1: i2c@10560000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10560000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi1: usi@105700c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x100c>; + status = "disabled"; + + hsi2c_2: i2c@10570000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10570000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_1: spi@10570000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10570000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_3: serial@10570000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10570000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_1: usi@105800c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105800c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_8>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_3: i2c@10580000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10580000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_8>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi2: usi@105900c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1014>; + status = "disabled"; + + hsi2c_4: i2c@10590000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10590000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_2: spi@10590000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10590000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_4: serial@10590000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10590000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_2: usi@105a00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105a00c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1018>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_10>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_10>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_5: i2c@105a0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105a0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c5_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_10>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi3: usi@105b00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105b00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_6: i2c@105b0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105b0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_3: spi@105b0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x105b0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_5: serial@105b0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x105b0000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_3: usi@105c00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105c00c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1020>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_12>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_12>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_7: i2c@105c0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105c0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c7_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_12>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_12>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi4: usi@105d00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105d00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1024>; + status = "disabled"; + + hsi2c_8: i2c@105d0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105d0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_4: spi@105d0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x105d0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_6: serial@105d0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x105d0000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_4: usi@105e00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105e00c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1028>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_14>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_14>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_9: i2c@105e0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105e0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c9_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_14>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_14>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi5: usi@105f00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105f00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x102c>; + status = "disabled"; + + hsi2c_10: i2c@105f0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105f0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_5: spi@105f0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x105f0000 0x30>; + interrupts = ; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_7: serial@105f0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x105f0000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_5: usi@106000c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106000c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1030>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_0>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_11: i2c@10600000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10600000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c11_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi13: usi@106300c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x103c>; + status = "disabled"; + + hsi2c_26: i2c@10630000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10630000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c26_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_13: spi@10630000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10630000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi13_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_15: serial@10630000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10630000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart15_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_13: usi@106400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106400c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1040>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_27: i2c@10640000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10640000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c27_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi14: usi@106500c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1044>; + status = "disabled"; + + hsi2c_28: i2c@10650000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10650000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c28_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_14: spi@10650000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10650000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi14_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_16: serial@10650000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10650000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart16_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_14: usi@106600c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106600c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1048>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_0>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_29: i2c@10660000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10660000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c29_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi15: usi@106700c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x104c>; + status = "disabled"; + + hsi2c_30: i2c@10670000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10670000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c30_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_15: spi@10650000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10670000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi15_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_17: serial@10670000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10670000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart17_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_15: usi@106800c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106800c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1050>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_8>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_31: i2c@10680000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10680000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c31_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_8>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10730000 0x1000>; interrupts = ; }; + cmu_peric1: clock-controller@10700000 { + compatible = "samsung,exynos990-cmu-peric1"; + reg = <0x10700000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + + sysreg_peric1: syscon@10720000 { + compatible = "samsung,exynos990-peric1-sysreg", "syscon"; + reg = <0x10720000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PCLK>; + }; + + usi_bt_uart: usi@108400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108400c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_1: serial@10840000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10840000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus_single>; + pinctrl-1 = <&uart1_bus_rts &uart1_bus_tx_con>; + pinctrl-2 = <&uart1_bus_tx_dat>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC0_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC0_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi6: usi@108a00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108a00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1018>; + status = "disabled"; + + hsi2c_12: i2c@108a0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108a0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_6: spi@108a0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x108a0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi6_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_8: serial@108a0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x108a0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_6: usi@108b00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108b00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x101c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_11>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_11>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_13: i2c@108b0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108b0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c13_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_11>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_11>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi7: usi@108c00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108c00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1020>; + status = "disabled"; + + hsi2c_14: i2c@108c0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108c0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_7: spi@108c0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x108c0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_9: serial@108c0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x108c0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_7: usi@108d00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108d00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1024>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_13>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_15: i2c@108d0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108d0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_13>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi8: usi@108e00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108e00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1028>; + status = "disabled"; + + hsi2c_16: i2c@108e0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108e0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c16_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_8: spi@108e0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x108e0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi8_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <256> + status = "disabled"; + }; + + serial_10: serial@108e0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x108e0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi_i2c_8: usi@108f00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108f00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x102c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_15>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_17: i2c@108f0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108f0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c17_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_15>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi9: usi@109000c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1030>; + status = "disabled"; + + hsi2c_18: i2c@10900000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c18_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_9: spi@10900000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10900000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <256> + status = "disabled"; + }; + + serial_11: serial@10900000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi_i2c_9: usi@109100c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1034>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_1>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_19: i2c@10910000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c19_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi10: usi@109200c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1038>; + status = "disabled"; + + hsi2c_20: i2c@10920000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c20_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_10: spi@10920000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10920000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <256> + status = "disabled"; + }; + + serial_12: serial@10920000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi_i2c_10: usi@109300c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x103c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_3>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_21: i2c@10930000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c21_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi11: usi@109400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1040>; + status = "disabled"; + + hsi2c_22: i2c@10940000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c22_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_11: spi@10940000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10940000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi11_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_13: serial@10940000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_11: usi@109500c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1044>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_5>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_23: i2c@10950000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c23_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi12: usi@109c00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109c00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x2000>; + status = "disabled"; + + hsi2c_24: i2c@109c0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109c0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c24_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_12: spi@109c0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x109c0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi12_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_14: serial@109c0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x109c0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_12: usi@109d00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109d00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x2004>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_13>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_25: i2c@109d0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109d0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c25_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_13>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi16: usi@109600c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1048>; + status = "disabled"; + + hsi2c_32: i2c@10960000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c32_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_16: spi@10960000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10960000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi16_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_18: serial@10960000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart18_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_16: usi@109700c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x104c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_7>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_7>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_33: i2c@10970000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c33_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_7>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi17: usi@109900c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1050>; + status = "disabled"; + + hsi2c_34: i2c@10990000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10990000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c34_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_17: spi@10990000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10990000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi17_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_19: serial@10990000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10990000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart19_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_17: usi@109a00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109a00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1054>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_10>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_35: i2c@10990000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10990000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c35_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi18: usi@109e00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109e00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x2008>; + status = "disabled"; + + hsi2c_36: i2c@109e0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109e0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c36_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_18: spi@109e0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x109e0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi18_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_20: serial@109e0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x109e0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart20_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_18: usi@109f00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109f00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x200c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_15>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_37: i2c@109f0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109f0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c37_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_15>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos990-cmu-hsi0"; reg = <0x10a00000 0x8000>;