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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390692bbeesm42205645e9.0.2025.02.06.03.33.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 01/16] hw/intc/xilinx_intc: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:06 +0100 Message-ID: <20250206113321.94906-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/xilinx_intc.c | 52 +++++++++++++++++------- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 3 files changed, 40 insertions(+), 14 deletions(-) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 6930f83907a..cd79ac4d4ff 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * https://docs.amd.com/v/u/en-US/xps_intc + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a) + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -49,6 +52,7 @@ struct XpsIntc { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; qemu_irq parent_irq; @@ -140,18 +144,29 @@ static void pic_write(void *opaque, hwaddr addr, update_irq(p); } -static const MemoryRegionOps pic_ops = { - .read = pic_read, - .write = pic_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .impl = { - .min_access_size = 4, - .max_access_size = 4, +static const MemoryRegionOps pic_ops[2] = { + [0 ... 1] = { + .read = pic_read, + .write = pic_write, + .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + /* + * All XPS INTC registers are accessed through the PLB interface. + * The base address for these registers is provided by the + * configuration parameter, C_BASEADDR. Each register is 32 bits + * although some bits may be unused and is accessed on a 4-byte + * boundary offset from the base address. + */ + .min_access_size = 4, + .max_access_size = 4, + }, }, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static void irq_handler(void *opaque, int irq, int level) @@ -174,13 +189,21 @@ static void xilinx_intc_init(Object *obj) qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); - - memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc", - R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); } +static void xilinx_intc_realize(DeviceState *dev, Error **errp) +{ + XpsIntc *p = XILINX_INTC(dev); + + memory_region_init_io(&p->mmio, OBJECT(dev), + &pic_ops[p->little_endian_model], + p, "xlnx.xps-intc", + R_MAX * 4); +} + static const Property xilinx_intc_properties[] = { + DEFINE_PROP_BOOL("little-endian", XpsIntc, little_endian_model, true), DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0), }; @@ -188,6 +211,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = xilinx_intc_realize; device_class_set_props(dc, xilinx_intc_properties); } diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 8b44be75a22..cf3b9574db3 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -111,6 +111,7 @@ petalogix_ml605_init(MachineState *machine) dev = qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 2c0d8c34cd2..0506497ad0a 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -95,6 +95,7 @@ petalogix_s3adsp1800_init(MachineState *machine) 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); dev = qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); From patchwork Thu Feb 6 11:33:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862480 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78370wrv; Thu, 6 Feb 2025 03:34:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWD9TV85MCv8KZJjRu9hRMKKMZnOz45XX0dmpZMO+IWwlMS2OJL9As3lt3NPYrlVlGqLEkKrQ==@linaro.org X-Google-Smtp-Source: AGHT+IFFbTh14QVIFBYXuKWd4nOIYMsPBAcDmSMuchFFiTBLiieee4vEtQeRmnCwqfug/pAgepgL X-Received: by 2002:a05:620a:454a:b0:7be:2a68:6d79 with SMTP id af79cd13be357-7c039f98127mr1007730585a.7.1738841647471; Thu, 06 Feb 2025 03:34:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841647; cv=none; d=google.com; s=arc-20240605; b=iZ3fNs2X8KLedQQasryx0elafLL8+A89n5mRpj5DcSE+NI8Gu4zkPt8qP/YlnSqHGP Qu1GyKlwYet6na70dU/K5bpXcv21Ec1p05dVHxmQdN5We5Alk+iC6/toi3UAZeEjC/XZ OHA8m8QsYfyNXpL3owBS78rrpbFL+XQeZFSBo0N+xuULAkKfuyemd1pQkzdZKPfF5zZq JsKe5H7npBTuOX4tl3xFEaNzwWM041MYlr/1Z78Vxglxmd5sp2z0UxKUqXQJIq+9pBZ7 e+t0iNK4TIjOPIJfesIPi83TpdokVWjKQ2HCh+JP4bPeRl2YLiktQRiTFgNYpxWX34Yk p2Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aMtXKyt7uU3QP4JcjRIhfj9cVUwd73AKtJN/LO4r3Xo=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=fvquJ1DO3O/0abq8owQ1Qxomsqr/IHVjhH3wUWSBps/sAI80fmiy589t7iaxDsK6hw CjH+bUrVX9/Eps+ZCGZh3fhQZWHLxpgUThBUdhZf8TQ7vvojFf4M13UHNO1nYWtNSoSM Jd563EUYqCoFrFGc2/zhVWUexEOgZTlIdToAcYJA79kDAzYu+AYm0IQJsjYRjrVKMXVO mkcy+asfLR1Lx2qfo/9KDQ1oJv0uEUh3BqJcIyLD4e0uVM3GF3BG/8AyG3yVwDjfj4pW w2bhcyoUG6jRm4pkKpTjsUMpmo/gf+nJ0cQ0A6gd3HeYLzBb20DQUMT8YD0sV8sN703D U1aA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="HPhrRp/a"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d7c7sm51664645e9.14.2025.02.06.03.33.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 02/16] hw/net/xilinx_ethlite: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:07 +0100 Message-ID: <20250206113321.94906-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + hw/net/xilinx_ethlite.c | 20 ++++++++++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 0506497ad0a..fbf52ba8f2f 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -121,6 +121,7 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); dev = qdev_new("xlnx.xps-ethernetlite"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 14bf2b2e17a..103e53831a7 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -90,6 +90,7 @@ struct XlnxXpsEthLite NICState *nic; NICConf conf; + bool little_endian_model; uint32_t c_tx_pingpong; uint32_t c_rx_pingpong; unsigned int port_index; /* dual port RAM index */ @@ -183,10 +184,10 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, } } -static const MemoryRegionOps eth_porttx_ops = { +static const MemoryRegionOps eth_porttx_ops[2] = { + [0 ... 1] = { .read = port_tx_read, .write = port_tx_write, - .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, @@ -195,6 +196,9 @@ static const MemoryRegionOps eth_porttx_ops = { .min_access_size = 4, .max_access_size = 4, }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size) @@ -232,10 +236,10 @@ static void port_rx_write(void *opaque, hwaddr addr, uint64_t value, } } -static const MemoryRegionOps eth_portrx_ops = { +static const MemoryRegionOps eth_portrx_ops[2] = { + [0 ... 1] = { .read = port_rx_read, .write = port_rx_write, - .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, @@ -244,6 +248,9 @@ static const MemoryRegionOps eth_portrx_ops = { .min_access_size = 4, .max_access_size = 4, }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static bool eth_can_rx(NetClientState *nc) @@ -328,7 +335,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) BUFSZ_MAX, &error_abort); memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf); memory_region_init_io(&s->port[i].txio, OBJECT(dev), - ð_porttx_ops, s, + ð_porttx_ops[s->little_endian_model], s, i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", 4 * TX_MAX); memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0, @@ -340,7 +347,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i, &s->port[i].rxbuf); memory_region_init_io(&s->port[i].rxio, OBJECT(dev), - ð_portrx_ops, s, + ð_portrx_ops[s->little_endian_model], s, i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", 4 * RX_MAX); memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0, @@ -363,6 +370,7 @@ static void xilinx_ethlite_init(Object *obj) } static const Property xilinx_ethlite_properties[] = { + DEFINE_PROP_BOOL("little-endian", XlnxXpsEthLite, little_endian_model, true), DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1), DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1), DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf), From patchwork Thu Feb 6 11:33:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862493 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp79045wrv; Thu, 6 Feb 2025 03:35:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUyDs70vHelpGTUEly6zlezXQ66ODIi51tTOz0SBbjdX7wUAEdagfiUnwjhaJL6K/WHClC6Mw==@linaro.org X-Google-Smtp-Source: AGHT+IE6xKzUdldGhv68RO+d5Nv/DXmZc96ZMXFKPuMaJqQi25V3lEVu2FDrs4/gs2pRFRcVd9Dp X-Received: by 2002:a05:6214:20a3:b0:6dd:84b7:dd86 with SMTP id 6a1803df08f44-6e42fc4aebamr108475256d6.36.1738841747112; Thu, 06 Feb 2025 03:35:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841747; cv=none; d=google.com; s=arc-20240605; b=hbW9Vl9LhKgbuL2h+9Xi2kE3i4ve7j0Il+sxCcv8dQhaqV1JuKHHin3m5i8B50eqFn F7h3OWdGTOKd3nj/Je9OzfCGREFW7yb9R9cIrXeE7oTThlt+y1e9plQ5XQ2fqhVruJaW nmMmWO/AKO5zu1EDFXAdv3crvpiKbkSdEUh8wtYOFPIzBhoBdQf0aN8ka0txFQa4DSzW 9dOnxRs2tz4tGZ3GblEIXl7M774Tf/Qolwu9LPCZT+xkIc+34rNdw1Rhmeox6G/5WiFY JZpNbuKLzioTzlpiHUd8Jt+Xie+UcpghvZyz+qaew0Y1myeSbxRxOJbDOTFtbrerb7As FXVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4hjV9qje+F9WM+1u7JaIIDgc7g6v/WUaxTXGCOTYvnI=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=iDgPmGtzHvcwcGbB1mq/fn7o45sBpUoL3auCDUgKaReXP9NWAQqj1asnH6dBqaktfb P4d7z/mTXNZtr4vCJWK+oF14VY4jKrkwHHTnHMIQV42RBuXfBC6g6RATddQ1Eh6Y+7pM h6FSiil/EqPvF57NAHK6lP5BDlnsoTART+dLtkziCGyL5yJWbpAG4eyq7Dv+Bt5tToe+ C4ZE6wvNGhjPK4BUU8Xw7kmTTQYsIQ4uhS3/XrPEXnk/6MyGkFLiqOvzeYKSFI/IZRb0 +O18bQolNR+hNKLc6YANvVYl5G2lCYV8F288XMvvVRKLK6D0mUaWzX42+mkFK3kxThIU aHGg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VPaL2ME7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0fd00sm1497546f8f.78.2025.02.06.03.33.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 03/16] hw/timer/xilinx_timer: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:08 +0100 Message-ID: <20250206113321.94906-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + hw/ppc/virtex_ml507.c | 1 + hw/timer/xilinx_timer.c | 35 +++++++++++++++--------- 4 files changed, 25 insertions(+), 13 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index cf3b9574db3..bbda70aa93b 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -127,6 +127,7 @@ petalogix_ml605_init(MachineState *machine) /* 2 timers at irq 2 @ 100 Mhz. */ dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index fbf52ba8f2f..9d4316b4036 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -114,6 +114,7 @@ petalogix_s3adsp1800_init(MachineState *machine) /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 23238119273..f87c221d076 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -230,6 +230,7 @@ static void virtex_init(MachineState *machine) /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", false); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 6595cf5f517..d942ac226e6 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS573: https://docs.amd.com/v/u/en-US/xps_timer + * LogiCORE IP XPS Timer/Counter (v1.02a) + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -69,6 +72,7 @@ struct XpsTimerState { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; qemu_irq irq; uint8_t one_timer_only; @@ -189,18 +193,21 @@ timer_write(void *opaque, hwaddr addr, timer_update_irq(t); } -static const MemoryRegionOps timer_ops = { - .read = timer_read, - .write = timer_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .impl = { - .min_access_size = 4, - .max_access_size = 4, +static const MemoryRegionOps timer_ops[2] = { + [0 ... 1] = { + .read = timer_read, + .write = timer_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static void timer_hit(void *opaque) @@ -233,8 +240,9 @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp) ptimer_transaction_commit(xt->ptimer); } - memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer", - R_MAX * 4 * num_timers(t)); + memory_region_init_io(&t->mmio, OBJECT(t), + &timer_ops[t->little_endian_model], t, + "xlnx.xps-timer", R_MAX * 4 * num_timers(t)); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio); } @@ -247,6 +255,7 @@ static void xilinx_timer_init(Object *obj) } static const Property xilinx_timer_properties[] = { + DEFINE_PROP_BOOL("little-endian", XpsTimerState, little_endian_model, true), DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000), DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0), }; From patchwork Thu Feb 6 11:33:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862482 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78373wrv; Thu, 6 Feb 2025 03:34:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUF3DX8+vwqk9ofj5h61clYLVu2FVVu09nDaqRGoDTQiGN/468AbCes2HtGtELkhRvuey27qQ==@linaro.org X-Google-Smtp-Source: AGHT+IFstX846M+PNIZUFDlkdRcueVr/ni8XyMWM4ZCh2LO5Td9T5woFK7EhVMSdpXm/vY7mrQDQ X-Received: by 2002:a05:6214:4a05:b0:6d4:e0a:230e with SMTP id 6a1803df08f44-6e42fb94d26mr108306696d6.16.1738841647373; Thu, 06 Feb 2025 03:34:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841647; cv=none; d=google.com; s=arc-20240605; b=cUzagltyb/e0pvMQVL6pZCJ1x122HW7RQJIgc5KdNqktnCaDblkq6JVN969cPbglRN 6BbbKLItsfZMtv2oPnRAVAwK3DkcGkh/3OKGTQMNpXuharhGfqM2IkQ6ccPltKfKHadI /YIam1Ao2EXwcZh/RHmkiJ+UXhJSCp0nD/H+v2fhOxbwe19ExTlUHlJW5Do4fE1cjgYd r6/jJF2+XgHxa/lBziWIvL+8iIPUwByT0ESeY/QjmVjexLnbTHfwtzOeWJxr/7X+tJ1n /opxbvLs+6NW6z/3MwRutQ5JWrfz71Cyeur31CxOWmByiGP307bPf0UKdufEHZgesKsI l7sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4b8oiIF0V/wXvMZ/KNd/Z66f59JylUbcAbl8fgf5Kk8=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=hsdmlZSm1CLFH4WSvUOO0fJdyoiBAeGxYB2gjqvRaVDJjj0gtQj5864mbT0TfyeaDr +2h/LTB0A55GXYFGGhcrlgMGllf5FQEExQuqRQ5fA9gTirr9xoZRI3gF1kIkwm6TCBXk B8kgkItnqem9neoG3bAOLoZ55wLASBTaAAc3ix/oAqw8DNwRLNvBwhuIZV1osVT5sFuS X8B1qs/zFkf5b1jwThqJQEA3OaUML9/hU3zzk2fqZE0SQOAWBVF+3oBxZi4VPP18sMtV +5GshTAtF5ARD1jklb1euTdf2B7ioruhcGk35eKUUPwHR11vLHsPfnUAGUwfOganQ9fl tH9w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oKGHTp8Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d7d4sm53433895e9.10.2025.02.06.03.33.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 04/16] hw/char/xilinx_uartlite: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:09 +0100 Message-ID: <20250206113321.94906-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/char/xilinx_uartlite.c | 27 ++++++++++++++---------- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 56955e0d74a..948da4263b9 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -57,6 +57,7 @@ struct XilinxUARTLite { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; CharBackend chr; qemu_irq irq; @@ -166,17 +167,21 @@ uart_write(void *opaque, hwaddr addr, uart_update_irq(s); } -static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4 - } +static const MemoryRegionOps uart_ops[2] = { + [0 ... 1] = { + .read = uart_read, + .write = uart_write, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static const Property xilinx_uartlite_properties[] = { + DEFINE_PROP_BOOL("little-endian", XilinxUARTLite, little_endian_model, true), DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), }; @@ -214,6 +219,9 @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp) { XilinxUARTLite *s = XILINX_UARTLITE(dev); + memory_region_init_io(&s->mmio, OBJECT(dev), + &uart_ops[s->little_endian_model], + s, "xlnx.xps-uartlite", R_MAX * 4); qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, NULL, s, NULL, true); } @@ -223,9 +231,6 @@ static void xilinx_uartlite_init(Object *obj) XilinxUARTLite *s = XILINX_UARTLITE(obj); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, &uart_ops, s, - "xlnx.xps-uartlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 9d4316b4036..96aed4ed1a3 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -107,6 +107,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } dev = qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); From patchwork Thu Feb 6 11:33:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862494 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp79277wrv; Thu, 6 Feb 2025 03:36:30 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXpYjzId4LhIryzGEsjoUA6hcrRDQZbaQi02LDJNCsMRRu7NlTctV8Nolo4wEFGZQsGFalPpg==@linaro.org X-Google-Smtp-Source: AGHT+IF3mZfFF1xBKrVi8iMuxtAvtNR71/iB6BQZ6HGnyy0dDa//HYsqoqzoQffCX/tr53y8Imsn X-Received: by 2002:a05:620a:268d:b0:7b6:d5ed:6091 with SMTP id af79cd13be357-7c03a03701cmr1017594485a.45.1738841790514; Thu, 06 Feb 2025 03:36:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841790; cv=none; d=google.com; s=arc-20240605; b=UoJzxT/82U4GwGwd2C1z+h6sKGYWIhSsrqhqzss2Yytj+QEXfhFaXKpCZjWbXIJFTH lrrUlHtgfr6KGxriZcO9P6AGxlnYZSkErdpYr9aB1vh9vq6d5n1IF+KignfN4WeCCuol cUo599dPLFysvNdijEwG3vj+DDtQfEQuzxR8D/AangQY3xrzIkfhgn8bNMXM86KlDAAw NZE2psjiu9mvFAg/12/NPxQs6ymwT1c9W0s8UQSDjh4Cia6isSQ9iSpzvJNE3tRb57go /g3YeXYuz0R1dzRVgTZXuWskHlwtafHxW9bmBGV6lZtV8F11lDXwd6tCp1NAz5MbmNvt 35wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X20R65gi2tCckItv1V/R89183LZ1ZNOLWFw83d9B9RI=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=T2Ez9PpljXUHa5btFI1PW+ybJiFcWooh4FQPEEimWuCjXmtgwGCJynhE3bscdh0g1s pF5PB4m8SnhhbAMKqy7rnju1Eta+XNRFj50sM2ngsW/DhcAsrXQ+XboU+A3q0kpgH5VC X6BPSqgPbyatjczYeCwvmoWe7tezSFZZTcOJC1G2W7bmB4H6IEWuEZh9fLhHYFJCOjvB 4PDOHj1faOvaC8dq3IKnohc1NDluQGWsz04AhWlsZj7q5PNKr1CjWzF/HvZAuCkC0PPS DyM8qPOhngcdODsgukGQiZLVywQjZrSOeF2id8nHK+D34w7tCHlGjS50b6jl4KLgazOR mQhw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="fTVFry/L"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd3856fsm1476849f8f.28.2025.02.06.03.33.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 05/16] hw/ssi/xilinx_spi: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:10 +0100 Message-ID: <20250206113321.94906-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/ssi/xilinx_spi.c | 24 +++++++++++++++--------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index bbda70aa93b..a795c6385b4 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -175,6 +175,7 @@ petalogix_ml605_init(MachineState *machine) SSIBus *spi; dev = qdev_new("xlnx.xps-spi"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index fd1ff12eb1d..299004ff36d 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -83,6 +83,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI) struct XilinxSPI { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; qemu_irq irq; @@ -313,14 +314,17 @@ done: xlx_spi_update_irq(s); } -static const MemoryRegionOps spi_ops = { - .read = spi_read, - .write = spi_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } +static const MemoryRegionOps spi_ops[2] = { + [0 ... 1] = { + .read = spi_read, + .write = spi_write, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static void xilinx_spi_realize(DeviceState *dev, Error **errp) @@ -339,7 +343,8 @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->cs_lines[i]); } - memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + memory_region_init_io(&s->mmio, OBJECT(s), + &spi_ops[s->little_endian_model], s, "xilinx-spi", R_MAX * 4); sysbus_init_mmio(sbd, &s->mmio); @@ -362,6 +367,7 @@ static const VMStateDescription vmstate_xilinx_spi = { }; static const Property xilinx_spi_properties[] = { + DEFINE_PROP_BOOL("little-endian", XilinxSPI, little_endian_model, true), DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1), }; From patchwork Thu Feb 6 11:33:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862490 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78849wrv; Thu, 6 Feb 2025 03:35:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVduJGbj9X1LbiLCmnYPmUfAGRqHbu1vfvzJNSQmnZ5/YNqq+h6GcTH7PqT/jv/RwoNJuZg3Q==@linaro.org X-Google-Smtp-Source: AGHT+IHbpz8crtq2XTXpxJzythnrXKj6CN6V9WzJuO3ZfbnCjOHDxI8boYKoSI4wivcm/J4nIp2I X-Received: by 2002:a05:622a:2288:b0:46c:8336:ad8 with SMTP id d75a77b69052e-470281b83c8mr73318051cf.12.1738841720580; Thu, 06 Feb 2025 03:35:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841720; cv=none; d=google.com; s=arc-20240605; b=UmpFxoA7/5pI15wQC70jDjjfY0D/PaigDU7N2bMhTeBKBTZ8UA7G3KnxPci/VPmpJj y+XP8CxpImgixdBlXA5UkswBg+TF/YCNUOD1ZcHOPRHL6R4COAXOL6uyPzvrfYfcukj+ 34fgAGDulW8NdTh0+gcZ0gq8OanQAo83IoaosY3R9DIbS5vaCf19fAuEl/LknJZ7uVnH fjUfbZuKrOC+MctLx0wnrDSsHPCZ1zozej327NV5iKDqVcdzW9GGlx7UMg/V8OHNSwu9 jGPgy2vDVbo69j4WrM2HCcTK41AidllfdnsTe3mnhrd6zo/oMiok8nMPjjrO27CSwgah z4cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=r3g08ohEQSqeyZw6xIdCyqqo2uAlLNUZF1ZoGaNfqHI=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=VlBFIotCGyPjwSulxseaqvSn33+rcuZjMaoGZImTyzQC9YtPl6K6I0+D3yog/CKl74 HyZSSXZdy1TsjY06mvT1CqcCg7EVajxpxP96gTH94L1lCoFFs8e1ivRhIpbEYtH4voRF 4lIMx9w/p/3dbGPaDgtFiBAicydvloBIrJSY7y1o7kslTGFrP4hWpbcUIPa4G+PTFl4j a67wfy3D53u8yDg1D7OBbBmRLKysB6PGFTRhZJ+zRlW11oitPfvOqe8SgtIm9nYVeML4 idxymwKu+8TcDw6jSA7WIqGTG1+141z3BsQMTj8tozU4pf7g9GDkR5g33mN9hNU9raFS +pRQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Url+ahEy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde31ccesm1506012f8f.98.2025.02.06.03.33.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 06/16] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors Date: Thu, 6 Feb 2025 12:33:11 +0100 Message-ID: <20250206113321.94906-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When a property value is static (not provided by QMP or CLI), error shouldn't happen, otherwise it is a programming error. Therefore simplify and use &error_abort as this can't fail. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/arm/xlnx-zynqmp.c | 38 ++++++++++++-------------------------- 1 file changed, 12 insertions(+), 26 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index bd5b0dd5e76..d6022ff2d3d 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -689,16 +689,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) * - SDIO Specification Version 3.0 * - eMMC Specification Version 4.51 */ - if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { - return; - } - if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, - errp)) { - return; - } - if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { - return; - } + object_property_set_uint(sdhci, "sd-spec-version", 3, &error_abort); + object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, + &error_abort); + object_property_set_uint(sdhci, "uhs", UHS_I, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { return; } @@ -763,14 +757,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { - if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, - errp)) { - return; - } - if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma", - OBJECT(system_memory), errp)) { - return; - } + object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, + &error_abort); + object_property_set_link(OBJECT(&s->gdma[i]), "dma", + OBJECT(system_memory), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { return; } @@ -811,10 +801,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0)); - if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", - OBJECT(&s->qspi_dma), errp)) { - return; - } + object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", + OBJECT(&s->qspi_dma), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { return; } @@ -833,10 +821,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) { - if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma", - OBJECT(system_memory), errp)) { - return; - } + object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma", + OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4); qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2); From patchwork Thu Feb 6 11:33:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862487 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78700wrv; Thu, 6 Feb 2025 03:35:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWcjz+UbIkbT8AicEeru0GWc9FRfaI5v9jsHhu94dk/se8rqro8ZjOVLDIuTOLLHZ1aBRFQ8w==@linaro.org X-Google-Smtp-Source: AGHT+IFytbBRdUgZpGZKfXIpJyq4QlEzJa/kkrQ1xUHhdkkTKcy0/d4HSKyGVgN4tCf1GFUdTl8V X-Received: by 2002:a05:622a:18a6:b0:467:8765:51bb with SMTP id d75a77b69052e-4702828d326mr86786861cf.37.1738841701629; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dca34a8sm16320255e9.16.2025.02.06.03.33.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Alistair Francis Subject: [PATCH v4 07/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Date: Thu, 6 Feb 2025 12:33:12 +0100 Message-ID: <20250206113321.94906-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/microblaze/translate.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 24005f05b21..86efabb83b5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -780,13 +780,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -798,26 +798,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -829,14 +829,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -846,7 +846,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -930,13 +930,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -948,26 +948,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -979,14 +979,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swx(DisasContext *dc, arg_typea *arg) @@ -1015,7 +1015,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TEUL); + dc->mem_index, MO_TE | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Thu Feb 6 11:33:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862483 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78432wrv; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0fb31sm1496293f8f.65.2025.02.06.03.34.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 08/16] target/microblaze: Set MO_TE once in do_load() / do_store() Date: Thu, 6 Feb 2025 12:33:13 +0100 Message-ID: <20250206113321.94906-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 36 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 86efabb83b5..0d51b2c468c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -713,6 +713,8 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -780,13 +782,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -798,26 +800,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -829,14 +831,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -863,6 +865,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -930,13 +934,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -948,26 +952,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -979,14 +983,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_swx(DisasContext *dc, arg_typea *arg) From patchwork Thu Feb 6 11:33:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862486 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78639wrv; Thu, 6 Feb 2025 03:34:50 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVSOTFlmKjcGUlU/R3EZy42GpaypTXPnd/RvmGMFWXm5Md49W6fYUaUwMD5FcHsC3ZPAPqEhA==@linaro.org X-Google-Smtp-Source: AGHT+IH2j9lt6yeTUoPCOJSMsaJHgzf9k1cwWnJwnEsCCssmK0mtDL7KQ/ZsWjX23xx8cWgSlhY4 X-Received: by 2002:ad4:5ca1:0:b0:6d1:7433:3670 with SMTP id 6a1803df08f44-6e42fb997c0mr108249806d6.4.1738841690555; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dc9ffd8sm16200085e9.10.2025.02.06.03.34.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 09/16] target/microblaze: Introduce mo_endian() helper Date: Thu, 6 Feb 2025 12:33:14 +0100 Message-ID: <20250206113321.94906-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0d51b2c468c..b5389d65b2e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -708,12 +708,17 @@ static void record_unaligned_ess(DisasContext *dc, int rd, } #endif +static inline MemOp mo_endian(DisasContext *dc) +{ + return MO_TE; +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -848,7 +853,8 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, + mo_endian(dc) | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -865,7 +871,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -1019,7 +1025,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TE | MO_UL); + dc->mem_index, mo_endian(dc) | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Thu Feb 6 11:33:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862488 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78829wrv; Thu, 6 Feb 2025 03:35:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVx/VcJC6devpqZ73t8Xj8I0PjvthfIkccCYbSzrZYOAoxd4PNyyuDX1SBUgyn+d35YEB8/Ng==@linaro.org X-Google-Smtp-Source: AGHT+IGvQjADDpwWKOGecFcM77ekhQndtVmu6bTwi4BgclPdI/kRlYrF/JVYLe2l9LKfTQ8pV0BB X-Received: by 2002:a05:6214:2482:b0:6d8:aba8:8393 with SMTP id 6a1803df08f44-6e42fc98eb9mr85940476d6.44.1738841719041; Thu, 06 Feb 2025 03:35:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841719; cv=none; d=google.com; s=arc-20240605; b=P8Rtz1QxpTWWD+XVsBUb5RV/BxqjJHOcPKmqVTFAvwINakQ2ghcffMRVnK2eLBdgSq OnUtq7+7kJI23x7ZjXrZ4svHkNoTj5E4boaVjgNUer8IqSj9oKPIG0wI9KieeQdHl75n klXz7QLJ27qLyPunwhvt/o558aYhERJ0zg0idSsCs/QIZIL1M19Fuqy0PZsMCrk7jrQC FVA+Dr4npRcBlhI2k7J+uF3X3YKBY7m2VKC9Lv4Swg3mOQpQZaSVOgVsxzK7uGCFuA8+ aiANvHfCIfOQYYoUVH887IEty2nLvspk2J6QDGJicxUs3ZPZF8ul9rlGIkOoJOBtoKa8 157A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kVKpviLMTY/xpsQ4Un5x7Zpm8oUwtOVraYJxurTn7aE=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=P9ljAOOKJ5a35pXMNn/OBDa+jSl4WwvL3UB406LZ0XuK7T6PVxB1JSqc8uQOQOVUJp mTjMd/0EPh2hqjKiWs/P+44wNfDRi95Ywm4JdsKjKkrbCcy1wQd862OcpuKktdzChvzX 8/ex589tOHtG94NWzVvcUjJsD6Ql8z3PL8tTXpcHCx2UJqsggPj9MBeAyNd1zUMmAdW7 ZOgDd+RWYqIqR4OyhReJyPLP3C7U4YmrcLmoTY9bRIG5qz9MnSu6BTrpsc+aTe0YdmWK v9orUwGV2XAUTtp5FLo3CPOaHFFOXaL/NsXJIsmOd9Elp+ma2N+j4vaBKCiTaZRdBNfQ hiZg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WLG7jbEy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0fe37sm1515984f8f.69.2025.02.06.03.34.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 10/16] target/microblaze: Consider endianness while translating code Date: Thu, 6 Feb 2025 12:33:15 +0100 Message-ID: <20250206113321.94906-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/cpu.h | 7 +++++++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f6879eee352..e44ddd53078 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -414,6 +414,13 @@ void mb_translate_code(CPUState *cs, TranslationBlock *tb, /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); +static inline bool mb_cpu_is_big_endian(CPUState *cs) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + + return !cpu->cfg.endi; +} + static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b5389d65b2e..b54e5ac4b2f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -710,7 +710,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return dc->cfg->endi ? MO_LE : MO_BE; } static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, @@ -1647,7 +1647,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags_to_set = 0; - ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); + ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next, + mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN); if (!decode(dc, ir)) { trap_illegal(dc, true); } From patchwork Thu Feb 6 11:33:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862496 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp79326wrv; Thu, 6 Feb 2025 03:36:42 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX/QBhLflCkzOZxq6698V2ECUiTDNSunNDCcs8C3h8dma+1PkVAksH5sMzYtN7hn1dgNkRB+Q==@linaro.org X-Google-Smtp-Source: AGHT+IEbaefrGDF+6UQWvGH9AQxdw4lLobL3kx29e7Zq2eoeDfy7QzoKVz1R/5NyRugAw85CuULL X-Received: by 2002:ad4:5f45:0:b0:6e4:2551:7bd6 with SMTP id 6a1803df08f44-6e42fc05836mr85979886d6.26.1738841801598; Thu, 06 Feb 2025 03:36:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841801; cv=none; d=google.com; s=arc-20240605; b=g1cR0aXQRwJxxnZShaYaL80ve/qE966g8dmfgnnH6/uoXHLWbiiPJtYzMarhHLiA0I 7Ht3WXpXMXC0eAsIB0G38MgeSitW6DB79yk/dAlMCyM1fu4HQB3jSwwtA6MiGMCL6U8S EebaJMIXUYwAnJa9g/UAaMNcmCw9umZO74Wsv3ka2qQI8CjlWEiAU5qepXvZ0P2XDnvV uhNQf/IcrNfC17s2O23e039iv2N2AfI3lNKY8/fxemxJ/g4oHsNwuC/DNGuWl+oib6/r URB9a+lTV7mfPwuYBYNpKT+UjHhd6iqsPvIrVAXEsHETj40e2RUXoeYMzEjk3BVV1DBi Y4/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Y5yL8FD/exSYKs1rjCaM0CVY1gRhFjhBlCLpvUbDQjM=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=d1rLrSfMZ99ozbNPV7aHIl900wg5B2OlaR6vFG8OQ0MzMREAk+YoMZt2cUFezURbK/ BiNBrgRyoYXewZYZUpVZD63a6S5N7oOaglqWKJD2RFeC92msJ4Oror+RetHtDTXflNE/ f8BI5usXizLgaUKE0ePdehZ8MYG/QcgGQ6Nn4tmO4ixxP4V2jPxXcHhTIPKVCIFAyTY0 WuYAeI6QVqmTDjNgSDJQvHwHY0FrtDHOB6ygG/zqf6R+/ihl9vQzyuLBk4/HKcwhUGUF BZVWWBgOTws8Cb0IDWmXUuDFWuvUyqjZz+bagFRSi6mTW4fSD4W3CI5UfuNlenmP53ze /NaA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YlteEe0m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd7f18bsm1518007f8f.60.2025.02.06.03.34.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines Date: Thu, 6 Feb 2025 12:33:16 +0100 Message-ID: <20250206113321.94906-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce an abstract machine parent class which defines the 'little_endian' property. Duplicate the current machine, which endian is tied to the binary endianness, to one big endian and a little endian machine; updating the machine description. Keep the current default machine for each binary. 'petalogix-s3adsp1800' machine is aliased as: - 'petalogix-s3adsp1800-be' on big-endian binary, - 'petalogix-s3adsp1800-le' on little-endian one. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 62 +++++++++++++++++++----- 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 96aed4ed1a3..aea727eb7ee 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -55,8 +55,17 @@ #define ETHLITE_IRQ 1 #define UARTLITE_IRQ 3 +typedef struct PetalogixS3adsp1800MachineClass { + MachineClass parent_obj; + + bool little_endian; +} PetalogixS3adsp1800MachineClass; + #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ - MACHINE_TYPE_NAME("petalogix-s3adsp1800") + MACHINE_TYPE_NAME("petalogix-s3adsp1800-common") +DECLARE_CLASS_CHECKERS(PetalogixS3adsp1800MachineClass, + PETALOGIX_S3ADSP1800_MACHINE, + TYPE_PETALOGIX_S3ADSP1800_MACHINE) static void petalogix_s3adsp1800_init(MachineState *machine) @@ -71,11 +80,13 @@ petalogix_s3adsp1800_init(MachineState *machine) MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32]; MemoryRegion *sysmem = get_system_memory(); + PetalogixS3adsp1800MachineClass *pmc; + pmc = PETALOGIX_S3ADSP1800_MACHINE_GET_CLASS(machine); cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); object_property_set_bool(OBJECT(cpu), "little-endian", - !TARGET_BIG_ENDIAN, &error_abort); + pmc->little_endian, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort); /* Attach emulated BRAM through the LMB. */ @@ -95,7 +106,7 @@ petalogix_s3adsp1800_init(MachineState *machine) 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); dev = qdev_new("xlnx.xps-intc"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -107,7 +118,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } dev = qdev_new(TYPE_XILINX_UARTLITE); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); @@ -115,7 +126,7 @@ petalogix_s3adsp1800_init(MachineState *machine) /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_new("xlnx.xps-timer"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -123,7 +134,7 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); dev = qdev_new("xlnx.xps-ethernetlite"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); @@ -133,26 +144,55 @@ petalogix_s3adsp1800_init(MachineState *machine) create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); - microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, + microblaze_load_kernel(cpu, pmc->little_endian, ddr_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); } -static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data) +static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, + bool little_endian) { MachineClass *mc = MACHINE_CLASS(oc); + PetalogixS3adsp1800MachineClass *pmc = PETALOGIX_S3ADSP1800_MACHINE_CLASS(oc); - mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; mc->init = petalogix_s3adsp1800_init; - mc->is_default = true; + pmc->little_endian = little_endian; + mc->desc = little_endian + ? "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (little endian)" + : "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (big endian)"; + if (little_endian == !TARGET_BIG_ENDIAN) { + mc->is_default = true; + mc->alias = "petalogix-s3adsp1800"; + } +} + +static void petalogix_s3adsp1800_machine_class_init_be(ObjectClass *oc, void *data) +{ + petalogix_s3adsp1800_machine_class_init(oc, false); +} + +static void petalogix_s3adsp1800_machine_class_init_le(ObjectClass *oc, void *data) +{ + petalogix_s3adsp1800_machine_class_init(oc, true); } static const TypeInfo petalogix_s3adsp1800_machine_types[] = { { .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE, .parent = TYPE_MACHINE, - .class_init = petalogix_s3adsp1800_machine_class_init, + .abstract = true, + .class_size = sizeof(PetalogixS3adsp1800MachineClass), + }, + { + .name = MACHINE_TYPE_NAME("petalogix-s3adsp1800-be"), + .parent = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init_be, + }, + { + .name = MACHINE_TYPE_NAME("petalogix-s3adsp1800-le"), + .parent = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init_le, }, }; From patchwork Thu Feb 6 11:33:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862485 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78561wrv; Thu, 6 Feb 2025 03:34:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVhazFeGSUDRqUIfptTQdN6dxcpvHh9bNcZLdHEyElfNNI4qQY4Dm5H9YKYmXb5qvfwwL8cSA==@linaro.org X-Google-Smtp-Source: AGHT+IHkR71UR3j+zhzFvUhCemLGo7GrihSF3BtM8yx4QmzE5fNjaD5TtHp5bGJKlk4nQN8pSTmK X-Received: by 2002:ad4:5ce9:0:b0:6d8:8a60:ef2c with SMTP id 6a1803df08f44-6e42fb6a6a3mr100942726d6.2.1738841679528; Thu, 06 Feb 2025 03:34:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841679; cv=none; d=google.com; s=arc-20240605; b=cQSeywjIIyVN2r+K+Cs+bEvgUNz+EHrxUYyBgFAN0pEJx5N5nDBkCLtHzQsARoj0Lb 8GpnRwvlzrYEkueSweJ907j1PMxUkPv+4TDUckLGn3TWgZO+I+waLqIf3TsDFF8CH2/R oVYySKekObtm0Zq3cm9/hBFqt3OefWAmb04/qQB477EbvksMJzoGrxWR3ihK/cNSXd+E 2S5DpQ5htTe5vbaiVNYwsW8NcRwHhFYJE97EvmzqQ/8SS4b3YvE4TGcOHM64NO7q24b6 hwmQeZ4lTyZC84FA+MUNzxJuurTdROpBlrLyMHjcbjnXf7SX5uDialMzoGu5kdv+6PAi XcBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2lrz/Z9U2Uf5jpDeQ6Q5rMzyggw9C9+W1C5t50i9qAk=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=FDleDEY5mN/yJ6A0zbv1lgFPKXc11PxAmrBeZlKeLiIzdicn7e3KTcLxvgXnL9raIy 9wkBo2yWJ2e0RP2WYXmlZRCzF9fS15GikfkIuEFVbR6vjhIFgvX/8Ld5gK9dQLD5hGRl kMSgGrsXjcKfqtRVF7HD7qKXxW+1w82ki2/ptPXTyput82nNAKxwPRNxr4vcDr5bgsii JVeKeGAdgG6r/dLZN5Xt3+UbqhqTGcPfgyBqhgOkBq2FDkUAvkVsLaGtVHntZfzNs90G +YLo17hswO8AamUaSHHCz19cYAfr/N3FeT21SWHRbWUXbZPQZrsMb+ptlC+wxBQT5pX+ m4Gg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NAz9wARY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc33939f3sm487320f8f.17.2025.02.06.03.34.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 12/16] tests/functional: Explicit endianness of microblaze assets Date: Thu, 6 Feb 2025 12:33:17 +0100 Message-ID: <20250206113321.94906-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The archive used in test_microblaze_s3adsp1800.py (testing a big-endian target) contains a big-endian kernel. Rename using the _BE suffix. Similarly, the archive in test_microblazeel_s3adsp1800 (testing a little-endian target) contains a little-endian kernel. Rename using _LE suffix. These changes will help when adding cross-endian kernel tests. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 6 +++--- tests/functional/test_microblazeel_s3adsp1800.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 2c4464bd05a..fac364b1ea9 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -15,14 +15,14 @@ class MicroblazeMachine(QemuSystemTest): timeout = 90 - ASSET_IMAGE = Asset( + ASSET_IMAGE_BE = Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') - def test_microblaze_s3adsp1800(self): + def test_microblaze_s3adsp1800_be(self): self.set_machine('petalogix-s3adsp1800') - self.archive_extract(self.ASSET_IMAGE) + self.archive_extract(self.ASSET_IMAGE_BE) self.vm.set_console() self.vm.add_args('-kernel', self.scratch_file('day17', 'ballerina.bin')) diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index c382afe6bfa..5d353dba5d2 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -17,14 +17,14 @@ class MicroblazeelMachine(QemuSystemTest): timeout = 90 - ASSET_IMAGE = Asset( + ASSET_IMAGE_LE = Asset( ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') - def test_microblazeel_s3adsp1800(self): + def test_microblazeel_s3adsp1800_le(self): self.require_netdev('user') self.set_machine('petalogix-s3adsp1800') - self.archive_extract(self.ASSET_IMAGE) + self.archive_extract(self.ASSET_IMAGE_LE) self.vm.set_console() self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) tftproot = self.scratch_file('day13') From patchwork Thu Feb 6 11:33:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862489 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78834wrv; Thu, 6 Feb 2025 03:35:19 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUK+JlithPQLTh/uN2wWBno9k4bAnviLAsEJcjA8scf/HsiXo6wRoXzsLFWukhQRq5NMujrQg==@linaro.org X-Google-Smtp-Source: AGHT+IFA48Opno5vA7qc394ey2dHlN+19P8//SPMqvFyUZ1n3UdhIou6MAWMAaQV/kky9ikaioi6 X-Received: by 2002:a05:622a:1826:b0:46c:7651:158c with SMTP id d75a77b69052e-470282f1ee9mr68397101cf.48.1738841719039; Thu, 06 Feb 2025 03:35:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841719; cv=none; d=google.com; s=arc-20240605; b=hfnsxOYwVEFS+AGMACUI26uNd946141j1MLOy2gh8fQk39UXHnJbl/qIPag+/cotXP /q7KxjGRJp/EHOjG6Zpn0SjNdejkFME5tGYtSZMw6MI4+jWy8aSWYamYlkaRfXPUX/cH cXwbjRgqoks6FQrKIvD4qYWqHzG6JCEQFjWkKP31aSALVGRiHansImtOcKkT4ONjUFZf jvVDPZCXGfBcTyD6TpGZiVRTRj0wAstmHUVaWDUIml/oGG1tkQI7+7xe8fe7/SVoxaIk vzoMxFcVWFjDDinbjb+a+kXumnPE8QMYzujQM+uYkAnr7Onu3on35Cy8sYUa263Q8ZQB YvXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zUtqHHDNY10ErvkSPLlzoR4cOpr1l8H4w8NugOOncxc=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=a/7n7umUJ1dq1Qce5c1AITExFfoTqL5JdzjjJGXg7LgH077uQMwZopYrVUHPFCELkz ezkgHAAJF6741BNAsnnDws6x0fQEnMZ/yG8YNzXkDDqzkpiBwacolmRStvt8Hz+EQRyA 2lETAe1z8hlnUHkMhsPiHkPZqqnG9VzsRLXXzLSSWpzN7z/LvI4Rrfer7G3p3uw9Dgoi FqD+pGN57KTGlQu6Y/3wR4vSJVYRTTcPAxCXatORH7jq9Qb118WzPs1+yUAg9DXW8ryK fC+bTIwEVdh8tyuzP+zvzzfFNMkrCk+5FLeYLhs2m63EFBeqr8ZZ0uh8HopTRU30UGG+ 1c6w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gejhkmtE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd4b154sm1521480f8f.38.2025.02.06.03.34.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 13/16] tests/functional: Allow microblaze tests to take a machine name argument Date: Thu, 6 Feb 2025 12:33:18 +0100 Message-ID: <20250206113321.94906-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Make microblaze tests a bit more generic. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 7 +++++-- tests/functional/test_microblazeel_s3adsp1800.py | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index fac364b1ea9..c4226f49cf3 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -20,8 +20,8 @@ class MicroblazeMachine(QemuSystemTest): 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') - def test_microblaze_s3adsp1800_be(self): - self.set_machine('petalogix-s3adsp1800') + def do_ballerina_be_test(self, machine): + self.set_machine(machine) self.archive_extract(self.ASSET_IMAGE_BE) self.vm.set_console() self.vm.add_args('-kernel', @@ -34,5 +34,8 @@ def test_microblaze_s3adsp1800_be(self): # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... + def test_microblaze_s3adsp1800_legacy_be(self): + self.do_ballerina_be_test('petalogix-s3adsp1800') + if __name__ == '__main__': QemuSystemTest.main() diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index 5d353dba5d2..715ef3f79ac 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -21,9 +21,9 @@ class MicroblazeelMachine(QemuSystemTest): ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') - def test_microblazeel_s3adsp1800_le(self): + def do_xmaton_le_test(self, machine): self.require_netdev('user') - self.set_machine('petalogix-s3adsp1800') + self.set_machine(machine) self.archive_extract(self.ASSET_IMAGE_LE) self.vm.set_console() self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) @@ -38,5 +38,8 @@ def test_microblazeel_s3adsp1800_le(self): 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', '821cd3cab8efd16ad6ee5acc3642a8ea') + def test_microblaze_s3adsp1800_legacy_le(self): + self.do_xmaton_le_test('petalogix-s3adsp1800') + if __name__ == '__main__': QemuSystemTest.main() From patchwork Thu Feb 6 11:33:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862491 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78851wrv; Thu, 6 Feb 2025 03:35:21 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXdf9npupr7ulH3h8P1pXv/wIKALivb564FihXBLhQCFn8BZuaUMcvfZ6f5Lg47B2mnaOdHhA==@linaro.org X-Google-Smtp-Source: AGHT+IE1M1Q0+VluLp0XgE7edjxnkukLhRjoltdAJ8tZOPncUGqCd7kzZQn8/IDKGjt+LXpl2t5N X-Received: by 2002:ad4:574f:0:b0:6e4:3fb2:538a with SMTP id 6a1803df08f44-6e43fb255f5mr10686206d6.42.1738841720858; Thu, 06 Feb 2025 03:35:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841720; cv=none; d=google.com; s=arc-20240605; b=fVuRqwgfunPV0a05b6OLj6emgfp1YczmRHkrqoFUrr+anPFygnlxt7qaBFLVGt9G2t +RT6YzffG6pJ7FM1KxCpBX+F6sphYs32lOVb1jeaFX6OgeYTMqbl/Nq1olliMzwMHYgY R8u2/hAacs8XBPg2udpB0448iasVCWde6+HO0PcTTkbFuQ5IG0o31HkSDXV5MPzXlXQK R6uidmZudWbzhApOaWwGQL41l3JDQfXkGGYfBNXbpOS0LqCFIncN6MUCbg1GGrc7m/5W 7BdrLvh/dhX5VfmYq4TFLTMMvQUoaHQffk6rG1BuePaqBR4CKiDy3ZjNqLk/pylsfNvU Prxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ppn20+OdDHYYHHj4mqusBuIEfs+xIwJ4iZjJotRYm4c=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=AH+zb0kWs4o1ojaGZJGGbk8U/Vgi00lnql2y4uw85QOSpHhLcPlQc8O1SGQ4WsWcWw 30HDQJmXItFwZgVAG3bwuHj2jmhnOgwzbNSIBiRWFWpebomarEdkiLA5sYC1dhWPfrzG ehuST27N8M4feo7jeY2Y/kKRKmx1B9HLno+vhcRAYgmcPv3UArweM1MGZDUTRU2SHqML Flp1II2OoQYLADCI7NQtWZj0/8FA/jxeG8s+fD0rRZzqO2XPCj7tIo2JcjG2SuCz5XKb ThfmFHCSjAEGyrXRVFvi2P9ZbB9MVhP8D8R3QDHGtjeEJvMq5yo/koOY0fzRsOSgZNDU zMWw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=joyjvxsv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd5c87csm1531231f8f.52.2025.02.06.03.34.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 14/16] tests/functional: Have microblaze tests inherit common parent class Date: Thu, 6 Feb 2025 12:33:19 +0100 Message-ID: <20250206113321.94906-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the MicroblazeMachine class being common to both MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine classes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 2 ++ tests/functional/test_microblazeel_s3adsp1800.py | 5 ++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index c4226f49cf3..2eff31f13a7 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -15,6 +15,8 @@ class MicroblazeMachine(QemuSystemTest): timeout = 90 +class MicroblazeBigEndianMachine(MicroblazeMachine): + ASSET_IMAGE_BE = Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index 715ef3f79ac..a3e8d7ca48e 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -12,10 +12,9 @@ from qemu_test import QemuSystemTest, Asset from qemu_test import wait_for_console_pattern +from test_microblaze_s3adsp1800 import MicroblazeMachine -class MicroblazeelMachine(QemuSystemTest): - - timeout = 90 +class MicroblazeLittleEndianMachine(MicroblazeMachine): ASSET_IMAGE_LE = Asset( ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), From patchwork Thu Feb 6 11:33:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862492 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp78888wrv; Thu, 6 Feb 2025 03:35:28 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW0t2cfWQLScE2WD8xwFR/mGSshfI+W2u+tPaia4nklm4q14amckkejZCYcnEKfG9tN3u5TKg==@linaro.org X-Google-Smtp-Source: AGHT+IH8fhss3g64Qd95FvGmOpboh5aaHl5YvC9swwx4xZg5rgpoHrLw1fQ67jrJnAat432tmW6D X-Received: by 2002:a05:622a:1aaa:b0:467:67d3:7c8f with SMTP id d75a77b69052e-470281a4c38mr99904081cf.21.1738841728694; Thu, 06 Feb 2025 03:35:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841728; cv=none; d=google.com; s=arc-20240605; b=RmshLkpgiQXGMKeG288W2en36C/xDPvy4Tt88t1bkGAbPSLYoGkcRbpUuIGLRJn4d9 j9Ri8ohhUh6MZUr+g7oUo+N5JBqgzI+TJ2ToJEB81mYT+PWZ4GQWd3kuTI7j7Ue9AUuy JO14lCEIYkBNmCleg1kywjpPJL7Gg0dU8X0ihzO/xo6hb7q6r4QPEDL8F6RP5T1rNXpO jEzfSlQVmohqXztnuXSvzkNU9WETBdsuGodpJO0hgf4ri4hiMBq3sMdPh4ezc/aiY2Se opQvTyHCfUvc8lRH5gc+nQng2xxWwqLrObGepvFFGdNUvSVB6iMuomEEngjzDOARdGas DRBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yAMhBvq7A2sY4fwGEsHhx6BSBdhRyxbY21rGxZGSxvM=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=gHxb6IPJY3mnv4kfarjBIiNe8h/AgZUaj0bHEAnFNZJcz70DTH62FAxC+LOUYH0M6O adCKxRxevlnNbgrp1BWz41hik7O8b5iKE5fEURKhfZ6OAlGcRMO/lqbYdBnqDnCFsWTF 5hpTZoQjyMrZCNKVIL6Xh59VBV48qjFbeiU4cKhuaDgn5VaiyXEuv+9EPE4ToGpXj4z1 anXfGqEhu+XxXi1suDGw7kb1+Un3SLXsYdWH243X/KYVdhd3IOADgS5mzLWA9Y4htNaT HgYKXVh5+IgVBg+MhjS2P4aMGjEoXNPMtr4vp7QohddpxNwnCfoRaIknTIG88ZcNYNEU lPQQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ocTCYsG5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8047sm16124075e9.33.2025.02.06.03.34.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 15/16] tests/functional: Move microblaze tests to common parent class Date: Thu, 6 Feb 2025 12:33:20 +0100 Message-ID: <20250206113321.94906-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the xmaton and ballerina tests to the parent class. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- .../functional/test_microblaze_s3adsp1800.py | 27 +++++++++++++++++-- .../test_microblazeel_s3adsp1800.py | 26 +----------------- 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 2eff31f13a7..0447097c048 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -7,6 +7,8 @@ # This work is licensed under the terms of the GNU GPL, version 2 or # later. See the COPYING file in the top-level directory. +import time +from qemu_test import exec_command, exec_command_and_wait_for_pattern from qemu_test import QemuSystemTest, Asset from qemu_test import wait_for_console_pattern @@ -15,13 +17,15 @@ class MicroblazeMachine(QemuSystemTest): timeout = 90 -class MicroblazeBigEndianMachine(MicroblazeMachine): - ASSET_IMAGE_BE = Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') + ASSET_IMAGE_LE = Asset( + ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), + 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') + def do_ballerina_be_test(self, machine): self.set_machine(machine) self.archive_extract(self.ASSET_IMAGE_BE) @@ -36,6 +40,25 @@ def do_ballerina_be_test(self, machine): # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... + def do_xmaton_le_test(self, machine): + self.require_netdev('user') + self.set_machine(machine) + self.archive_extract(self.ASSET_IMAGE_LE) + self.vm.set_console() + self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) + tftproot = self.scratch_file('day13') + self.vm.add_args('-nic', f'user,tftp={tftproot}') + self.vm.launch() + wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') + time.sleep(0.1) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, + 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', + '821cd3cab8efd16ad6ee5acc3642a8ea') + +class MicroblazeBigEndianMachine(MicroblazeMachine): + def test_microblaze_s3adsp1800_legacy_be(self): self.do_ballerina_be_test('petalogix-s3adsp1800') diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index a3e8d7ca48e..56645bd0bb2 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -7,36 +7,12 @@ # This work is licensed under the terms of the GNU GPL, version 2 or # later. See the COPYING file in the top-level directory. -import time -from qemu_test import exec_command, exec_command_and_wait_for_pattern -from qemu_test import QemuSystemTest, Asset -from qemu_test import wait_for_console_pattern +from qemu_test import QemuSystemTest from test_microblaze_s3adsp1800 import MicroblazeMachine class MicroblazeLittleEndianMachine(MicroblazeMachine): - ASSET_IMAGE_LE = Asset( - ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), - 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') - - def do_xmaton_le_test(self, machine): - self.require_netdev('user') - self.set_machine(machine) - self.archive_extract(self.ASSET_IMAGE_LE) - self.vm.set_console() - self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) - tftproot = self.scratch_file('day13') - self.vm.add_args('-nic', f'user,tftp={tftproot}') - self.vm.launch() - wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') - time.sleep(0.1) - exec_command(self, 'root') - time.sleep(0.1) - exec_command_and_wait_for_pattern(self, - 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', - '821cd3cab8efd16ad6ee5acc3642a8ea') - def test_microblaze_s3adsp1800_legacy_le(self): self.do_xmaton_le_test('petalogix-s3adsp1800') From patchwork Thu Feb 6 11:33:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862495 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp79290wrv; Thu, 6 Feb 2025 03:36:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWb4XhNhQRk3fVLcaRTo3RZui5GIObRKHB/nWyrZLA3sNpcTzXrTLpF2R9dKbIVuM+gS/dI6A==@linaro.org X-Google-Smtp-Source: AGHT+IFNLn0t35DHDKZdIu2vcv8P0yA5ngp4svhMZdlLNSPeQQ7ZRhVoLr6HavFvrXvDbVFq6x1S X-Received: by 2002:a05:6214:2482:b0:6df:97ba:4f7a with SMTP id 6a1803df08f44-6e42fca5385mr93995106d6.33.1738841793251; Thu, 06 Feb 2025 03:36:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738841793; cv=none; d=google.com; s=arc-20240605; b=I7XeE9LhtGF2EKh+TDoGKur3m+xo+4Tl5V7tkR+U0lpOOjyPGiHUkYb+Hc5Smw7CEJ 2DyDs0tbHwF1yg8d2je68IDYaE1CBLqegOLywo2ZgvAXYH0i42jRlLFjBmqwsvK9ZNVs XHproIn91BET53JbQ6QtDJkiylqMrcxBLSqyG1Vk8Dl+y572I/6NrAW13k2T6m9AujHW qfWb3b4RA/XNjehk42DdD9MPRfdKR9EUv1rkbCjyuUQsgmwcRDYOLUnszvhJn5XFGBpF Yx6NgKR3FDCSU8zCMIaYA25LmlShXA957qvLNNpA0U18YzFVJmogl1+Qpqgd7hwXWkSz X/CA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mb4oxd/vwXhE6pcy1gQ3cwUL95fH15TJV9xJOH6RkVw=; fh=KB7JHaNjI5K4DpKM/QhtRxZS6iSNZtGQL2GKAsTumMw=; b=LHm8F5n+oDzG2cfsaXq++NServsmS9PPG7jHLYTwNWug0VPQ6u7KXxsr0udAcD67jn 54yUquj4j/PtgMYctWMijtY81gwufrx8yHBCWge6g9B3D81RdS3xQJWcP7SdchoXuLvp joF3MPgbMx1h+wfAbWAx29x33hPAK+lyotK+viDsKlb8KQ1SByfgzkAiYy/qMcgbBm5A jsb6LfmF9ztnwu4cpLmS3f7g5gldzis6xC3yU+qrHTR7dzvFQdGBd1b5AqXvg0qEK5vM vGTR+QDmzUmMAGNmkxDM0TA8zBU5MX1PvloMZaa2r03x4EbeTpuRPDnzkya6pSoVOC9A MfTg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PlPF0GDr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd55656sm1517180f8f.50.2025.02.06.03.34.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 16/16] tests/functional: Run cross-endian microblaze tests Date: Thu, 6 Feb 2025 12:33:21 +0100 Message-ID: <20250206113321.94906-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Ensure microblaze machines can run cross-endianness by running all tests on all machines. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 6 ++++++ tests/functional/test_microblazeel_s3adsp1800.py | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 0447097c048..f955f6f4021 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -62,5 +62,11 @@ class MicroblazeBigEndianMachine(MicroblazeMachine): def test_microblaze_s3adsp1800_legacy_be(self): self.do_ballerina_be_test('petalogix-s3adsp1800') + def test_microblaze_s3adsp1800_be(self): + self.do_ballerina_be_test('petalogix-s3adsp1800-be') + + def test_microblaze_s3adsp1800_le(self): + self.do_xmaton_le_test('petalogix-s3adsp1800-le') + if __name__ == '__main__': QemuSystemTest.main() diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index 56645bd0bb2..b10944bbb0c 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -16,5 +16,11 @@ class MicroblazeLittleEndianMachine(MicroblazeMachine): def test_microblaze_s3adsp1800_legacy_le(self): self.do_xmaton_le_test('petalogix-s3adsp1800') + def test_microblaze_s3adsp1800_le(self): + self.do_xmaton_le_test('petalogix-s3adsp1800-le') + + def test_microblaze_s3adsp1800_be(self): + self.do_ballerina_be_test('petalogix-s3adsp1800-be') + if __name__ == '__main__': QemuSystemTest.main()